* [PATCH 2/2] clk: aspeed: add AST2700 PECI clock
From: Ryan Chen @ 2026-06-24 5:45 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery
Cc: linux-clk, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, Ryan Chen
In-Reply-To: <20260624-peci_clk-v1-0-ee28b92e22e9@aspeedtech.com>
Register the SoC1 PECI clock as a mux selected by SCU1_CLK_SEL2 bit 16,
choosing between the 25MHz CLKIN and HPLL/4. Add the HPLL/4 fixed factor
clock to serve as the second mux parent.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
drivers/clk/aspeed/clk-ast2700.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/aspeed/clk-ast2700.c b/drivers/clk/aspeed/clk-ast2700.c
index 8b7b382f6f3e..5f499ec0e1d1 100644
--- a/drivers/clk/aspeed/clk-ast2700.c
+++ b/drivers/clk/aspeed/clk-ast2700.c
@@ -273,6 +273,13 @@ static const unsigned int sdclk_parent_ids[] = {
static const struct clk_hw *sdclk_parent_hws[ARRAY_SIZE(sdclk_parent_ids)];
+static const unsigned int peciclk_parent_ids[] = {
+ SCU1_CLKIN,
+ SCU1_CLK_HPLL_DIV4
+};
+
+static const struct clk_hw *peciclk_parent_hws[ARRAY_SIZE(peciclk_parent_ids)];
+
#define FIXED_CLK(_id, _name, _rate) \
{ \
.id = _id, \
@@ -458,6 +465,7 @@ static const struct ast2700_clk_info ast2700_scu1_clk_info[] __initconst = {
PLL_CLK(SCU1_CLK_HPLL, CLK_PLL, "soc1-hpll", SCU1_CLKIN, SCU1_HPLL_PARAM),
PLL_CLK(SCU1_CLK_APLL, CLK_PLL, "soc1-apll", SCU1_CLKIN, SCU1_APLL_PARAM),
PLL_CLK(SCU1_CLK_DPLL, CLK_PLL, "soc1-dpll", SCU1_CLKIN, SCU1_DPLL_PARAM),
+ FIXED_FACTOR_CLK(SCU1_CLK_HPLL_DIV4, "soc1-hpll_div4", SCU1_CLK_HPLL, 1, 4),
FIXED_FACTOR_CLK(SCU1_CLK_APLL_DIV2, "soc1-apll_div2", SCU1_CLK_APLL, 1, 2),
FIXED_FACTOR_CLK(SCU1_CLK_APLL_DIV4, "soc1-apll_div4", SCU1_CLK_APLL, 1, 4),
FIXED_FACTOR_CLK(SCU1_CLK_CAN, "canclk", SCU1_CLK_APLL, 1, 10),
@@ -481,6 +489,8 @@ static const struct ast2700_clk_info ast2700_scu1_clk_info[] __initconst = {
uxclk_parent_hws, SCU1_CLK_SEL2, 0, 2),
MUX_CLK(SCU1_CLK_HUXCLK, "huxclk", uxclk_parent_ids, ARRAY_SIZE(uxclk_parent_ids),
uxclk_parent_hws, SCU1_CLK_SEL2, 3, 2),
+ MUX_CLK(SCU1_CLK_PECI, "peciclk", peciclk_parent_ids, ARRAY_SIZE(peciclk_parent_ids),
+ peciclk_parent_hws, SCU1_CLK_SEL2, 16, 1),
DIVIDER_CLK(SCU1_CLK_SDCLK, "sdclk", SCU1_CLK_SDMUX,
SCU1_CLK_SEL1, 14, 3, ast2700_clk_div_table),
PLL_CLK(SCU1_CLK_UARTX, CLK_UART_PLL, "uartxclk", SCU1_CLK_UXCLK, SCU1_UXCLK_CTRL),
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/2] arm64: dts: socfpga: agilex72: Add initial device tree
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 5:56 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
In-Reply-To: <20260624055644.7508-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Add initial device tree support for the Intel SoCFPGA Agilex72
platform. This introduces the SoC DTSI and the SoCDK board DTS as
the first upstream submission for this platform.
The Agilex72 SoC features a heterogeneous CPU cluster with
Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for
memory management.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Rename platform from agilex7-gen2 to agilex72
- Add arm,armv8-timer node (was mistakenly removed in v1); other
review comments from Shashiko are either addressed or confirmed as false positives
consistent with existing SoCFPGA platform conventions
---
arch/arm64/boot/dts/intel/Makefile | 1 +
.../boot/dts/intel/socfpga_agilex72.dtsi | 128 ++++++++++++++++++
.../boot/dts/intel/socfpga_agilex72_socdk.dts | 15 ++
3 files changed, 144 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 088a03b89c99..270c70fdf084 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex5_socdk_013b.dtb \
socfpga_agilex5_socdk_modular.dtb \
socfpga_agilex5_socdk_nand.dtb \
+ socfpga_agilex72_socdk.dtb \
socfpga_agilex7m_socdk.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
new file mode 100644
index 000000000000..2a4ad4130f37
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+/dts-v1/;
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "intel,socfpga-agilex72";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ atf_reserved: atf@80000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80000000 0x0 0x100000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ service_reserved: svcbuffer@80100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x80100000 0x0 0xf00000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a520";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a520";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a720";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a720";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ intc: interrupt-controller@7000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x7000000 0x0 0x10000>,
+ <0x0 0x7080000 0x0 0x100000>;
+ ranges;
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x40000>;
+
+ its: msi-controller@7040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x7040000 0x0 0x20000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ soc: soc@0 {
+ compatible = "simple-bus";
+ ranges = <0 0 0 0xffffffff>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+
+ smmu: iommu@c100000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0c100000 0x30000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "gerror", "priq";
+ dma-coherent;
+ #iommu-cells = <1>;
+ };
+
+ ocram: sram@0 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0x80000>;
+ ranges = <0 0 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
new file mode 100644
index 000000000000..336e12a88cb4
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026, Altera Corporation
+ */
+#include "socfpga_agilex72.dtsi"
+
+/ {
+ model = "Altera SoCFPGA Agilex72 SoCDK";
+ compatible = "intel,socfpga-agilex72-socdk", "intel,socfpga-agilex72";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+};
--
2.43.7
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 5:56 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
In-Reply-To: <20260624055644.7508-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Add the SoC and board compatible strings for the Intel SoCFPGA
Agilex72 platform.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v2:
- Rename platform from agilex7-gen2 to agilex72
---
Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 4b096e52243e..cc03fb437a9a 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -115,6 +115,12 @@ properties:
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
+ - description: Agilex72 boards
+ items:
+ - enum:
+ - intel,socfpga-agilex72-socdk
+ - const: intel,socfpga-agilex72
+
- description: Agilex7m boards
items:
- enum:
--
2.43.7
^ permalink raw reply related
* [PATCH v2 0/2] arm64: dts: socfpga: agilex72: Add initial device tree support
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 5:56 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
This series introduces initial device tree support for the Intel
SoCFPGA Agilex72 platform.
The first patch registers the new SoC and board compatible strings in
the DT binding. The second patch adds the SoC DTSI and board DTS with
basic platform nodes.
Changes in v2:
- Rename platform from agilex7-gen2 to agilex72
- Add arm,armv8-timer node (was mistakenly removed in v1); other
review comments from Shashiko are either addressed or confirmed as false positives
consistent with existing SoCFPGA platform conventions
Nazim Amirul (2):
dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings
arm64: dts: socfpga: agilex72: Add initial device tree
.../devicetree/bindings/arm/altera.yaml | 6 +
arch/arm64/boot/dts/intel/Makefile | 1 +
.../boot/dts/intel/socfpga_agilex72.dtsi | 128 ++++++++++++++++++
.../boot/dts/intel/socfpga_agilex72_socdk.dts | 15 ++
4 files changed, 150 insertions(+)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts
--
2.43.7
^ permalink raw reply
* [PATCH v2] dt-bindings: watchdog: microchip,pic32mzda-wdt: Convert to DT schema
From: Udaya Kiran Challa @ 2026-06-24 5:56 UTC (permalink / raw)
To: tsbogend, robh, krzk+dt, conor+dt
Cc: skhan, me, linux-rtc, devicetree, linux-kernel,
Udaya Kiran Challa, Krzysztof Kozlowski
Convert Microchip PIC32 Watchdog Timer devicetree binding
from legacy text format to DT schema.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Udaya Kiran Challa <challauday369@gmail.com>
---
Changelog:
Changes since v1:
- Fix example indentation
- Correct example clock specifier from REF2CLK to LPRCCLK
Link to v1:https://lore.kernel.org/all/20260620172354.155565-1-challauday369@gmail.com/
---
.../bindings/watchdog/microchip,pic32-wdt.txt | 18 --------
.../watchdog/microchip,pic32mzda-wdt.yaml | 44 +++++++++++++++++++
2 files changed, 44 insertions(+), 18 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
create mode 100644 Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
deleted file mode 100644
index f03a29a1b323..000000000000
--- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* Microchip PIC32 Watchdog Timer
-
-When enabled, the watchdog peripheral can be used to reset the device if the
-WDT is not cleared periodically in software.
-
-Required properties:
-- compatible: must be "microchip,pic32mzda-wdt".
-- reg: physical base address of the controller and length of memory mapped
- region.
-- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>.
-
-Example:
-
- watchdog@1f800800 {
- compatible = "microchip,pic32mzda-wdt";
- reg = <0x1f800800 0x200>;
- clocks = <&rootclk LPRCCLK>;
- };
diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml
new file mode 100644
index 000000000000..a5dd633c3e78
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/microchip,pic32mzda-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PIC32MZDA Watchdog Timer
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+description:
+ The PIC32 watchdog timer can be used to reset the device if software fails
+ to periodically service the watchdog.
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: microchip,pic32mzda-wdt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,pic32-clock.h>
+
+ watchdog@1f800800 {
+ compatible = "microchip,pic32mzda-wdt";
+ reg = <0x1f800800 0x200>;
+ clocks = <&rootclk LPRCCLK>;
+ };
--
2.34.1
^ permalink raw reply related
* RE: [PATCH v9 2/2] i3c: master: Add driver for AMD AXI I3C master controller
From: Guntupalli, Manikanta @ 2026-06-24 6:06 UTC (permalink / raw)
To: Patil, Shubham Sanjay, git (AMD-Xilinx), Simek, Michal,
alexandre.belloni@bootlin.com, Frank.Li@nxp.com, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, pgaj@cadence.com,
wsa+renesas@sang-engineering.com,
tommaso.merciai.xr@bp.renesas.com, arnd@arndb.de,
quic_msavaliy@quicinc.com, S-k, Shyam-sundar,
sakari.ailus@linux.intel.com, billy_tsai@aspeedtech.com,
kees@kernel.org, gustavoars@kernel.org,
jarkko.nikula@linux.intel.com, jorge.marques@analog.com,
linux-i3c@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org,
linux-hardening@vger.kernel.org
Cc: Pandey, Radhey Shyam, Goud, Srinivas, Datta, Shubhrajyoti,
Patil, Shubham Sanjay
In-Reply-To: <20260623114417.2578189-3-shubhamsanjay.patil@amd.com>
AMD General
Hi,
> -----Original Message-----
> From: Shubham Patil <shubhamsanjay.patil@amd.com>
> Sent: Tuesday, June 23, 2026 5:14 PM
> To: git (AMD-Xilinx) <git@amd.com>; Simek, Michal <michal.simek@amd.com>;
> alexandre.belloni@bootlin.com; Frank.Li@nxp.com; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; pgaj@cadence.com;
> wsa+renesas@sang-engineering.com; tommaso.merciai.xr@bp.renesas.com;
> arnd@arndb.de; quic_msavaliy@quicinc.com; S-k, Shyam-sundar <Shyam-
> sundar.S-k@amd.com>; sakari.ailus@linux.intel.com; billy_tsai@aspeedtech.com;
> kees@kernel.org; gustavoars@kernel.org; jarkko.nikula@linux.intel.com;
> jorge.marques@analog.com; linux-i3c@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> arch@vger.kernel.org; linux-hardening@vger.kernel.org
> Cc: Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>; Goud, Srinivas
> <srinivas.goud@amd.com>; Datta, Shubhrajyoti <shubhrajyoti.datta@amd.com>;
> Patil, Shubham Sanjay <ShubhamSanjay.Patil@amd.com>; Guntupalli, Manikanta
> <manikanta.guntupalli@amd.com>
> Subject: [PATCH v9 2/2] i3c: master: Add driver for AMD AXI I3C master controller
>
> From: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
>
> Add an I3C master driver and maintainers fragment for the AMD I3C bus controller.
>
> The driver currently supports the I3C bus operating in SDR mode, with features
> including Dynamic Address Assignment, private data transfers, and CCC transfers in
> both broadcast and direct modes. It also supports operation in I2C mode.
>
> The controller's data FIFOs are accessed big-endian; the driver performs this
> conversion locally using ioread32be()/iowrite32be() with the helpers, so it does not
> depend on any core FIFO-endianness helpers.
>
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
> Co-developed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> Co-developed-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
> ---
> Changes for V9:
> Updated commit description to note that the driver performs big-endian FIFO
> accesses locally (the v8 core-helper patches were dropped).
> Dropped the big-endian MMIO infrastructure patches from the series
> ("asm-generic/io.h: Add big-endian MMIO accessors", "i3c: fix big-endian FIFO
> transfers", and "i3c: master: Add endianness support for
> i3c_readl_fifo()/i3c_writel_fifo()"). The driver now performs big-endian FIFO
> accesses locally using ioread32be()/iowrite32be() with
> get_unaligned()/put_unaligned(), so the series is self-contained and no longer
> includes internals.h.
> Replaced the async completion/transfer-queue machinery with a simple
> synchronous transfer path under the existing mutex.
> Reworked response handling: added enum i3c_error_code to struct xi3c_cmd,
> named the response codes, return -ENODEV/-EIO as appropriate and set err =
> I3C_ERROR_M2/M0 so the i3c core and callers can tell a NACK apart from a bus
> error; propagate err to CCC commands and to each priv xfer (including actual_len).
> Switched from .priv_xfers to the new .i3c_xfers op; reject non-SDR modes with -
> EOPNOTSUPP and report actual_len.
> Reworked DAA: assign addresses incrementally, bound the device count (-
> ENOSPC), detect end-of-enumeration via -ENODEV, zero-initialize the PID buffers,
> and check i3c_master_add_i3c_dev_locked().
> Avoid busy-spinning: sleep with usleep_range() in the FIFO drain/fill loops.
> Use FIELD_PREP() with named command-FIFO field masks instead of open-coded
> shifts, and convert the register-accessor macros to inline functions.
> Split the overloaded timeout macro into XI3C_RESP_TIMEOUT_US and
> XI3C_XFER_TIMEOUT_MS with documented units, and add
> XI3C_POLL_INTERVAL_US.
> xi3c_clk_cfg(): use NSEC_PER_SEC and named timing constants, guard against
> unsigned underflow, and handle I3C_BUS_MODE_MIXED_SLOW.
> Dropped ENTHDR from supports_ccc_cmd() (SDR-only), and dispatch CCCs using
> the I3C_CCC_DIRECT bit.
> Use const for TX buffers and drop the related casts; use parity8() for the DAA parity
> bit.
> Updated MODULE_DESCRIPTION and authors, the copyright year, renamed the
> Kconfig symbol to AMD_AXI_I3C_MASTER, and fixed the MAINTAINERS entry
> (title, mailing list, and the correct binding filename).
>
> Changes for V8:
> Used time_left instead of timeout.
> Used __free(kfree) for xfer to simplify err path in multiple places.
>
> Changes for V7:
> Updated timeout macro name.
> Updated xi3c_master_wr_to_tx_fifo() and xi3c_master_rd_from_rx_fifo() to use
> i3c_writel_fifo() and i3c_readl_fifo().
>
> Changes for V6:
> Removed typecast for xi3c_getrevisionnumber(), xi3c_wrfifolevel(), and
> xi3c_rdfifolevel().
> Replaced dynamic allocation with a static variable for pid_bcr_dcr.
> Fixed sparse warning in do_daa by typecasting the address parity value to u8.
> Fixed sparse warning in xi3c_master_bus_init by typecasting the pid value to u64 in
> info.pid calculation.
>
> Changes for V5:
> Used GENMASK_ULL for PID mask as it's 64bit mask.
>
> Changes for V4:
> Updated timeout macros.
> Removed type casting for xi3c_is_resp_available() macro.
> Used ioread32() and iowrite32() instead of readl() and writel() to keep consistency.
> Read XI3C_RESET_OFFSET reg before udelay().
> Removed xi3c_master_free_xfer() and directly used kfree().
> Skipped checking return value of i3c_master_add_i3c_dev_locked().
> Used devm_mutex_init() instead of mutex_init().
>
> Changes for V3:
> Resolved merge conflicts.
>
> Changes for V2:
> Updated commit description.
> Added mixed mode support with clock configuration.
> Converted smaller functions into inline functions.
> Used FIELD_GET() in xi3c_get_response().
> Updated xi3c_master_rd_from_rx_fifo() to use cmd->rx_buf.
> Used parity8() for address parity calculation.
> Added guards for locks.
> Dropped num_targets and updated xi3c_master_do_daa().
> Used __free(kfree) in xi3c_master_send_bdcast_ccc_cmd().
> Dropped PM runtime support.
> Updated xi3c_master_read() and xi3c_master_write() with
> xi3c_is_resp_available() check.
> Created separate functions: xi3c_master_init() and xi3c_master_reinit().
> Used xi3c_master_init() in bus initialization and xi3c_master_reinit() in error paths.
> Added DAA structure to xi3c_master structure.
> ---
> MAINTAINERS | 8 +
> drivers/i3c/master/Kconfig | 15 +
> drivers/i3c/master/Makefile | 1 +
> drivers/i3c/master/amd-i3c-master.c | 1060 +++++++++++++++++++++++++++
> 4 files changed, 1084 insertions(+)
> create mode 100644 drivers/i3c/master/amd-i3c-master.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 461a3eed6129..bfaa6999913c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1035,6 +1035,14 @@ L: linux-sound@vger.kernel.org
> S: Supported
> F: sound/soc/amd/
>
> +AMD AXI I3C MASTER DRIVER
> +M: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
> +M: Shubham Patil <shubhamsanjay.patil@amd.com>
> +L: linux-i3c@lists.infradead.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml
> +F: drivers/i3c/master/amd-i3c-master.c
> +
> AMD AXI W1 DRIVER
> M: Kris Chaplin <kris.chaplin@amd.com>
> R: Thomas Delev <thomas.delev@amd.com>
> diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig index
> 2609f2b18e0a..da96d2aaa399 100644
> --- a/drivers/i3c/master/Kconfig
> +++ b/drivers/i3c/master/Kconfig
> @@ -86,3 +86,18 @@ config RENESAS_I3C
>
> This driver can also be built as a module. If so, the module will be
> called renesas-i3c.
> +
> +config AMD_AXI_I3C_MASTER
> + tristate "AMD AXI I3C Master driver"
> + depends on HAS_IOMEM
> + help
> + Support for the AMD AXI I3C master controller, a soft IP used on
> + AMD (Xilinx) FPGAs and adaptive SoCs with ARM or MicroBlaze
> + processors.
> +
> + The controller currently supports Standard Data Rate (SDR) mode.
> + Features include Dynamic Address Assignment, private transfers,
> + and CCC transfers in both broadcast and direct modes.
> +
> + This driver can also be built as a module. If so, the module
> + will be called amd-i3c-master.
> diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile index
> 816a227b6f7a..8d82196dcf83 100644
> --- a/drivers/i3c/master/Makefile
> +++ b/drivers/i3c/master/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_AST2600_I3C_MASTER) += ast2600-i3c-
> master.o
> obj-$(CONFIG_SVC_I3C_MASTER) += svc-i3c-master.o
> obj-$(CONFIG_MIPI_I3C_HCI) += mipi-i3c-hci/
> obj-$(CONFIG_RENESAS_I3C) += renesas-i3c.o
> +obj-$(CONFIG_AMD_AXI_I3C_MASTER) += amd-i3c-master.o
> diff --git a/drivers/i3c/master/amd-i3c-master.c b/drivers/i3c/master/amd-i3c-master.c
> new file mode 100644
> index 000000000000..34ab1028c3ce
> --- /dev/null
> +++ b/drivers/i3c/master/amd-i3c-master.c
> @@ -0,0 +1,1060 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * I3C master driver for the AMD I3C controller.
> + *
> + * Copyright (C) 2026, Advanced Micro Devices, Inc.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
> +#include <linux/cleanup.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/i3c/master.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/time.h>
> +#include <linux/unaligned.h>
> +
> +#define XI3C_VERSION_OFFSET 0x00 /* Version Register */
> +#define XI3C_RESET_OFFSET 0x04 /* Soft Reset Register */
> +#define XI3C_CR_OFFSET 0x08 /* Control Register */
> +#define XI3C_ADDRESS_OFFSET 0x0C /* Target Address
> Register */
> +#define XI3C_SR_OFFSET 0x10 /* Status Register */
> +#define XI3C_CMD_FIFO_OFFSET 0x20 /* I3C Command
> FIFO Register */
> +#define XI3C_WR_FIFO_OFFSET 0x24 /* I3C Write Data FIFO
> Register */
> +#define XI3C_RD_FIFO_OFFSET 0x28 /* I3C Read Data FIFO
> Register */
> +#define XI3C_RESP_STATUS_FIFO_OFFSET 0x2C /* I3C Response
> status FIFO Register */
> +#define XI3C_FIFO_LVL_STATUS_OFFSET 0x30 /* CMD slots free
> | WR-FIFO free (words) */
> +#define XI3C_FIFO_LVL_STATUS_1_OFFSET 0x34 /* RESP fill | RD-
> FIFO fill level (words) */
> +#define XI3C_SCL_HIGH_TIME_OFFSET 0x38 /* I3C SCL HIGH
> Register */
> +#define XI3C_SCL_LOW_TIME_OFFSET 0x3C /* I3C SCL LOW
> Register */
> +#define XI3C_SDA_HOLD_TIME_OFFSET 0x40 /* I3C SDA
> HOLD Register */
> +#define XI3C_TSU_START_OFFSET 0x48 /* I3C START
> SETUP Register */
> +#define XI3C_THD_START_OFFSET 0x4C /* I3C START
> HOLD Register */
> +#define XI3C_TSU_STOP_OFFSET 0x50 /* I3C STOP
> Setup Register */
> +#define XI3C_OD_SCL_HIGH_TIME_OFFSET 0x54 /* I3C OD SCL
> HIGH Register */
> +#define XI3C_OD_SCL_LOW_TIME_OFFSET 0x58 /* I3C OD SCL
> LOW Register */
> +#define XI3C_PID0_OFFSET 0x6C /* LSB 4 bytes of the
> PID */
> +#define XI3C_PID1_BCR_DCR 0x70 /* MSB 2 bytes of the
> PID, BCR and DCR */
> +
> +#define XI3C_CR_EN_MASK BIT(0) /* Core Enable */
> +#define XI3C_CR_RESUME_MASK BIT(2) /* Core Resume
> */
> +#define XI3C_SR_RESP_NOT_EMPTY_MASK BIT(4) /* Resp Fifo not
> empty status mask */
> +#define XI3C_RD_FIFO_NOT_EMPTY_MASK BIT(15) /* Read
> Fifo not empty status mask */
> +
> +#define XI3C_BCR_MASK GENMASK(23, 16)
> +#define XI3C_DCR_MASK GENMASK(31, 24)
> +#define XI3C_PID_MASK GENMASK_ULL(63, 16)
> +#define XI3C_TIMING_MASK GENMASK(17, 0)
> +#define XI3C_REV_NUM_MASK GENMASK(15, 8)
> +#define XI3C_PID1_MASK GENMASK(15, 0)
> +#define XI3C_FIFO_LEVEL_MASK GENMASK(15, 0)
> +#define XI3C_RESP_CODE_MASK GENMASK(8, 5)
> +#define XI3C_RESP_CODE_SUCCESS 0 /* Transfer
> completed OK */
> +#define XI3C_RESP_CODE_NO_TARGET 2 /* 7E NACK: no
> target on bus */
> +#define XI3C_RESP_CODE_NACK 3 /* Target NACK /
> CE2 / DAA end */
> +#define XI3C_ADDR_MASK GENMASK(6, 0)
> +#define XI3C_FIFOS_RST_MASK GENMASK(4, 1)
> +
> +/* Command FIFO word layout (bit ranges encoded in the GENMASK/BIT args) */
> +#define XI3C_CMD_TYPE GENMASK(3, 0) /*
> command type */
> +#define XI3C_CMD_TERMINATE BIT(4) /* terminate (last
> cmd of xfer) */
> +#define XI3C_CMD_ADDR GENMASK(15, 8) /* target
> address << 1 | RnW */
> +#define XI3C_CMD_LEN GENMASK(27, 16) /*
> payload length in bytes */
> +#define XI3C_CMD_TID GENMASK(31, 28) /* transfer
> ID */
> +
> +#define XI3C_OD_TLOW_NS 500000
> +#define XI3C_OD_THIGH_NS 41000
> +#define XI3C_I2C_TCASMIN_NS 600000
> +#define XI3C_TCASMIN_NS 260000
> +#define XI3C_MAXDATA_LENGTH 4095
> +#define XI3C_MAX_DEVS 32
> +#define XI3C_DAA_SLAVEINFO_READ_BYTECOUNT 8
> +
> +#define XI3C_THOLD_MIN_REV0 5 /* Min SDA hold cycles,
> rev 0 IP */
> +#define XI3C_THOLD_MIN_REV1 6 /* Min SDA hold cycles,
> rev >= 1 IP */
> +#define XI3C_CYCLE_ADJUST 2 /* SCL/SDA pre-bias for
> HW pipeline */
> +#define XI3C_FIFO_RESET_DELAY_US 10 /* HW settling time after
> FIFO reset */
> +#define XI3C_POLL_INTERVAL_US 10 /*
> readl_poll_timeout() sleep slice */
> +
> +#define XI3C_I2C_MODE 0
> +#define XI3C_I2C_TID 0
> +#define XI3C_SDR_MODE 1
> +#define XI3C_SDR_TID 1
> +
> +#define XI3C_WORD_LEN 4
> +
> +/*
> + * XI3C_RESP_TIMEOUT_US is in microseconds because it is passed as the
> + * timeout_us argument of readl_poll_timeout(). XI3C_XFER_TIMEOUT_MS is
> +in
> + * milliseconds because it feeds msecs_to_jiffies(). Keep the two units
> + * distinct in the names so callers cannot mix them up.
> + */
> +#define XI3C_RESP_TIMEOUT_US 500000
> +#define XI3C_XFER_TIMEOUT_MS 1000
> +
> +struct xi3c_cmd {
> + const void *tx_buf;
> + void *rx_buf;
> + u16 tx_len;
> + u16 rx_len;
> + u8 addr;
> + u8 type;
> + u8 tid;
> + bool rnw;
> + bool is_daa;
> + bool continued;
> + enum i3c_error_code err;
> +};
> +
> +struct xi3c_xfer {
> + unsigned int ncmds;
> + struct xi3c_cmd cmds[] __counted_by(ncmds); };
> +
> +/**
> + * struct xi3c_master - I3C master controller state.
> + * @base: I3C master controller embedded by the framework.
> + * @dev: Pointer to the backing device structure.
> + * @membase: Memory base of the HW registers.
> + * @pclk: Input clock driving the controller.
> + * @lock: Serializes transfers and CCC submission.
> + * @daa: ENTDAA enumeration state.
> + * @daa.addrs: Dynamic addresses assigned in enumeration order.
> + * @daa.index: Number of responders enumerated so far.
> + */
> +struct xi3c_master {
> + struct i3c_master_controller base;
> + struct device *dev;
> + void __iomem *membase;
> + struct clk *pclk;
> + struct mutex lock; /* serializes transfers and CCC submission */
> + struct {
> + u8 addrs[XI3C_MAX_DEVS];
> + u8 index;
> + } daa;
> +};
> +
> +static inline struct xi3c_master *
> +to_xi3c_master(struct i3c_master_controller *master) {
> + return container_of(master, struct xi3c_master, base); }
> +
> +static inline u8 xi3c_get_revision_number(struct xi3c_master *master) {
> + return FIELD_GET(XI3C_REV_NUM_MASK,
> + ioread32(master->membase + XI3C_VERSION_OFFSET)); }
> +
> +static inline u16 xi3c_wr_fifo_level(struct xi3c_master *master) {
> + return ioread32(master->membase + XI3C_FIFO_LVL_STATUS_OFFSET) &
> + XI3C_FIFO_LEVEL_MASK;
> +}
> +
> +static inline u16 xi3c_rd_fifo_level(struct xi3c_master *master) {
> + return ioread32(master->membase +
> XI3C_FIFO_LVL_STATUS_1_OFFSET) &
> + XI3C_FIFO_LEVEL_MASK;
> +}
> +
> +static inline bool xi3c_is_resp_available(struct xi3c_master *master) {
> + return FIELD_GET(XI3C_SR_RESP_NOT_EMPTY_MASK,
> + ioread32(master->membase + XI3C_SR_OFFSET)); }
> +
> +static int xi3c_get_response(struct xi3c_master *master, struct
> +xi3c_cmd *cmd) {
> + u32 response_data;
> + u32 resp_reg;
> + u8 code;
> + int ret;
> +
> + ret = readl_poll_timeout(master->membase + XI3C_SR_OFFSET,
> + resp_reg,
> + resp_reg & XI3C_SR_RESP_NOT_EMPTY_MASK,
> + XI3C_POLL_INTERVAL_US,
> XI3C_RESP_TIMEOUT_US);
> + if (ret) {
> + dev_err(master->dev, "XI3C response timeout\n");
> + return ret;
> + }
> +
> + response_data = ioread32(master->membase +
> XI3C_RESP_STATUS_FIFO_OFFSET);
> + code = FIELD_GET(XI3C_RESP_CODE_MASK, response_data);
> +
> + switch (code) {
> + case XI3C_RESP_CODE_SUCCESS:
> + cmd->err = I3C_ERROR_UNKNOWN;
> + return 0;
> + case XI3C_RESP_CODE_NO_TARGET:
> + case XI3C_RESP_CODE_NACK:
> + /*
> + * Target did not ACK. Record it as I3C_ERROR_M2 so callers
> + * (and the i3c core, which keys on err == I3C_ERROR_M2) can
> + * tell a NACK apart from other failures. A normal transfer
> + * surfaces this as -EIO per the i3c_xfer contract; the DAA
> + * path instead expects -ENODEV as its enumeration terminator.
> + */
> + cmd->err = I3C_ERROR_M2;
> + return cmd->is_daa ? -ENODEV : -EIO;
> + default:
> + cmd->err = I3C_ERROR_M0;
> + dev_err(master->dev, "XI3C transfer error, response code %u\n",
> + code);
> + return -EIO;
> + }
> +}
> +
> +static inline void xi3c_writesl_be(void __iomem *addr, const void *buffer,
> + unsigned int count)
> +{
> + const u32 *buf = buffer;
> +
> + while (count--)
> + iowrite32be(get_unaligned(buf++), addr); }
> +
> +static inline void xi3c_readsl_be(const void __iomem *addr, void *buffer,
> + unsigned int count)
> +{
> + u32 *buf = buffer;
> +
> + while (count--)
> + put_unaligned(ioread32be(addr), buf++); }
> +
> +static inline void xi3c_writel_fifo(void __iomem *addr, const void *buf,
> + int nbytes)
> +{
> + xi3c_writesl_be(addr, buf, nbytes / 4);
> + if (nbytes & 3) {
> + u32 tmp = 0;
> +
> + memcpy(&tmp, (const u8 *)buf + (nbytes & ~3), nbytes & 3);
> + xi3c_writesl_be(addr, &tmp, 1);
> + }
> +}
> +
> +static inline void xi3c_readl_fifo(const void __iomem *addr, void *buf,
> + int nbytes)
> +{
> + xi3c_readsl_be(addr, buf, nbytes / 4);
> + if (nbytes & 3) {
> + u32 tmp;
> +
> + xi3c_readsl_be(addr, &tmp, 1);
> + memcpy((u8 *)buf + (nbytes & ~3), &tmp, nbytes & 3);
> + }
> +}
> +
> +static void xi3c_master_write_to_cmdfifo(struct xi3c_master *master,
> + struct xi3c_cmd *cmd, u16 len)
> +{
> + u32 transfer_cmd;
> + u8 addr;
> +
> + addr = ((cmd->addr & XI3C_ADDR_MASK) << 1) | (u8)cmd->rnw;
> +
> + transfer_cmd = FIELD_PREP(XI3C_CMD_TYPE, cmd->type);
> + transfer_cmd |= FIELD_PREP(XI3C_CMD_TERMINATE, !cmd->continued);
> + transfer_cmd |= FIELD_PREP(XI3C_CMD_ADDR, addr);
> + transfer_cmd |= FIELD_PREP(XI3C_CMD_TID, cmd->tid);
> +
> + /*
> + * For dynamic addressing, an additional 1-byte length must be added
> + * to the command FIFO to account for the address present in the TX FIFO
> + */
> + if (cmd->is_daa) {
> + xi3c_writel_fifo(master->membase + XI3C_WR_FIFO_OFFSET,
> + cmd->tx_buf, cmd->tx_len);
> +
> + len++;
> + }
> +
> + transfer_cmd |= FIELD_PREP(XI3C_CMD_LEN, len);
> + iowrite32(transfer_cmd, master->membase + XI3C_CMD_FIFO_OFFSET); }
> +
> +static inline void xi3c_master_enable(struct xi3c_master *master) {
> + iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) |
> XI3C_CR_EN_MASK,
> + master->membase + XI3C_CR_OFFSET);
> +}
> +
> +static inline void xi3c_master_disable(struct xi3c_master *master) {
> + iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) &
> ~XI3C_CR_EN_MASK,
> + master->membase + XI3C_CR_OFFSET);
> +}
> +
> +static inline void xi3c_master_resume(struct xi3c_master *master) {
> + iowrite32(ioread32(master->membase + XI3C_CR_OFFSET) |
> + XI3C_CR_RESUME_MASK, master->membase +
> XI3C_CR_OFFSET); }
> +
> +static void xi3c_master_reset_fifos(struct xi3c_master *master) {
> + u32 data;
> +
> + /* Assert FIFO reset. */
> + data = ioread32(master->membase + XI3C_RESET_OFFSET);
> + data |= XI3C_FIFOS_RST_MASK;
> + iowrite32(data, master->membase + XI3C_RESET_OFFSET);
> + /* Read-back flushes the posted write before the settling delay below. */
> + ioread32(master->membase + XI3C_RESET_OFFSET);
> + udelay(XI3C_FIFO_RESET_DELAY_US);
> +
> + /* De-assert FIFO reset, then wait for the FIFOs to come back up. */
> + data &= ~XI3C_FIFOS_RST_MASK;
> + iowrite32(data, master->membase + XI3C_RESET_OFFSET);
> + ioread32(master->membase + XI3C_RESET_OFFSET);
> + udelay(XI3C_FIFO_RESET_DELAY_US);
> +}
> +
> +static inline void xi3c_master_init(struct xi3c_master *master) {
> + /* Reset fifos */
> + xi3c_master_reset_fifos(master);
> +
> + /* Enable controller */
> + xi3c_master_enable(master);
> +}
> +
> +static inline void xi3c_master_reinit(struct xi3c_master *master) {
> + /* Reset fifos */
> + xi3c_master_reset_fifos(master);
> +
> + /* Resume controller */
> + xi3c_master_resume(master);
> +}
> +
> +static struct xi3c_xfer *xi3c_master_alloc_xfer(unsigned int ncmds) {
> + struct xi3c_xfer *xfer;
> +
> + xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
> + if (!xfer)
> + return NULL;
> +
> + xfer->ncmds = ncmds;
> +
> + return xfer;
> +}
> +
> +static void xi3c_master_rd_from_rx_fifo(struct xi3c_master *master,
> + struct xi3c_cmd *cmd)
> +{
> + u16 rx_data_available;
> + u16 copy_len;
> + u16 len;
> +
> + rx_data_available = xi3c_rd_fifo_level(master);
> + len = rx_data_available * XI3C_WORD_LEN;
> +
> + if (!len)
> + return;
> +
> + copy_len = min_t(u16, len, cmd->rx_len);
> + xi3c_readl_fifo(master->membase + XI3C_RD_FIFO_OFFSET,
> + (u8 *)cmd->rx_buf, copy_len);
> +
> + cmd->rx_buf = (u8 *)cmd->rx_buf + copy_len;
> + cmd->rx_len -= copy_len;
> +}
> +
> +static int xi3c_master_read(struct xi3c_master *master, struct xi3c_cmd
> +*cmd) {
> + unsigned long timeout;
> + u32 status_reg;
> + int ret;
> +
> + if (!cmd->rx_buf || cmd->rx_len > XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + /* Fill command fifo */
> + xi3c_master_write_to_cmdfifo(master, cmd, cmd->rx_len);
> +
> + if (!cmd->rx_len)
> + return 0;
> +
> + ret = readl_poll_timeout(master->membase + XI3C_SR_OFFSET,
> + status_reg,
> + status_reg & (XI3C_RD_FIFO_NOT_EMPTY_MASK
> |
> + XI3C_SR_RESP_NOT_EMPTY_MASK),
> + XI3C_POLL_INTERVAL_US,
> XI3C_RESP_TIMEOUT_US);
> + if (ret) {
> + dev_err(master->dev, "XI3C read timeout\n");
> + return ret;
> + }
> +
> + if (!(status_reg & XI3C_RD_FIFO_NOT_EMPTY_MASK))
> + return 0;
> +
> + timeout = jiffies + msecs_to_jiffies(XI3C_XFER_TIMEOUT_MS);
> +
> + /* Read data from rx fifo */
> + while (cmd->rx_len > 0 && !xi3c_is_resp_available(master)) {
> + if (time_after(jiffies, timeout)) {
> + dev_err(master->dev, "XI3C read timeout\n");
> + return -EIO;
> + }
> + xi3c_master_rd_from_rx_fifo(master, cmd);
> + usleep_range(XI3C_POLL_INTERVAL_US, 2 *
> XI3C_POLL_INTERVAL_US);
> + }
> +
> + /* Read remaining data */
> + xi3c_master_rd_from_rx_fifo(master, cmd);
> +
> + return 0;
> +}
> +
> +static void xi3c_master_wr_to_tx_fifo(struct xi3c_master *master,
> + struct xi3c_cmd *cmd)
> +{
> + u16 wrfifo_space;
> + u16 len;
> +
> + wrfifo_space = xi3c_wr_fifo_level(master);
> + if (cmd->tx_len > wrfifo_space * XI3C_WORD_LEN)
> + len = wrfifo_space * XI3C_WORD_LEN;
> + else
> + len = cmd->tx_len;
> +
> + if (len) {
> + xi3c_writel_fifo(master->membase + XI3C_WR_FIFO_OFFSET,
> cmd->tx_buf,
> + len);
> +
> + cmd->tx_buf = (const u8 *)cmd->tx_buf + len;
> + cmd->tx_len -= len;
> + }
> +}
> +
> +static int xi3c_master_write(struct xi3c_master *master, struct
> +xi3c_cmd *cmd) {
> + unsigned long timeout;
> + u16 cmd_len;
> +
> + if (!cmd->tx_buf || cmd->tx_len > XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + cmd_len = cmd->tx_len;
> +
> + /* Fill Tx fifo */
> + xi3c_master_wr_to_tx_fifo(master, cmd);
> +
> + /* Write to command fifo */
> + xi3c_master_write_to_cmdfifo(master, cmd, cmd_len);
> +
> + timeout = jiffies + msecs_to_jiffies(XI3C_XFER_TIMEOUT_MS);
> + /* Fill if any remaining data to tx fifo */
> + while (cmd->tx_len > 0 && !xi3c_is_resp_available(master)) {
> + if (time_after(jiffies, timeout)) {
> + dev_err(master->dev, "XI3C write timeout\n");
> + return -EIO;
> + }
> +
> + xi3c_master_wr_to_tx_fifo(master, cmd);
> + usleep_range(XI3C_POLL_INTERVAL_US, 2 *
> XI3C_POLL_INTERVAL_US);
> + }
> +
> + return 0;
> +}
> +
> +static int xi3c_master_xfer(struct xi3c_master *master, struct xi3c_cmd
> +*cmd) {
> + int ret;
> +
> + if (cmd->rnw)
> + ret = xi3c_master_read(master, cmd);
> + else
> + ret = xi3c_master_write(master, cmd);
> +
> + if (ret)
> + goto err_xfer_out;
> +
> + ret = xi3c_get_response(master, cmd);
> + if (ret)
> + goto err_xfer_out;
> +
> + return 0;
> +
> +err_xfer_out:
> + xi3c_master_reinit(master);
> + return ret;
> +}
> +
> +static int xi3c_master_common_xfer(struct xi3c_master *master,
> + struct xi3c_xfer *xfer)
> +{
> + unsigned int i;
> + int ret;
> +
> + guard(mutex)(&master->lock);
> +
> + for (i = 0; i < xfer->ncmds; i++) {
> + ret = xi3c_master_xfer(master, &xfer->cmds[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int xi3c_master_do_daa(struct i3c_master_controller *m) {
> + u8
> pid_bufs[XI3C_MAX_DEVS][XI3C_DAA_SLAVEINFO_READ_BYTECOUNT] = {};
> + struct xi3c_master *master = to_xi3c_master(m);
> + struct xi3c_xfer *xfer __free(kfree) = NULL;
> + struct xi3c_cmd *daa_cmd;
> + int addr, ret, i;
> + u8 last_addr = 0;
> + u8 *pid_buf;
> + u8 ccc_id;
> +
> + xfer = xi3c_master_alloc_xfer(1);
> + if (!xfer)
> + return -ENOMEM;
> +
> + /* Fill ENTDAA CCC */
> + ccc_id = I3C_CCC_ENTDAA;
> + daa_cmd = &xfer->cmds[0];
> + daa_cmd->addr = I3C_BROADCAST_ADDR;
> + daa_cmd->rnw = false;
> + daa_cmd->tx_buf = &ccc_id;
> + daa_cmd->tx_len = 1;
> + daa_cmd->type = XI3C_SDR_MODE;
> + daa_cmd->tid = XI3C_SDR_TID;
> + daa_cmd->continued = true;
> +
> + ret = xi3c_master_common_xfer(master, xfer);
> + /*
> + * A NACK on the ENTDAA broadcast (I3C_ERROR_M2) means no slaves
> are
> + * present to enter DAA. Treat as a successful no-op after letting
> + * err_daa reinitialize the controller.
> + */
> + if (ret && daa_cmd->err == I3C_ERROR_M2) {
> + ret = 0;
> + goto err_daa;
> + }
> + if (ret)
> + goto err_daa;
> +
> + master->daa.index = 0;
> +
> + while (true) {
> + struct xi3c_cmd *cmd = &xfer->cmds[0];
> + u8 daa_byte;
> +
> + if (master->daa.index >= XI3C_MAX_DEVS) {
> + ret = -ENOSPC;
> + goto err_daa;
> + }
> +
> + addr = i3c_master_get_free_addr(m, last_addr + 1);
> + if (addr < 0) {
> + ret = addr;
> + goto err_daa;
> + }
> +
> + pid_buf = pid_bufs[master->daa.index];
> +
> + daa_byte = (addr << 1) | (parity8(addr) ^ 1);
> +
> + cmd->tx_buf = &daa_byte;
> + cmd->tx_len = 1;
> + cmd->addr = I3C_BROADCAST_ADDR;
> + cmd->rnw = true;
> + cmd->rx_buf = pid_buf;
> + cmd->rx_len = XI3C_DAA_SLAVEINFO_READ_BYTECOUNT;
> + cmd->is_daa = true;
> + cmd->type = XI3C_SDR_MODE;
> + cmd->tid = XI3C_SDR_TID;
> + cmd->continued = true;
> +
> + ret = xi3c_master_common_xfer(master, xfer);
> +
> + /*
> + * End of enumeration: the next responder NACK'd the
> + * dynamic-address grant, surfaced as -ENODEV.
> + * xi3c_master_xfer() has already reset the FIFOs and
> + * resumed the core for us; just exit the loop and
> + * register the responders collected so far.
> + */
> + if (ret == -ENODEV) {
> + ret = 0;
> + break;
> + }
> + if (ret)
> + goto err_daa;
> +
> + master->daa.addrs[master->daa.index] = addr;
> + last_addr = addr;
> + master->daa.index++;
> + }
> +
> + for (i = 0; i < master->daa.index; i++) {
> + u64 pid;
> +
> + ret = i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]);
> + if (ret)
> + goto err_daa;
> +
> + pid = FIELD_GET(XI3C_PID_MASK,
> + get_unaligned_be64(pid_bufs[i]));
> + dev_dbg(master->dev, "Client %d: PID: 0x%llx\n", i, pid);
> + }
> +
> + return 0;
> +
> +err_daa:
> + xi3c_master_reinit(master);
> + return ret;
> +}
> +
> +static bool
> +xi3c_master_supports_ccc_cmd(struct i3c_master_controller *master,
> + const struct i3c_ccc_cmd *cmd)
> +{
> + if (cmd->ndests > 1)
> + return false;
> +
> + switch (cmd->id) {
> + case I3C_CCC_ENEC(true):
> + case I3C_CCC_ENEC(false):
> + case I3C_CCC_DISEC(true):
> + case I3C_CCC_DISEC(false):
> + case I3C_CCC_ENTAS(0, true):
> + case I3C_CCC_ENTAS(0, false):
> + case I3C_CCC_RSTDAA(true):
> + case I3C_CCC_RSTDAA(false):
> + case I3C_CCC_ENTDAA:
> + case I3C_CCC_SETMWL(true):
> + case I3C_CCC_SETMWL(false):
> + case I3C_CCC_SETMRL(true):
> + case I3C_CCC_SETMRL(false):
> + case I3C_CCC_SETDASA:
> + case I3C_CCC_SETNEWDA:
> + case I3C_CCC_GETMWL:
> + case I3C_CCC_GETMRL:
> + case I3C_CCC_GETPID:
> + case I3C_CCC_GETBCR:
> + case I3C_CCC_GETDCR:
> + case I3C_CCC_GETSTATUS:
> + case I3C_CCC_GETMXDS:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static int xi3c_master_send_bdcast_ccc_cmd(struct xi3c_master *master,
> + struct i3c_ccc_cmd *ccc)
> +{
> + struct xi3c_xfer *xfer __free(kfree) = NULL;
> + u8 *buf __free(kfree) = NULL;
> + struct xi3c_cmd *cmd;
> + u16 xfer_len;
> + int ret;
> +
> + if (ccc->dests[0].payload.len >= XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + xfer_len = ccc->dests[0].payload.len + 1;
> +
> + xfer = xi3c_master_alloc_xfer(1);
> + if (!xfer)
> + return -ENOMEM;
> +
> + buf = kmalloc(xfer_len, GFP_KERNEL);
> + if (!buf)
> + return -ENOMEM;
> +
> + buf[0] = ccc->id;
> + memcpy(&buf[1], ccc->dests[0].payload.data,
> +ccc->dests[0].payload.len);
> +
> + cmd = &xfer->cmds[0];
> + cmd->addr = ccc->dests[0].addr;
> + cmd->rnw = ccc->rnw;
> + cmd->tx_buf = buf;
> + cmd->tx_len = xfer_len;
> + cmd->type = XI3C_SDR_MODE;
> + cmd->tid = XI3C_SDR_TID;
> + cmd->continued = false;
> +
> + ret = xi3c_master_common_xfer(master, xfer);
> + ccc->err = cmd->err;
> +
> + return ret;
> +}
> +
> +static int xi3c_master_send_direct_ccc_cmd(struct xi3c_master *master,
> + struct i3c_ccc_cmd *ccc)
> +{
> + struct xi3c_xfer *xfer __free(kfree) = NULL;
> + struct xi3c_cmd *cmd;
> + int ret;
> +
> + if (ccc->dests[0].payload.len > XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + xfer = xi3c_master_alloc_xfer(2);
> + if (!xfer)
> + return -ENOMEM;
> +
> + /* Broadcasted message */
> + cmd = &xfer->cmds[0];
> + cmd->addr = I3C_BROADCAST_ADDR;
> + cmd->rnw = false;
> + cmd->tx_buf = &ccc->id;
> + cmd->tx_len = 1;
> + cmd->type = XI3C_SDR_MODE;
> + cmd->tid = XI3C_SDR_TID;
> + cmd->continued = true;
> +
> + /* Directed message */
> + cmd = &xfer->cmds[1];
> + cmd->addr = ccc->dests[0].addr;
> + cmd->rnw = ccc->rnw;
> + if (cmd->rnw) {
> + cmd->rx_buf = ccc->dests[0].payload.data;
> + cmd->rx_len = ccc->dests[0].payload.len;
> + } else {
> + cmd->tx_buf = ccc->dests[0].payload.data;
> + cmd->tx_len = ccc->dests[0].payload.len;
> + }
> + cmd->type = XI3C_SDR_MODE;
> + cmd->tid = XI3C_SDR_TID;
> + cmd->continued = false;
> +
> + ret = xi3c_master_common_xfer(master, xfer);
> +
> + /*
> + * Report the broadcast command's error if it failed, otherwise the
> + * directed command's, so a NACK on either phase reaches the caller.
> + */
> + ccc->err = xfer->cmds[0].err ? xfer->cmds[0].err : xfer->cmds[1].err;
> +
> + return ret;
> +}
> +
> +static int xi3c_master_send_ccc_cmd(struct i3c_master_controller *m,
> + struct i3c_ccc_cmd *cmd)
> +{
> + struct xi3c_master *master = to_xi3c_master(m);
> +
> + if (cmd->id & I3C_CCC_DIRECT)
> + return xi3c_master_send_direct_ccc_cmd(master, cmd);
> +
> + return xi3c_master_send_bdcast_ccc_cmd(master, cmd); }
> +
> +static int xi3c_master_i3c_xfers(struct i3c_dev_desc *dev,
> + struct i3c_xfer *xfers,
> + int nxfers, enum i3c_xfer_mode mode) {
> + struct i3c_master_controller *m = i3c_dev_get_master(dev);
> + struct xi3c_master *master = to_xi3c_master(m);
> + struct xi3c_xfer *xfer __free(kfree) = NULL;
> + int i, ret;
> +
> + if (!nxfers)
> + return 0;
> +
> + if (mode != I3C_SDR)
> + return -EOPNOTSUPP;
> +
> + for (i = 0; i < nxfers; i++)
> + if (xfers[i].len > XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + xfer = xi3c_master_alloc_xfer(nxfers);
> + if (!xfer)
> + return -ENOMEM;
> +
> + for (i = 0; i < nxfers; i++) {
> + struct xi3c_cmd *cmd = &xfer->cmds[i];
> +
> + cmd->addr = dev->info.dyn_addr;
> + cmd->rnw = xfers[i].rnw;
> +
> + if (cmd->rnw) {
> + cmd->rx_buf = xfers[i].data.in;
> + cmd->rx_len = xfers[i].len;
> + } else {
> + cmd->tx_buf = xfers[i].data.out;
> + cmd->tx_len = xfers[i].len;
> + }
> +
> + cmd->type = XI3C_SDR_MODE;
> + cmd->tid = XI3C_SDR_TID;
> + cmd->continued = (i + 1) < nxfers;
> + }
> +
> + ret = xi3c_master_common_xfer(master, xfer);
> +
> + for (i = 0; i < nxfers; i++) {
> + xfers[i].err = xfer->cmds[i].err;
> + if (xfers[i].rnw)
> + xfers[i].actual_len = xfers[i].len - xfer->cmds[i].rx_len;
> + }
> +
> + return ret;
> +}
> +
> +static int xi3c_master_i2c_xfers(struct i2c_dev_desc *dev,
> + struct i2c_msg *xfers,
> + int nxfers)
> +{
> + struct i3c_master_controller *m = i2c_dev_get_master(dev);
> + struct xi3c_master *master = to_xi3c_master(m);
> + struct xi3c_xfer *xfer __free(kfree) = NULL;
> + int i;
> +
> + if (!nxfers)
> + return 0;
> +
> + for (i = 0; i < nxfers; i++)
> + if (xfers[i].len > XI3C_MAXDATA_LENGTH)
> + return -EINVAL;
> +
> + xfer = xi3c_master_alloc_xfer(nxfers);
> + if (!xfer)
> + return -ENOMEM;
> +
> + for (i = 0; i < nxfers; i++) {
> + struct xi3c_cmd *cmd = &xfer->cmds[i];
> +
> + cmd->addr = xfers[i].addr & XI3C_ADDR_MASK;
> + cmd->rnw = !!(xfers[i].flags & I2C_M_RD);
> +
> + if (cmd->rnw) {
> + cmd->rx_buf = xfers[i].buf;
> + cmd->rx_len = xfers[i].len;
> + } else {
> + cmd->tx_buf = xfers[i].buf;
> + cmd->tx_len = xfers[i].len;
> + }
> +
> + cmd->type = XI3C_I2C_MODE;
> + cmd->tid = XI3C_I2C_TID;
> + cmd->continued = (i + 1) < nxfers;
> + }
> +
> + return xi3c_master_common_xfer(master, xfer); }
> +
> +static int xi3c_clk_cfg(struct xi3c_master *master, unsigned long
> +sclhz, u8 mode) {
> + unsigned long core_rate, core_periodns;
> + u32 tcasmin, tsustart, tsustop, thdstart;
> + u32 thigh, tlow, thold;
> + u32 odthigh, odtlow;
> +
> + core_rate = clk_get_rate(master->pclk);
> + if (!core_rate)
> + return -EINVAL;
> +
> + if (!sclhz)
> + return -EINVAL;
> +
> + core_periodns = DIV_ROUND_UP(NSEC_PER_SEC, core_rate);
> +
> + thigh = DIV_ROUND_UP(core_rate, sclhz) >> 1;
> + tlow = thigh;
> +
> + if (thigh <= XI3C_CYCLE_ADJUST)
> + return -EINVAL;
> +
> + /* Hold time : 40% of tlow time */
> + thold = (tlow * 4) / 10;
> +
> + if (xi3c_get_revision_number(master) == 0)
> + thold = max_t(u32, thold, XI3C_THOLD_MIN_REV0);
> + else
> + thold = max_t(u32, thold, XI3C_THOLD_MIN_REV1);
> +
> + iowrite32((thigh - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_SCL_HIGH_TIME_OFFSET);
> + iowrite32((tlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_SCL_LOW_TIME_OFFSET);
> + iowrite32((thold - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_SDA_HOLD_TIME_OFFSET);
> +
> + if (mode == XI3C_I2C_MODE) {
> + iowrite32((thigh - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase +
> XI3C_OD_SCL_HIGH_TIME_OFFSET);
> + iowrite32((tlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase +
> XI3C_OD_SCL_LOW_TIME_OFFSET);
> +
> + tcasmin = DIV_ROUND_UP(XI3C_I2C_TCASMIN_NS,
> core_periodns);
> + } else {
> + odtlow = DIV_ROUND_UP(XI3C_OD_TLOW_NS, core_periodns);
> + odthigh = DIV_ROUND_UP(XI3C_OD_THIGH_NS, core_periodns);
> +
> + odtlow = max(tlow, odtlow);
> + odthigh = min(thigh, odthigh);
> +
> + if (odthigh <= XI3C_CYCLE_ADJUST)
> + return -EINVAL;
> +
> + iowrite32((odthigh - XI3C_CYCLE_ADJUST) &
> XI3C_TIMING_MASK,
> + master->membase +
> XI3C_OD_SCL_HIGH_TIME_OFFSET);
> + iowrite32((odtlow - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase +
> XI3C_OD_SCL_LOW_TIME_OFFSET);
> +
> + tcasmin = DIV_ROUND_UP(XI3C_TCASMIN_NS, core_periodns);
> + }
> +
> + thdstart = max(thigh, tcasmin);
> + tsustart = max(tlow, tcasmin);
> + tsustop = max(tlow, tcasmin);
> +
> + iowrite32((tsustart - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_TSU_START_OFFSET);
> + iowrite32((thdstart - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_THD_START_OFFSET);
> + iowrite32((tsustop - XI3C_CYCLE_ADJUST) & XI3C_TIMING_MASK,
> + master->membase + XI3C_TSU_STOP_OFFSET);
> +
> + return 0;
> +}
> +
> +static int xi3c_master_bus_init(struct i3c_master_controller *m) {
> + struct xi3c_master *master = to_xi3c_master(m);
> + struct i3c_bus *bus = i3c_master_get_bus(m);
> + struct i3c_device_info info = {};
> + unsigned long sclhz;
> + u32 pid1_bcr_dcr;
> + u8 mode;
> + int ret;
> +
> + switch (bus->mode) {
> + case I3C_BUS_MODE_MIXED_FAST:
> + case I3C_BUS_MODE_MIXED_LIMITED:
> + case I3C_BUS_MODE_MIXED_SLOW:
> + mode = XI3C_I2C_MODE;
> + sclhz = bus->scl_rate.i2c;
> + break;
> + case I3C_BUS_MODE_PURE:
> + mode = XI3C_SDR_MODE;
> + sclhz = bus->scl_rate.i3c;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + ret = xi3c_clk_cfg(master, sclhz, mode);
> + if (ret)
> + return ret;
> +
> + xi3c_master_init(master);
> +
> + /* Get an address for the master. */
> + ret = i3c_master_get_free_addr(m, 0);
> + if (ret < 0)
> + return ret;
> +
> + info.dyn_addr = ret;
> +
> + /* Write the dynamic address value to the address register. */
> + iowrite32(info.dyn_addr, master->membase + XI3C_ADDRESS_OFFSET);
> +
> + /* Read PID, BCR and DCR values, and assign to i3c device info. */
> + pid1_bcr_dcr = ioread32(master->membase + XI3C_PID1_BCR_DCR);
> + info.pid = ((u64)FIELD_GET(XI3C_PID1_MASK, pid1_bcr_dcr) << 32) |
> + ioread32(master->membase + XI3C_PID0_OFFSET);
> + info.bcr = FIELD_GET(XI3C_BCR_MASK, pid1_bcr_dcr);
> + info.dcr = FIELD_GET(XI3C_DCR_MASK, pid1_bcr_dcr);
> +
> + return i3c_master_set_info(&master->base, &info); }
> +
> +static void xi3c_master_bus_cleanup(struct i3c_master_controller *m) {
> + struct xi3c_master *master = to_xi3c_master(m);
> +
> + xi3c_master_disable(master);
> +}
> +
> +static const struct i3c_master_controller_ops xi3c_master_ops = {
> + .bus_init = xi3c_master_bus_init,
> + .bus_cleanup = xi3c_master_bus_cleanup,
> + .do_daa = xi3c_master_do_daa,
> + .supports_ccc_cmd = xi3c_master_supports_ccc_cmd,
> + .send_ccc_cmd = xi3c_master_send_ccc_cmd,
> + .i3c_xfers = xi3c_master_i3c_xfers,
> + .i2c_xfers = xi3c_master_i2c_xfers,
> +};
> +
> +static int xi3c_master_probe(struct platform_device *pdev) {
> + struct xi3c_master *master;
> + int ret;
> +
> + master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
> + if (!master)
> + return -ENOMEM;
> +
> + master->dev = &pdev->dev;
> +
> + master->membase = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(master->membase))
> + return dev_err_probe(master->dev, PTR_ERR(master->membase),
> + "Failed to map registers\n");
> +
> + master->pclk = devm_clk_get_enabled(master->dev, NULL);
> + if (IS_ERR(master->pclk))
> + return dev_err_probe(master->dev, PTR_ERR(master->pclk),
> + "Failed to get and enable clock\n");
> +
> + ret = devm_mutex_init(master->dev, &master->lock);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, master);
> +
> + return i3c_master_register(&master->base, master->dev,
> + &xi3c_master_ops, false);
> +}
> +
> +static void xi3c_master_remove(struct platform_device *pdev) {
> + struct xi3c_master *master = platform_get_drvdata(pdev);
> +
> + i3c_master_unregister(&master->base);
> +}
> +
> +static const struct of_device_id xi3c_master_of_ids[] = {
> + { .compatible = "xlnx,axi-i3c-1.0" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, xi3c_master_of_ids);
> +
> +static struct platform_driver xi3c_master_driver = {
> + .probe = xi3c_master_probe,
> + .remove = xi3c_master_remove,
> + .driver = {
> + .name = "axi-i3c-master",
> + .of_match_table = xi3c_master_of_ids,
> + },
> +};
> +module_platform_driver(xi3c_master_driver);
> +
> +MODULE_AUTHOR("Manikanta Guntupalli <manikanta.guntupalli@amd.com>");
> +MODULE_AUTHOR("Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>");
> +MODULE_AUTHOR("Shubham Patil <shubhamsanjay.patil@amd.com>");
I don't agree with adding new authors in V9.
This driver is already part of the downstream kernel and is being used:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/i3c/master/amd-i3c-master.c
The main purpose of V9 is to drop the framework-level support added in recent versions. The current V9 patch is mostly aligned with the initial patch versions (without framework support changes).
Thanks,
Manikanta
> +MODULE_DESCRIPTION("AMD AXI I3C master driver");
> MODULE_LICENSE("GPL");
> --
> 2.34.1
^ permalink raw reply
* [PATCH] spi: dt-bindings: microchip,pic32mzda-sqi: Convert to DT schema
From: Udaya Kiran Challa @ 2026-06-24 6:13 UTC (permalink / raw)
To: tsbogend, robh, krzk+dt, conor+dt
Cc: skhan, me, linux-rtc, devicetree, linux-kernel,
Udaya Kiran Challa
Convert Microchip PIC32 Quad SPI controller devicetree binding
from legacy text format to DT schema.
Signed-off-by: Udaya Kiran Challa <challauday369@gmail.com>
---
.../bindings/spi/microchip,pic32mzda-sqi.yaml | 53 +++++++++++++++++++
.../devicetree/bindings/spi/sqi-pic32.txt | 18 -------
2 files changed, 53 insertions(+), 18 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/sqi-pic32.txt
diff --git a/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml
new file mode 100644
index 000000000000..39f06b61e894
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,pic32mzda-sqi.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,pic32mzda-sqi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PIC32MZDA Quad SPI controller
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ const: microchip,pic32mzda-sqi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: spi_ck
+ - const: reg_ck
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,pic32-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ sqi1: spi@1f8e2000 {
+ compatible = "microchip,pic32mzda-sqi";
+ reg = <0x1f8e2000 0x200>;
+ interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
+ clock-names = "spi_ck", "reg_ck";
+ };
diff --git a/Documentation/devicetree/bindings/spi/sqi-pic32.txt b/Documentation/devicetree/bindings/spi/sqi-pic32.txt
deleted file mode 100644
index c82d021bce50..000000000000
--- a/Documentation/devicetree/bindings/spi/sqi-pic32.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-Microchip PIC32 Quad SPI controller
------------------------------------
-Required properties:
-- compatible: Should be "microchip,pic32mzda-sqi".
-- reg: Address and length of SQI controller register space.
-- interrupts: Should contain SQI interrupt.
-- clocks: Should contain phandle of two clocks in sequence, one that drives
- clock on SPI bus and other that drives SQI controller.
-- clock-names: Should be "spi_ck" and "reg_ck" in order.
-
-Example:
- sqi1: spi@1f8e2000 {
- compatible = "microchip,pic32mzda-sqi";
- reg = <0x1f8e2000 0x200>;
- clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
- clock-names = "spi_ck", "reg_ck";
- interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
- };
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 2/2] arm64: dts: socfpga: agilex72: Add initial device tree
From: sashiko-bot @ 2026-06-24 6:15 UTC (permalink / raw)
To: muhammad.nazim.amirul.nazle.asmade; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260624055644.7508-3-muhammad.nazim.amirul.nazle.asmade@altera.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing VGIC maintenance interrupt breaks KVM virtualization support.
- [Medium] Invalid properties in static `reserved-memory` nodes (ATF and service buffers).
- [Medium] Missing CPU capacity properties for heterogeneous ARMv9 scheduling.
--
commit aab0b211863fe0abf5dfd65b45d11637ecf3a3d5
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
arm64: dts: socfpga: agilex72: Add initial device tree
This commit introduces the initial device tree support for the Intel
SoCFPGA Agilex72 platform, including the SoC DTSI and the SoCDK board
DTS.
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> new file mode 100644
> index 0000000000000..2a4ad4130f37e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi
> @@ -0,0 +1,128 @@
[ ... ]
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + atf_reserved: atf@80000000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x80000000 0x0 0x100000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> +
> + service_reserved: svcbuffer@80100000 {
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x80100000 0x0 0xf00000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
[Severity: Medium]
Is it intentional to expose the Arm Trusted Firmware secure memory region
as a shared DMA pool? The compatible = "shared-dma-pool" property here could
expose secure EL3 memory as a Linux DMA pool, which could trigger a fatal
secure monitor abort if a driver attempts to attach and access it.
Also, both the atf_reserved and service_reserved nodes define a static
physical address using the reg property, but they also include the alignment
property. Does this violate the devicetree schema? The reserved-memory.yaml
schema dictates that alignment is strictly for dynamically placed allocations
and is mutually exclusive with reg.
[ ... ]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a520";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x0>;
> + };
[ ... ]
> + cpu2: cpu@200 {
> + compatible = "arm,cortex-a720";
> + device_type = "cpu";
> + enable-method = "psci";
> + reg = <0x200>;
> + };
[Severity: Medium]
Since the Agilex72 features a heterogeneous cluster with Cortex-A520
and Cortex-A720 cores, does this cpus node need capacity-dmips-mhz
properties?
Without these properties or an active OPP table, the Energy Aware Scheduling
(EAS) subsystem cannot discover the relative compute capacities, and might
assume all cores are identical. This could cause heavy workloads to be
scheduled suboptimally on the slower A520 cores.
[ ... ]
> + intc: interrupt-controller@7000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x7000000 0x0 0x10000>,
> + <0x0 0x7080000 0x0 0x100000>;
> + ranges;
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-controller;
[Severity: High]
Is the VGIC maintenance interrupt missing from this node?
KVM relies on this interrupt (typically GIC_PPI 9) to populate gic_v3_kvm_info
during the GICv3 driver initialization in drivers/irqchip/irq-gic-v3.c.
Without it, the driver skips VGIC setup, which leaves hardware virtualization
support broken on this platform.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260624055644.7508-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2
^ permalink raw reply
* [PATCH v4 0/2] arm64: dts: socfpga: Enable SMMU and add DMA coherency for XGMAC
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 6:22 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
This series enables the SMMU and adds DMA coherency support for the
XGMAC nodes across the affected board device trees.
Patch 1 enables the SMMU for the SoCFPGA board device trees where it
was missing. The SoC uses a different memory-mapped base address for
its peripherals, which requires the SMMU to be active so that the
Secure Device Manager (SDM) can correctly access those regions through
address translation.
Patch 2 adds the dma-coherent property to the XGMAC nodes. The SMMU
is enabled and transactions going through it are cache coherent.
Adding dma-coherent prevents redundant cache flush/invalidate
operations and potential stale data issues.
Changes in v4:
- Remove status = "disabled" instead of setting status = "okay", as nodes
without a status property are enabled by default
Changes in v3:
- Fix commit header to follow subsystem naming convention (patches 1 and 2)
- Remove commit body line that restated the subject
- Clarify which file had the SMMU disabled
Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files
- Move dma-coherent property into the base DTSI file instead of individual DTS files
- Improve commit messages and cover letter descriptions with more context on why the changes are needed
Nazim Amirul (2):
arm64: dts: socfpga: agilex5: Enable the SMMU
arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--
2.43.7
^ permalink raw reply
* [PATCH v4 1/2] arm64: dts: socfpga: agilex5: Enable the SMMU
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 6:22 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
In-Reply-To: <20260624062203.12221-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different
memory-mapped base address for its peripherals, which requires the SMMU
to be active so that the Secure Device Manager (SDM) can correctly
access those regions through address translation.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v4:
- Remove status = "disabled" instead of setting status = "okay", as nodes
without a status property are enabled by default
Changes in v3:
- Fix commit header to follow subsystem naming convention
- Remove commit body line that restated the subject
- Clarify which file had the SMMU disabled
Changes in v2:
- Move SMMU enable into the base DTSI file instead of individual DTS files
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index b06c6d5d60ee..daa1f9e0d1f5 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -385,7 +385,6 @@ smmu: iommu@16000000 {
interrupt-names = "eventq", "gerror", "priq";
dma-coherent;
#iommu-cells = <1>;
- status = "disabled";
};
spi0: spi@10da4000 {
--
2.43.7
^ permalink raw reply related
* [PATCH v4 2/2] arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-24 6:22 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
In-Reply-To: <20260624062203.12221-1-muhammad.nazim.amirul.nazle.asmade@altera.com>
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Changes in v3:
- Fix commit header to follow subsystem naming convention (add agilex5: prefix)
Changes in v2:
- Move dma-coherent property into the base DTSI file instead of individual DTS files
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index daa1f9e0d1f5..3822f06c2694 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -576,6 +576,7 @@ gmac0: ethernet@10810000 {
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
snps,clk-csr = <0>;
iommus = <&smmu 1>;
+ dma-coherent;
status = "disabled";
stmmac_axi_emac0_setup: stmmac-axi-config {
@@ -689,6 +690,7 @@ gmac1: ethernet@10820000 {
altr,sysmgr-syscon = <&sysmgr 0x48 0>;
snps,clk-csr = <0>;
iommus = <&smmu 2>;
+ dma-coherent;
status = "disabled";
stmmac_axi_emac1_setup: stmmac-axi-config {
@@ -802,6 +804,7 @@ gmac2: ethernet@10830000 {
altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
snps,clk-csr = <0>;
iommus = <&smmu 3>;
+ dma-coherent;
status = "disabled";
stmmac_axi_emac2_setup: stmmac-axi-config {
--
2.43.7
^ permalink raw reply related
* Re: [PATCH v5 3/3] MAINTAINERS: add entry for MAX86150 IIO health driver
From: Krzysztof Kozlowski @ 2026-06-24 6:22 UTC (permalink / raw)
To: Md Shofiqul Islam, linux-iio
Cc: jic23, lars, conor, conor+dt, robh, krzk+dt, devicetree,
linux-kernel
In-Reply-To: <20260623201124.18271-4-shofiqtest@gmail.com>
On 23/06/2026 22:11, Md Shofiqul Islam wrote:
> Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
> ---
> MAINTAINERS | 7 +++++++
> 1 file changed, 7 insertions(+)
>
You need to slow down, please. One version per 24h.
And the last one is not even correct anymore...
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: iio: dac: Add DAC8163
From: Lukas Metz @ 2026-06-24 6:25 UTC (permalink / raw)
To: David Lechner
Cc: Lukas Metz, Jonathan Cameron, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-kernel,
linux-iio, devicetree
In-Reply-To: <5a19c272-e8fc-4fa9-b137-842b6ed6649b@baylibre.com>
Thanks a lot for the review. This is my first time submitting a
patch so im grateful for the detailed comments and suggestions.
On Tue, Jun 23, 2026 at 02:17:04PM -0500, David Lechner wrote:
> It is more logical to put the dt-bindings patch first in the series
> before the driver that makes use of it.
I will reorder the commits in v2.
> There are a couple of more SPI properties needed since this is not a "normal"
> SPI device. We can only write and not read because there is no D_OUT pin. So
>
> spi-rx-bus-width:
> items:
> - const: 0
>
> will describe this.
I will the add the suggested changes to v2. Are there any other poperties
i have missed? Same for the other comments regarding vendor-prefix,
spi-max-frequency, avdd-supply and vref supply name.
> We also want the binding to be complete even if the driver doesn't all of it, so
> `clear-gpios` and `sync-gpios` probably make sense too.
SYNC pin is the chip select pin of the device as described below. In
that case i dont need to add it here right?
> Usually, we don't bother with a property like this since it is redundant.
> If an external reference supply is given, then it gets used, otherwise
> the internal reference is used.
That sounds logical. I will remove the property completly.
> These chips don't appear to have a chip select pin, so this comment
> doesn't make sense to me. More logical would be to just use dac@0
> and reg = <0>; since it should just be ignored.
The SYNC pin on the device acts like a chip select pin.
According to the datasheet: when the pin goes low it enables the input shift
register. At least that was my understanding. On my board i have tested the
driver with the chip select signal connected to the SYNC pin. The
example comes straight from my own device tree where i have two devices
on the bus. Thats why i used reg<1> here but i can change it to 0 and
remove the comment.
> The pin is marked active low in the datasheet, so I would expect
> this to be GPIO_ACTIVE_LOW.
I wasnt sure about that. The pin needs to be held low continuously. I
thought when the pin is marked active low and i initialize the pin with
GPIOD_OUT_LOW the result will be that the pin is held high. To match the
datasheet description seems logical though.
^ permalink raw reply
* Re: [PATCH] dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDA 850
From: Krzysztof Kozlowski @ 2026-06-24 6:26 UTC (permalink / raw)
To: david, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260623-sda850-v1-1-ddd8e62c85d8@ixit.cz>
On 23/06/2026 20:41, David Heidelberg via B4 Relay wrote:
> From: David Heidelberg <david@ixit.cz>
>
> Add SoC ID for Qualcomm Snapdragon SDA850.
>
> Signed-off-by: David Heidelberg <david@ixit.cz>
> ---
> Will be used by Comma three.
Can you provide a link?
In general this must be send with the user.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 3/4] drm/ssd130x: Add SSD135X_FAMILY and SSD1351 support
From: Markus Elfring @ 2026-06-24 6:27 UTC (permalink / raw)
To: Amit Barzilai, dri-devel, devicetree, linux-fbdev, linux-staging
Cc: LKML, Adam Azuddin, Andy Shevchenko, Chintan Patel, Conor Dooley,
David Airlie, Greg Kroah-Hartman, Helge Deller,
Javier Martinez Canillas, Krzysztof Kozlowski, Maarten Lankhorst,
Maxime Ripard, Rob Herring, Simona Vetter, Thomas Zimmermann
In-Reply-To: <20260623213447.30196-1-amit.barzilai22@gmail.com>
>>> +++ b/drivers/gpu/drm/solomon/ssd130x.c
>>> @@ -146,6 +146,33 @@
>>> #define SSD133X_COLOR_DEPTH_256 0x0
>>> #define SSD133X_COLOR_DEPTH_65K 0x1
>>>
>>> +/* ssd135x commands */
>>> +#define SSD135X_SET_COL_RANGE 0x15
>>> +#define SSD135X_WRITE_RAM 0x5c
>>> +#define SSD135X_SET_ROW_RANGE 0x75
>> [...]
>>
>> How do you think about to use an enumeration for such data?
>> https://en.wikipedia.org/wiki/Enumerated_type#C_and_syntactically_similar_languages
>
> Thank you for the suggestion.
>
> I used #define to stay consistent with the rest of ssd130x.c, where the
> command constants for the other families are all defined the same way.
Will any further adjustments become more interesting?
> In my opinion an enum could be a readable solution for these values,
This is nice.
> but I don't think the switch should be included in this series.
What does hinder you to take another design option better into account?
Regards,
Markus
^ permalink raw reply
* Re: [PATCH v4 2/2] arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
From: sashiko-bot @ 2026-06-24 6:30 UTC (permalink / raw)
To: muhammad.nazim.amirul.nazle.asmade; +Cc: robh, devicetree, conor+dt
In-Reply-To: <20260624062203.12221-3-muhammad.nazim.amirul.nazle.asmade@altera.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] Omission of `dma-coherent` property on SMMU-routed DMA master nodes (`usb0`, `dmac0`, `dmac1`) causes potential data corruption.
--
commit d5421d52fec812147859d426e90e92990eb7c1b8
Author: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes
The SMMU is enabled and transactions going through it are cache
coherent. Add the dma-coherent property to the XGMAC nodes to prevent
redundant cache flush/invalidate operations and potential stale data
issues.
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 654f94ded1e85..3de424ae3b8ba 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -576,6 +576,7 @@ gmac0: ethernet@10810000 {
> altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> snps,clk-csr = <0>;
> iommus = <&smmu 1>;
> + dma-coherent;
> status = "disabled";
>
> stmmac_axi_emac0_setup: stmmac-axi-config {
[Severity: High]
This is a pre-existing issue, but since the commit message establishes that
transactions going through the SMMU are cache coherent, should the
dma-coherent property also be added to other SMMU-routed DMA master nodes?
Looking at arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi, the dmac0, dmac1,
and usb0 nodes also route through the SMMU but lack the dma-coherent property:
dmac0: dma-controller@0 {
...
iommus = <&smmu 8>;
};
If the kernel incorrectly treats these devices as non-coherent, allocating
a DMA buffer for reading (DMA_FROM_DEVICE) might result in a cache
invalidation (DC IVAC via dmac_inv_range()) discarding dirty cache lines
without writing them back to memory.
This would cause the CPU to subsequently read stale data, permanently losing
the data the device just wrote.
Could this incomplete fix leave usb0, dmac0, and dmac1 vulnerable to data
corruption and loss?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260624062203.12221-1-muhammad.nazim.amirul.nazle.asmade@altera.com?part=2
^ permalink raw reply
* Re: [PATCH v7 2/6] dt-bindings: remoteproc: qcom: move interrupts and interrupt-names list out of pas-common
From: Krzysztof Kozlowski @ 2026-06-24 6:33 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Luca Weiss, Bartosz Golaszewski, Kumar Patro, Komal Bajaj,
Konrad Dybcio, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
In-Reply-To: <20260623-knp-soccp-v7-2-1ec7bb5c9fec@oss.qualcomm.com>
On Tue, Jun 23, 2026 at 03:05:18AM -0700, Jingyi Wang wrote:
> Move interrupts and interrupt-names list out of pas-common since they
> will be redefined differently for Kaanapali SoCCP.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH] arm64: dts: qcom: kaanapali: fix traceNoC probe issue
From: Jie Gan @ 2026-06-24 6:33 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jingyi Wang, Jie Gan, Abel Vesa
Cc: Konrad Dybcio, linux-arm-msm, devicetree, linux-kernel
Fix probing of the traceNoC device by switching from the AMBA bus to
the platform itnoc driver.
Fixes: f73959d86c15 ("arm64: dts: qcom: kaanapali: add coresight nodes")
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7aa9653bd456..84561b5faf81 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -5003,12 +5003,12 @@ tpdm_pcie_rscc_out: endpoint {
};
};
- tn@111b8000 {
- compatible = "qcom,coresight-tnoc", "arm,primecell";
+ itnoc@111b8000 {
+ compatible = "qcom,coresight-itnoc";
reg = <0x0 0x111b8000 0x0 0x4200>;
clocks = <&aoss_qmp>;
- clock-names = "apb_pclk";
+ clock-names = "apb";
in-ports {
#address-cells = <1>;
---
base-commit: 4e5dfb7c84012007c3c7061126491bbc92d71bf1
change-id: 20260624-fix-tracenoc-probe-issue-c6429da28df4
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH v7 3/6] dt-bindings: remoteproc: qcom: Document pas for SoCCP on Kaanapali and Glymur platforms
From: Krzysztof Kozlowski @ 2026-06-24 6:35 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Luca Weiss, Bartosz Golaszewski, Kumar Patro, Komal Bajaj,
Konrad Dybcio, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
In-Reply-To: <20260623-knp-soccp-v7-3-1ec7bb5c9fec@oss.qualcomm.com>
On Tue, Jun 23, 2026 at 03:05:19AM -0700, Jingyi Wang wrote:
> Document the component used to boot SoCCP on Kaanapali SoC and add
> compatible for Glymur SoCCP which could fallback to Kaanapali. Extend
> the "qcom,smem-states", "qcom,smem-state-names" in the pas-common
> and add maxItems constraints for SMEM properties in the documents
> that reference to pas-common.
>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v7 4/6] dt-bindings: remoteproc: qcom: Document pas for SoCCP on Hawi and Maili SoC
From: Krzysztof Kozlowski @ 2026-06-24 6:36 UTC (permalink / raw)
To: Jingyi Wang
Cc: Bjorn Andersson, Mathieu Poirier, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Manivannan Sadhasivam,
Luca Weiss, Bartosz Golaszewski, Kumar Patro, Komal Bajaj,
Konrad Dybcio, aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel,
Mukesh Ojha
In-Reply-To: <20260623-knp-soccp-v7-4-1ec7bb5c9fec@oss.qualcomm.com>
On Tue, Jun 23, 2026 at 03:05:20AM -0700, Jingyi Wang wrote:
> From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
>
> Document SoCCP remote processor used on Qualcomm Hawi and Maili SoC which
> is fully compatible with Kaanapali.
>
> Co-developed-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
> Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> .../devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH v8] arm64: dts: qcom: kodiak: Add EL2 overlay
From: Mukesh Ojha @ 2026-06-24 6:39 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Mukesh Ojha, Sumit Garg
All the existing variants Kodiak boards are using Gunyah hypervisor
which means that, so far, Linux-based OS could only boot in EL1 on those
devices. However, it is possible for us to boot Linux at EL2 on these
devices [1].
When running under Gunyah, the remote processor firmware IOMMU
streams are controlled by Gunyah. However, without Gunyah, the IOMMU is
managed by the consumer of this DeviceTree. Therefore, describe the
firmware streams for each remote processor.
Add a EL2-specific DT overlay and apply it to Kodiak IOT variant
devices to create -el2.dtb for each of them alongside "normal" dtb.
Note that modem and media subsystems haven't been supported yet due
to missing dependencies. For GPU to work, zap shader is disabled and
in EL2 mode the kernel owns hardware watchdog which is enabled here.
And for wifi to work wpss copy engine memory need to be mapped for
WPSS firmware to work which is aligning with sc7280 chrome.
[1]
https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi
Co-developed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
Changes in v8: https://lore.kernel.org/lkml/20260522115936.201208-2-sumit.garg@kernel.org/
- Added a wpss copy engine memory similar to chrome for Wifi to work.
- WPSS does not have firmware Stream, so that was removed.
- Added wifi streams similar to chrome for wifi to work.
- Removed this patch from Generic Pas patch series, can be followed
separately.
- Moved Sumit as co-author as part of modification done to the patch
in the past.
- Added some more kodiak's board variants in the makefile.
Changes in v1-v7:
- mpss was disabled and will be enabled once the dependencies patches
get merged.
arch/arm64/boot/dts/qcom/Makefile | 12 ++++++
arch/arm64/boot/dts/qcom/kodiak-el2.dtso | 52 ++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +-
3 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/qcom/kodiak-el2.dtso
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 6f33c4e2f09c..d2cee1190954 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -164,7 +164,11 @@ purwa-iot-evk-el2-dtbs := purwa-iot-evk.dtb x1-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += purwa-iot-evk-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-fairphone-fp5.dtb
+
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
+qcm6490-idp-el2-dtbs := qcm6490-idp.dtb kodiak-el2.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp-el2.dtb
+
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-particle-tachyon.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
@@ -176,12 +180,20 @@ qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride-el2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-radxa-dragon-q6a.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
+qcs6490-rb3gen2-el2-dtbs := qcs6490-rb3gen2.dtb kodiak-el2.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-el2.dtb
qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb
+qcs6490-rb3gen2-industrial-mezzanine-el2-dtbs := qcs6490-rb3gen2-industrial-mezzanine.dtb kodiak-el2.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-el2.dtb
+
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb
+qcs6490-rb3gen2-vision-mezzanine-el2-dtbs := qcs6490-rb3gen2-vision-mezzanine.dtb kodiak-el2.dtbo
+dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine-el2.dtb
+
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
diff --git a/arch/arm64/boot/dts/qcom/kodiak-el2.dtso b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso
new file mode 100644
index 000000000000..91e4cda45b49
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * Kodiak specific modifications required to boot in EL2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+&gpu_zap_shader {
+ status = "disabled";
+};
+
+&remoteproc_adsp {
+ iommus = <&apps_smmu 0x1800 0x0>;
+};
+
+&remoteproc_cdsp {
+ iommus = <&apps_smmu 0x11a0 0x0400>;
+};
+
+&remoteproc_mpss {
+ status = "disabled";
+};
+
+&reserved_memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ wlan_ce_mem: wlan-ce@4cd000 {
+ no-map;
+ reg = <0x0 0x004cd000 0x0 0x1000>;
+ };
+};
+
+&venus {
+ status = "disabled";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
+ status = "okay";
+
+ wifi-firmware {
+ iommus = <&apps_smmu 0x1c02 0x1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index fa540d8c2615..2486d15fa2ba 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -91,7 +91,7 @@ sleep_clk: sleep-clk {
};
};
- reserved-memory {
+ reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH] arm64: dts: qcom: kaanapali: fix traceNoC probe issue
From: sashiko-bot @ 2026-06-24 6:49 UTC (permalink / raw)
To: Jie Gan; +Cc: devicetree, robh, conor+dt
In-Reply-To: <20260624-fix-tracenoc-probe-issue-v1-1-bcc785198fc5@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
New issues:
- [High] Switching traceNoC to the platform itnoc driver breaks trace enablement for connected sources.
Pre-existing issues:
- [High] Probe error path unconditionally invokes PM runtime suspend, causing a NULL pointer dereference.
- [Medium] Driver removal and unbind paths cause a clock enable count underflow warning.
--
commit 152b245041f20740bb96bedaa8fe0632753867d1
Author: Jie Gan <jie.gan@oss.qualcomm.com>
arm64: dts: qcom: kaanapali: fix traceNoC probe issue
This commit fixes probing of the traceNoC device by switching from the AMBA
bus to the platform itnoc driver.
> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> index 7aa9653bd456e..84561b5faf811 100644
> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
> @@ -5003,12 +5003,12 @@ tpdm_pcie_rscc_out: endpoint {
> };
> };
>
> - tn@111b8000 {
> - compatible = "qcom,coresight-tnoc", "arm,primecell";
> + itnoc@111b8000 {
> + compatible = "qcom,coresight-itnoc";
[Severity: High]
This is a pre-existing issue, but does switching to the platform driver expose
a NULL pointer dereference if probing fails?
If _tnoc_probe() fails in itnoc_probe(), the code unconditionally calls
pm_runtime_put() before drvdata is fully initialized. This triggers:
drivers/hwtracing/coresight/coresight-tnoc.c:itnoc_runtime_suspend() {
struct trace_noc_drvdata *drvdata = dev_get_drvdata(dev);
clk_disable_unprepare(drvdata->pclk);
}
Could this dereference a NULL drvdata during the error path?
[Severity: Medium]
This isn't a bug introduced by this patch, but does using the itnoc driver
lead to a clock enable count underflow on unbind?
The clock is fetched with managed enablement in _tnoc_probe():
ret = coresight_get_enable_clocks(dev, &drvdata->pclk, NULL);
This registers a devres cleanup action. However, the driver also manages the
clock manually:
drivers/hwtracing/coresight/coresight-tnoc.c:itnoc_runtime_suspend() {
clk_disable_unprepare(drvdata->pclk);
}
If the driver is unbound while in a runtime-suspended state, will the devres
framework attempt to disable the already-disabled clock?
[Severity: High]
Will changing the compatible string without "arm,primecell" break trace
enablement for connected sources like TPDM?
When probed as a platform device, the driver initializes atid to unsupported:
drivers/hwtracing/coresight/coresight-tnoc.c:trace_noc_init_default_data() {
if (!dev_is_amba(drvdata->dev)) {
drvdata->atid = -EOPNOTSUPP;
return 0;
}
}
During trace enablement, coresight_path_assign_trace_id() could fail because
-EOPNOTSUPP is evaluated as an invalid trace ID:
drivers/hwtracing/coresight/coresight-core.c:coresight_path_assign_trace_id() {
if (!IS_VALID_CS_TRACE_ID(trace_id))
return -EINVAL;
}
Does this immediately abort trace enablement for any source relying on this
traceNoC?
> reg = <0x0 0x111b8000 0x0 0x4200>;
>
> clocks = <&aoss_qmp>;
> - clock-names = "apb_pclk";
> + clock-names = "apb";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260624-fix-tracenoc-probe-issue-v1-1-bcc785198fc5@oss.qualcomm.com?part=1
^ permalink raw reply
* Re: [PATCH v6 1/4] dt-bindings: soc: cix: add sky1 audss cru controller
From: Krzysztof Kozlowski @ 2026-06-24 6:49 UTC (permalink / raw)
To: joakim.zhang
Cc: mturquette, sboyd, bmasney, robh, krzk+dt, conor+dt, p.zabel,
gary.yang, cix-kernel-upstream, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260623070805.211019-2-joakim.zhang@cixtech.com>
On Tue, Jun 23, 2026 at 03:08:02PM +0800, joakim.zhang@cixtech.com wrote:
> From: Joakim Zhang <joakim.zhang@cixtech.com>
>
> The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU)
> groups clock muxing, gating and block-level software reset control
> in a single register block.
>
> Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com>
> ---
> .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 +++++++++++++++++++
> .../dt-bindings/clock/cix,sky1-audss-cru.h | 60 ++++++++++++
> .../dt-bindings/reset/cix,sky1-audss-cru.h | 25 +++++
> 3 files changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml
> create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h
> create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 4/6] dt-bindings: input: sun4i-lradc-keys: Add A100/A133 compatible
From: Krzysztof Kozlowski @ 2026-06-24 6:51 UTC (permalink / raw)
To: Alexander Sverdlin
Cc: linux-arm-kernel, linux-sunxi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Hans de Goede, Dmitry Torokhov, Andre Przywara, Jun Yan,
Lukas Schmid, J. Neuschäfer, Eric Biggers, Michal Simek,
Luca Weiss, Sven Peter, Maxime Ripard, devicetree, linux-kernel,
linux-input
In-Reply-To: <20260623204824.691832-5-alexander.sverdlin@gmail.com>
On Tue, Jun 23, 2026 at 10:48:16PM +0200, Alexander Sverdlin wrote:
> The Allwinner A100/A133 SoCs have an LRADC which is compatible with the
> versions in existing SoCs. Add a compatible string for A100, with the R329
> fallback.
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v5 3/3] MAINTAINERS: add entry for MAX86150 IIO health driver
From: Joshua Crofts @ 2026-06-24 6:53 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Md Shofiqul Islam, linux-iio, jic23, lars, conor, conor+dt, robh,
krzk+dt, devicetree, linux-kernel
In-Reply-To: <25846cbb-8318-43d1-a57e-16734cdad6bd@kernel.org>
On Wed, 24 Jun 2026 08:22:48 +0200
Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 23/06/2026 22:11, Md Shofiqul Islam wrote:
> > Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
> > ---
> > MAINTAINERS | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
>
>
> You need to slow down, please. One version per 24h.
>
> And the last one is not even correct anymore...
Additionally, refrain from sending a separate patch for MAINTAINERS,
fold the new addition into your dt-binding patch, and then add the
F: entry for the driver code in the actual driver patch.
--
Kind regards
CJD
^ permalink raw reply
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