* Re: [PATCH v9 01/14] dt-bindings: media: qcom,glymur-iris: Add glymur video codec
From: Vishnu Reddy @ 2026-07-17 3:48 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Vikash Garodia, Dikshita Agarwal, Abhinav Kumar,
Bryan O'Donoghue, Dmitry Baryshkov, Mauro Carvalho Chehab,
Joerg Roedel (AMD), Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Stanimir Varbanov,
Bjorn Andersson, Konrad Dybcio, linux-kernel, linux-media,
linux-arm-msm, iommu, devicetree, Krzysztof Kozlowski
In-Reply-To: <20260716-soft-dexterous-adder-badb49@quoll>
On 7/16/2026 1:10 PM, Krzysztof Kozlowski wrote:
> On Wed, Jul 15, 2026 at 07:39:55PM +0530, Vishnu Reddy wrote:
>> Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
>> is a new generation of video IP that introduces a dual-core architecture.
>> The second core brings its own power domain, clocks, and reset lines,
>> requiring additional power domains and clocks in the power sequence.
>> The current maxItems constraints for clocks and power-domains in the
>> common venus schema were sized for platforms available at the time of
>> authoring. The glymur platform introduces a dual core architecture
>> that requires more clocks and power domains, exceeding these limits.
>> Raise maxItems for clocks, clock-names, power-domains and
>> power-domain-names to accommodate the glymur platform.
>> The glymur platform-specific schema have fixed constraints for these
>> properties, so the common schema only acts as an upper bound.
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> You must drop the tag, you changed the binding significantly without any
> doubts.
Ack
> Best regards,
> Krzysztof
>
^ permalink raw reply
* [PATCH v3 1/8] dt-bindings: arm: axiado: add AX3005 EVK
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang,
Conor Dooley
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add device tree binding schema for the Axiado AX3005 SoC and its
associated evaluation board. This binding will be used for the
board-level DTS files that support the AX3005 platforms.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/arm/axiado.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/axiado.yaml b/Documentation/devicetree/bindings/arm/axiado.yaml
index bfabe7b32e65..008d2b1d4e62 100644
--- a/Documentation/devicetree/bindings/arm/axiado.yaml
+++ b/Documentation/devicetree/bindings/arm/axiado.yaml
@@ -20,4 +20,10 @@ properties:
- axiado,ax3000-evk # Axiado AX3000 Evaluation Board
- const: axiado,ax3000 # Axiado AX3000 SoC
+ - description: AX3005 based boards
+ items:
+ - enum:
+ - axiado,ax3005-evk # Axiado AX3005 Evaluation Board
+ - const: axiado,ax3005 # Axiado AX3005 SoC
+
additionalProperties: true
--
2.34.1
^ permalink raw reply related
* [PATCH v3 3/8] dt-bindings: i2c: cdns: add Axiado AX3005 I2C variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 I2C controller. So far, no changes
are known, so it can fall back to the cdns,i2c-r1p14 compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
index 9f1d35ce1fe8..4dc69d54f75d 100644
--- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
+++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
@@ -14,9 +14,13 @@ allOf:
properties:
compatible:
- enum:
- - cdns,i2c-r1p10 # cadence i2c controller version 1.0
- - cdns,i2c-r1p14 # cadence i2c controller version 1.4
+ oneOf:
+ - enum:
+ - cdns,i2c-r1p10 # cadence i2c controller version 1.0
+ - cdns,i2c-r1p14 # cadence i2c controller version 1.4
+ - items:
+ - const: axiado,ax3005-i2c
+ - const: cdns,i2c-r1p14
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply related
* [PATCH v3 0/8] arm64: Add Axiado AX3005 SoC and EVK support
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang,
Conor Dooley
This series adds initial device tree support for the Axiado AX3005 SoC
and its evaluation board (EVK).
The AX3005 uses Cadence-derived UART/I2C/I3C/GPIO and Synopsys
DesignWare SPI IP blocks. These are already described by
existing bindings, so the device tree reuses the "axiado,ax3000-*",
"cdns,*" and "snps,*" compatible strings; only a new SoC/board
level compatible is added.
Patch 1 adds the AX3005 board/SoC compatible strings to the Axiado
platform binding.
Patch 2 adds the AX3005 SoC dtsi, the EVK board dts, and the Makefile
entry. The EVK enables the CPUs, timer, GPIO, UART, I2C, I3C, SPI and
USB controllers.
Validated with:
- make CHECK_DTBS=y axiado/ax3005-evk.dtb
- make dt_binding_check DT_SCHEMA_FILES=axiado.yaml
- boot-tested on the AX3005 EVK (to init CLI via ramfs)
Signed-off-by: Swark Yang <syang@axiado.com>
---
Changes in v3:
- Added SoC-specific compatibles (e.g., axiado,ax3005-gpio) with appropriate
fallbacks to all IP blocks (UART, I3C, I2C, SPI, USB, GPIO).
- Added corresponding dt-bindings patches for all updated IPs.
- Renamed l2-cache0 node to l2-cache to drop the unnecessary unit address.
- Fixed DT node sorting.
- Link to v2: https://lore.kernel.org/r/20260705-upstream-axiado-ax3005-upstream-v2-0-2dfbd1448f81@axiado.com
Changes in v2:
- Confirmed with internal team that AX3005 BootROM multiplexes the
single release address for SMP bring-up.
- Corrected architectural timer PPIs and VGIC maintenance interrupt
polarity to active-low.
- Aligned memory node unit-address with reg base address
(@81000000).
- Removed 'arm,cpu-registers-not-fw-configured' property from the
timer node.
- Collected Conor Dooley's Acked-by for the dt-binding patch.
- Link to v1: https://lore.kernel.org/r/20260624-upstream-axiado-ax3005-upstream-v1-0-c05bd0bc9124@axiado.com
---
Swark Yang (8):
dt-bindings: arm: axiado: add AX3005 EVK
dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant
dt-bindings: i2c: cdns: add Axiado AX3005 I2C variant
dt-bindings: i3c: cdns: add Axiado AX3005 I3C variant
dt-bindings: serial: cdns: add Axiado AX3005 UART variant
dt-bindings: spi: dw-apb-ssi: add Axiado AX3005 SPI variant
dt-bindings: usb: generic-xhci: add Axiado AX3005 xHCI variant
arm64: dts: axiado: Add initial support for AX3005 SoC and eval board
Documentation/devicetree/bindings/arm/axiado.yaml | 6 +
.../devicetree/bindings/gpio/cdns,gpio.yaml | 7 +-
.../devicetree/bindings/i2c/cdns,i2c-r1p10.yaml | 10 +-
.../devicetree/bindings/i3c/cdns,i3c-master.yaml | 1 +
.../devicetree/bindings/serial/cdns,uart.yaml | 1 +
.../devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 +
.../devicetree/bindings/usb/generic-xhci.yaml | 4 +
arch/arm64/boot/dts/axiado/Makefile | 1 +
arch/arm64/boot/dts/axiado/ax3005-evk.dts | 327 ++++++++
arch/arm64/boot/dts/axiado/ax3005.dtsi | 842 +++++++++++++++++++++
10 files changed, 1198 insertions(+), 5 deletions(-)
---
base-commit: 2b414a95b8f7307d42173ba9e580d6d3e2bcbfce
change-id: 20260617-upstream-axiado-ax3005-upstream-bb09780a2fdf
Best regards,
--
Swark Yang <syang@axiado.com>
^ permalink raw reply
* [PATCH v3 4/8] dt-bindings: i3c: cdns: add Axiado AX3005 I3C variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 I3C master. So far, no changes
are known, so it can fall back to the cdns,i3c-master compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
index 6fa3078074d0..280f0ada3c43 100644
--- a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
+++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- axiado,ax3000-i3c
+ - axiado,ax3005-i3c
- const: cdns,i3c-master
reg:
--
2.34.1
^ permalink raw reply related
* [PATCH v3 5/8] dt-bindings: serial: cdns: add Axiado AX3005 UART variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 UART controller. So far, no changes
are known, so it can fall back to the cdns,uart-r1p12 compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/serial/cdns,uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
index 9d3e5c1d8502..11292de42c67 100644
--- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- axiado,ax3000-uart
+ - axiado,ax3005-uart
- xlnx,zynqmp-uart
- const: cdns,uart-r1p12
--
2.34.1
^ permalink raw reply related
* [PATCH v3 7/8] dt-bindings: usb: generic-xhci: add Axiado AX3005 xHCI variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 xHCI controller. So far, no changes
are known, so it can fall back to the generic-xhci compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/usb/generic-xhci.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/generic-xhci.yaml b/Documentation/devicetree/bindings/usb/generic-xhci.yaml
index 62678abd74b5..d7fb0301fe4c 100644
--- a/Documentation/devicetree/bindings/usb/generic-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-xhci.yaml
@@ -14,6 +14,10 @@ properties:
oneOf:
- description: Generic xHCI device
const: generic-xhci
+ - description: Axiado AX3005 SoC xHCI controller
+ items:
+ - const: axiado,ax3005-xhci
+ - const: generic-xhci
- description: Armada 375/38x SoCs
items:
- enum:
--
2.34.1
^ permalink raw reply related
* [PATCH v3 2/8] dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 GPIO controller. So far, no changes
are known, so it can fall back to the cdns,gpio-r1p02 compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/gpio/cdns,gpio.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
index a84d60b39459..7eacf5af6554 100644
--- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
@@ -14,8 +14,11 @@ properties:
oneOf:
- const: cdns,gpio-r1p02
- items:
- - enum:
- - axiado,ax3000-gpio
+ - const: axiado,ax3000-gpio
+ - const: cdns,gpio-r1p02
+ - items:
+ - const: axiado,ax3005-gpio
+ - const: axiado,ax3000-gpio
- const: cdns,gpio-r1p02
reg:
--
2.34.1
^ permalink raw reply related
* [PATCH v3 6/8] dt-bindings: spi: dw-apb-ssi: add Axiado AX3005 SPI variant
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add binding for Axiado AX3005 SPI controller. So far, no changes
are known, so it can fall back to the snps,dwc-ssi-1.01a compatible.
Signed-off-by: Swark Yang <syang@axiado.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index 8ebebcebca16..7b16053d2244 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -41,6 +41,10 @@ properties:
enum:
- snps,dw-apb-ssi
- snps,dwc-ssi-1.01a
+ - description: Axiado AX3005 SPI Controller
+ items:
+ - const: axiado,ax3005-spi
+ - const: snps,dwc-ssi-1.01a
- description: Microchip Sparx5 SoC SPI Controller
const: microchip,sparx5-spi
- description: Amazon Alpine SPI Controller
--
2.34.1
^ permalink raw reply related
* [PATCH v3 8/8] arm64: dts: axiado: Add initial support for AX3005 SoC and eval board
From: Swark Yang @ 2026-07-17 3:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Harshit Shah,
Linus Walleij, Bartosz Golaszewski, Jan Kotas, Michal Simek,
Andi Shyti, Przemysław Gaj, Alexandre Belloni, Frank Li,
Boris Brezillon, Greg Kroah-Hartman, Jiri Slaby, Mark Brown,
Mathias Nyman
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-gpio, linux-i2c,
linux-i3c, linux-serial, linux-spi, linux-usb, Swark Yang
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com>
Add initial device tree support for the AX3005 SoC and its evaluation
board. The AX3005 is a multi-core SoC featuring 4 Cortex-A53 cores, and
this adds the CPUs, timer, GPIO, UART, I2C, I3C, SPI and USB
controllers.
Note that all secondary CPUs share a single cpu-release-addr for SMP
bring-up per the AX3005 platform specification.
The AX3005 groups its low-speed controllers into four Slow Peripheral
(SP) blocks (SP0-SP3), each exposing its own I2C/I3C, SPI and UART
instances. The controllers are numbered by their per-SP hardware
instance ID, so the i2cN/spiN/uartN labels and their aliases are
intentionally non-contiguous and do not increase monotonically with
the register address.
Signed-off-by: Swark Yang <syang@axiado.com>
---
arch/arm64/boot/dts/axiado/Makefile | 1 +
arch/arm64/boot/dts/axiado/ax3005-evk.dts | 327 ++++++++++++
arch/arm64/boot/dts/axiado/ax3005.dtsi | 842 ++++++++++++++++++++++++++++++
3 files changed, 1170 insertions(+)
diff --git a/arch/arm64/boot/dts/axiado/Makefile b/arch/arm64/boot/dts/axiado/Makefile
index 6676ad07db61..e71a0850a451 100644
--- a/arch/arm64/boot/dts/axiado/Makefile
+++ b/arch/arm64/boot/dts/axiado/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_AXIADO) += ax3000-evk.dtb
+dtb-$(CONFIG_ARCH_AXIADO) += ax3005-evk.dtb
diff --git a/arch/arm64/boot/dts/axiado/ax3005-evk.dts b/arch/arm64/boot/dts/axiado/ax3005-evk.dts
new file mode 100644
index 000000000000..f6705504679e
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3005-evk.dts
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * DTS file for Axiado AX3005 SoC based EVK
+ * Copyright (c) 2026 Axiado Corporation.
+ */
+
+/dts-v1/;
+
+#include "ax3005.dtsi"
+
+/ {
+ model = "Axiado AX3005 EVK";
+ compatible = "axiado,ax3005-evk", "axiado,ax3005";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i3c12;
+ i2c13 = &i3c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
+ i2c16 = &i2c16;
+ i2c17 = &i2c17;
+ i2c18 = &i2c18;
+ i2c19 = &i2c19;
+ i2c20 = &i2c20;
+ i2c21 = &i2c21;
+ i2c22 = &i2c22;
+ i2c23 = &i2c23;
+ i2c24 = &i2c24;
+ i2c25 = &i2c25;
+ i2c26 = &i2c26;
+ i2c27 = &i2c27;
+ i2c28 = &i2c28;
+ i2c29 = &i2c29;
+ i2c30 = &i2c30;
+ i2c31 = &i2c31;
+ i2c32 = &i2c32;
+ i2c33 = &i2c33;
+ i2c34 = &i2c34;
+ i2c35 = &i2c35;
+ i2c36 = &i2c36;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi5 = &spi5;
+ spi6 = &spi6;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200";
+ };
+
+ memory@81000000 {
+ device_type = "memory";
+ /* Cortex-A53 will use following memory map */
+ reg = <0x0 0x81000000 0x0 0x7f000000>;
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
+&gpio3 {
+ status = "okay";
+};
+
+&gpio4 {
+ status = "okay";
+};
+
+&gpio5 {
+ status = "okay";
+};
+
+&gpio6 {
+ status = "okay";
+};
+
+&gpio7 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c10 {
+ status = "okay";
+};
+
+&i2c11 {
+ status = "okay";
+};
+
+&i3c12 {
+ status = "okay";
+};
+
+&i3c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&i2c16 {
+ status = "okay";
+};
+
+&i2c17 {
+ status = "okay";
+};
+
+&i2c18 {
+ status = "okay";
+};
+
+&i2c19 {
+ status = "okay";
+};
+
+&i2c20 {
+ status = "okay";
+};
+
+&i2c21 {
+ status = "okay";
+};
+
+&i2c22 {
+ status = "okay";
+};
+
+&i2c23 {
+ status = "okay";
+};
+
+&i2c24 {
+ status = "okay";
+};
+
+&i2c25 {
+ status = "okay";
+};
+
+&i2c26 {
+ status = "okay";
+};
+
+&i2c27 {
+ status = "okay";
+};
+
+&i2c28 {
+ status = "okay";
+};
+
+&i2c29 {
+ status = "okay";
+};
+
+&i2c30 {
+ status = "okay";
+};
+
+&i2c31 {
+ status = "okay";
+};
+
+&i2c32 {
+ status = "okay";
+};
+
+&i2c33 {
+ status = "okay";
+};
+
+&i2c34 {
+ status = "okay";
+};
+
+&i2c35 {
+ status = "okay";
+};
+
+&i2c36 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&spi2 {
+ status = "okay";
+};
+
+&spi3 {
+ status = "okay";
+};
+
+&spi5 {
+ status = "okay";
+};
+
+&spi6 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&uart6 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
+
+&uart8 {
+ status = "okay";
+};
+
+&usb2_0 {
+ status = "okay";
+};
+
+&usb2_1 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/axiado/ax3005.dtsi b/arch/arm64/boot/dts/axiado/ax3005.dtsi
new file mode 100644
index 000000000000..f9ec68efc613
--- /dev/null
+++ b/arch/arm64/boot/dts/axiado/ax3005.dtsi
@@ -0,0 +1,842 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2026 Axiado Corporation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/memreserve/ 0x80002fa0 0x00000008;
+/ {
+ model = "Axiado AX3005";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ refclk: clock-125000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ pclk: clock-100000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ sysclk: clock-200000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ spiclk: clock-400000000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0x80002fa0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic500>;
+ ranges;
+
+ gic500: interrupt-controller@40400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x40400000 0x0 0x10000>,
+ <0x0 0x40500000 0x0 0xc0000>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ #redistributor-regions = <1>;
+ };
+
+ /* GPIO Controller banks 0 - 7 */
+ gpio0: gpio-controller@33000000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33000000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@33080000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33080000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@33100000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33100000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@33180000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33180000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@33200000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33200000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@33280000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33280000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@33300000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33300000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@33380000 {
+ compatible = "axiado,ax3005-gpio", "axiado,ax3000-gpio", "cdns,gpio-r1p02";
+ reg = <0x0 0x33380000 0x0 0x100>;
+ clocks = <&pclk>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@33000400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33000400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@33000800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33000800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@33080400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33080400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@33080800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33080800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@33100400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33100400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@33100800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33100800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@33200400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33200400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@33200800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33200800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@33280400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33280400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@33280800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33280800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c12: i3c@33300400 {
+ compatible = "axiado,ax3005-i3c", "cdns,i3c-master";
+ reg = <0x0 0x33300400 0x0 0x400>;
+ clock-names = "pclk", "sysclk";
+ clocks = <&pclk &sysclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i3c13: i3c@33300800 {
+ compatible = "axiado,ax3005-i3c", "cdns,i3c-master";
+ reg = <0x0 0x33300800 0x0 0x400>;
+ clock-names = "pclk", "sysclk";
+ clocks = <&pclk &sysclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-scl-hz = <100000>;
+ i3c-scl-hz = <400000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@33380400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33380400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@33380800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33380800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c16: i2c@33120400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33120400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c17: i2c@33021400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33021400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c18: i2c@33021800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33021800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c19: i2c@330c0400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c20: i2c@330c0800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c21: i2c@330c0c00 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x330c0c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c22: i2c@331a0800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x331a0800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c23: i2c@33302800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33302800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c24: i2c@33302c00 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33302c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c25: i2c@33303000 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33303000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c26: i2c@33382000 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33382000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c27: i2c@33382400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33382400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c28: i2c@33382800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33382800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c29: i2c@33382c00 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33382c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c30: i2c@33383000 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33383000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c31: i2c@33383400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33383400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c32: i2c@33383800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33383800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c33: i2c@33282400 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33282400 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c34: i2c@33282800 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33282800 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c35: i2c@33282c00 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33282c00 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c36: i2c@33283000 {
+ compatible = "axiado,ax3005-i2c", "cdns,i2c-r1p14";
+ reg = <0x0 0x33283000 0x0 0x400>;
+ clocks = <&pclk>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi0: spi@33010000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33010000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi1: spi@33090000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33090000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi2: spi@333c0000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x333c0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi3: spi@330e0000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x330e0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi5: spi@33390000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x33390000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ spi6: spi@333a0000 {
+ compatible = "axiado,ax3005-spi", "snps,dwc-ssi-1.01a";
+ reg = <0x0 0x333a0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&spiclk>;
+ num-cs = <1>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart0: serial@33020000 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33020000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart1: serial@330a0000 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x330a0000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart2: serial@33120000 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33120000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart3: serial@33020800 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33020800 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart4: serial@331a0400 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x331a0400 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart5: serial@33381d00 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381d00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart6: serial@33381e00 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381e00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart7: serial@33381f00 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x33381f00 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ uart8: serial@330c0000 {
+ compatible = "axiado,ax3005-uart", "cdns,uart-r1p12";
+ reg = <0x0 0x330c0000 0x0 0x100>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&refclk &pclk>;
+ status = "disabled";
+ };
+
+ usb2_0: usb@41000000 {
+ compatible = "axiado,ax3005-xhci", "generic-xhci";
+ reg = <0x0 0x41000000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb2_1: usb@41100000 {
+ compatible = "axiado,ax3005-xhci", "generic-xhci";
+ reg = <0x0 0x41100000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb3_0: usb@41400000 {
+ compatible = "axiado,ax3005-xhci", "generic-xhci";
+ reg = <0x0 0x41400000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ usb3_1: usb@41500000 {
+ compatible = "axiado,ax3005-xhci", "generic-xhci";
+ reg = <0x0 0x41500000 0x0 0x100000>;
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 2/8] dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant
From: sashiko-bot @ 2026-07-17 4:00 UTC (permalink / raw)
To: Swark Yang
Cc: linux-i3c, Alexandre Belloni, robh, Frank.Li, conor+dt,
devicetree
In-Reply-To: <20260716-upstream-axiado-ax3005-upstream-v3-2-c429095143ec@axiado.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The schema enforces a 3-item compatible string chain that unintentionally forces AX3005 devices to inherit an AX3000-specific driver quirk, contradicting the commit message.
--
--- Patch [2]: [PATCH v3 2/8] dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant ---
commit 53c67e7dc4609ee9e61f57a1d43c9c6ca04d123b
Author: Swark Yang <syang@axiado.com>
dt-bindings: gpio: cdns: add Axiado AX3005 GPIO variant
Add binding for the Axiado AX3005 GPIO controller. The commit message states
there are no known changes and it should fall back directly to the
cdns,gpio-r1p02 compatible string.
> diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> --- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml
> @@ -14,8 +14,11 @@ properties:
> oneOf:
> - const: cdns,gpio-r1p02
> - items:
> - - enum:
> - - axiado,ax3000-gpio
> + - const: axiado,ax3000-gpio
> + - const: cdns,gpio-r1p02
> + - items:
> + - const: axiado,ax3005-gpio
> + - const: axiado,ax3000-gpio
> - const: cdns,gpio-r1p02
[Severity: High]
Does forcing axiado,ax3000-gpio into the 3-item compatible string chain
unintentionally cause AX3005 devices to inherit AX3000-specific driver
quirks?
By requiring the axiado,ax3000-gpio compatible string in the fallback chain,
any AX3005 device tree must include it to pass schema validation. The
underlying driver will then match this intermediate string via
device_get_match_data() and apply ax3000_gpio_quirks, such as skipping
initialization of CDNS_GPIO_DIRECTION_MODE and CDNS_GPIO_OUTPUT_EN.
The commit message states the intent is to fall back to the cdns,gpio-r1p02
compatible. Should axiado,ax3005-gpio instead be added to an enum alongside
axiado,ax3000-gpio in a 2-item fallback chain, avoiding the intermediate
AX3000 string entirely?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260716-upstream-axiado-ax3005-upstream-v3-0-c429095143ec@axiado.com?part=2
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: qcom,snps-dwc3: Add property indicating presence of eUSB2 phy
From: Krishna Kurapati @ 2026-07-17 4:01 UTC (permalink / raw)
To: Peter Chen, Thinh Nguyen, Konrad Dybcio
Cc: Krzysztof Kozlowski, Dmitry Baryshkov, Greg Kroah-Hartman,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Wesley Cheng,
linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <almknp4Fx4EXqjm-@hu-petche-lv.qualcomm.com>
On 7/17/2026 9:12 AM, Peter Chen wrote:
> On 26-07-17 01:56:59, Thinh Nguyen wrote:
>> On Thu, Jul 16, 2026, Peter Chen wrote:
>>> On 26-07-17 00:06:37, Thinh Nguyen wrote:
>>>>>
>>>>> I have seen fewer platforms use "phy_type" at dts for arm64, dwc3
>>>>> core uses it only for special cases and the code was added for
>>>>> ten years ago. For the default situation, we may not need to
>>>>> change DWC3_GUSB2PHYCFG_EUSB2OPMODE value for UTMI+, Thinh, is it
>>>>> correct?
>>>>>
>>>>
>>>> The GUSB2PHYCFG.eUSB2OPMODE is only relevant for host mode and mainly
>>>> for electrical compliance. Usually by default, the CoreConsultant
>>>> setting should have this set correctly. So not explicitly setting it
>>>> should be functionally fine (IIRC).
>>>>
>>>> That said, this is separate from the GUSB2PHYCFG.PHYIF, which the core
>>>> uses dwc->hsphy_mode to indicate whether the UTMI interface is 8-bit or
>>>> 16-bit.
>>>>
>>>
>>> Why only rockchip uses this "phy_type" property, why other SoC vendors
>>> no this requirement for UTMI width setting?
>>>
>>
>> Not just rockchip, some tegra and hikey also use it. Some old qcom dts
>> files also have it for ulpi.
>
> Tegra and old qcom platforms use chipidea, hikey uses dwc3.
>
>>
>> It is typically set when the coreConsultant default differs from what
>> the platform needs, so the driver can override it with the correct
>> setting.
>>
>> My point is that changing "phy_type" definition is more involved than it
>> looks. I'm open to alternatives.
>>
>
> I know your concern that in case the eUSB2 PHY SoC wants to change UTMI
> width, it can't do that. Are there controller register know it connects
> eUSB2 PHY?
>
> For the place to put "eusb2" for phy type, I still think enum
> usb_phy_interface at: include/linux/usb/phy.h is the most suitable
> place, would you have any alternatives?
>
> Another solution is using generic PHY API phy_get_mode, set fixed "eusb2"
> mode at eUSB2 PHY driver, but it depends on PHY driver doesn't have
> different settings for device and host mode.
>
Konrad did suggest this on v3:
https://lore.kernel.org/all/3de365a0-4632-42ea-8a8a-5a4765945a76@oss.qualcomm.com/
This involves cleaning all drivers using these enums if we take that route.
Regards,
Krishna,
> Other solution is compare the generic PHY compatible string at dwc3 qcom
> glue layer, it depends on eUSB2 PHY compatible string always contains
> "eusb2-phy"
>
> I prefer the solution that extend enum usb_phy_interface for eUSB2 PHY,
> it uses existed kernel structure and device tree binding.
>
^ permalink raw reply
* [PATCH 1/2] dt-bindings: media: i2c: Add Samsung S5KJN5 image sensor
From: Wenmeng Liu @ 2026-07-17 4:08 UTC (permalink / raw)
To: Wenmeng Liu, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sakari Ailus
Cc: linux-media, devicetree, linux-kernel
In-Reply-To: <20260717-sk5jn5-v1-0-da610d7fd494@oss.qualcomm.com>
Add device tree bindings for the Samsung S5KJN5, a 50 MP GBRG 10-bit RAW
MIPI CSI-2 image sensor controlled over CCI.
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
.../bindings/media/i2c/samsung,s5kjn5.yaml | 109 +++++++++++++++++++++
MAINTAINERS | 7 ++
2 files changed, 116 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/i2c/samsung,s5kjn5.yaml b/Documentation/devicetree/bindings/media/i2c/samsung,s5kjn5.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..7fd9034f32efa93a753f27787b54022655010af8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/samsung,s5kjn5.yaml
@@ -0,0 +1,109 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/samsung,s5kjn5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5KJN5 Image Sensor
+
+description:
+ Samsung S5KJN5 is a 50MP GBRG 10-bit RAW MIPI CSI-2 image sensor.
+ The sensor is controlled over I2C. The full resolution pixel array is
+ 8192x6144, data output format is RAW10 transferred over 4-lane MIPI
+ D-PHY interface.
+
+maintainers:
+ - Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+
+allOf:
+ - $ref: /schemas/media/video-interface-devices.yaml#
+
+properties:
+ compatible:
+ const: samsung,s5kjn5
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: MCLK/XVCLK input clock.
+ maxItems: 1
+
+ reset-gpios:
+ description: Active low GPIO connected to RESET pad of the sensor.
+ maxItems: 1
+
+ vddio-supply:
+ description: Digital I/O voltage supply, 1.2 volts.
+
+ vddd-supply:
+ description: Digital core voltage supply, 1.0 volts.
+
+ vdda-supply:
+ description: Analogue voltage supply, 2.2 volts.
+
+ vdda2-supply:
+ description: Secondary analogue voltage supply, 1.8 volts.
+
+ afvdd-supply:
+ description: Autofocus actuator voltage supply, 2.8 volts.
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ required:
+ - link-frequencies
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - port
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@10 {
+ compatible = "samsung,s5kjn5";
+ reg = <0x10>;
+ clocks = <&camera_mclk 0>;
+ assigned-clocks = <&camera_mclk 0>;
+ assigned-clock-rates = <19200000>;
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ vddio-supply = <&vreg_1p2>;
+ vddd-supply = <&vreg_1p0>;
+ vdda-supply = <&vreg_2p2>;
+ vdda2-supply = <&vreg_1p8>;
+ afvdd-supply = <&vreg_2p8>;
+
+ port {
+ endpoint {
+ link-frequencies = /bits/ 64 <1248000000>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mipi_csi2_ep>;
+ };
+ };
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3af0fe95a92fc21c60819b892142380fad2ebd4e..02b564cb8839e7de82d95855f95d6af17139d0f3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24190,6 +24190,13 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/samsung,s5kjn1.yaml
F: drivers/media/i2c/s5kjn1.c
+SAMSUNG S5KJN5 CAMERA DRIVER
+M: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
+L: linux-media@vger.kernel.org
+S: Supported
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/samsung,s5kjn5.yaml
+
SAMSUNG S5P Security SubSystem (SSS) DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Vladimir Zapolskiy <vz@mleia.com>
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] media: i2c: Add Samsung S5KJN5 image sensor
From: Wenmeng Liu @ 2026-07-17 4:08 UTC (permalink / raw)
To: Wenmeng Liu, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sakari Ailus
Cc: linux-media, devicetree, linux-kernel
This series adds support for the Samsung S5KJN5, a 50 MP GBRG 10-bit RAW
MIPI CSI-2 image sensor.
This is implemented as a separate driver rather than extending the existing
s5kjn1 driver. Although both sensors belong to the same family, they are
different parts with different register maps, power supplies.
Combining support for both devices in a single driver would result in very
little shared code while introducing separate initialization and control
paths, so keeping them as independent drivers is cleaner.
Tested on the Qualcomm Hawi qrd board.
---
Wenmeng Liu (2):
dt-bindings: media: i2c: Add Samsung S5KJN5 image sensor
media: i2c: Add Samsung S5KJN5 image sensor driver
.../bindings/media/i2c/samsung,s5kjn5.yaml | 109 +
MAINTAINERS | 8 +
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/s5kjn5.c | 2835 ++++++++++++++++++++
5 files changed, 2964 insertions(+)
---
base-commit: b8809969e1d7a591e0f49dd464a5d04b3cf02ab1
change-id: 20260716-sk5jn5-be432bc99a98
Best regards,
--
Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 2/2] media: i2c: Add Samsung S5KJN5 image sensor driver
From: Wenmeng Liu @ 2026-07-17 4:08 UTC (permalink / raw)
To: Wenmeng Liu, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sakari Ailus
Cc: linux-media, devicetree, linux-kernel
In-Reply-To: <20260717-sk5jn5-v1-0-da610d7fd494@oss.qualcomm.com>
Add a V4L2 sub-device driver for the Samsung S5KJN5, a 50 MP GBRG 10-bit
RAW MIPI CSI-2 image sensor. The driver supports the 4096x3072 mode and
exposes the standard controls (exposure, gain, vblank/hblank, test
pattern).
Signed-off-by: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
---
MAINTAINERS | 1 +
drivers/media/i2c/Kconfig | 11 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/s5kjn5.c | 2835 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 2848 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 02b564cb8839e7de82d95855f95d6af17139d0f3..4c3b3aa905a124f8dded8b3d752cb56a3d32928a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24196,6 +24196,7 @@ L: linux-media@vger.kernel.org
S: Supported
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/samsung,s5kjn5.yaml
+F: drivers/media/i2c/s5kjn5.c
SAMSUNG S5P Security SubSystem (SSS) DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 7ffccba897ae5637bd0cb913e1e04f9c7d0c89f5..06b5dbc32cab328df8d10da04d91a708bff6fdda 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -824,6 +824,17 @@ config VIDEO_S5KJN1
To compile this driver as a module, choose M here: the
module will be called s5kjn1.
+config VIDEO_S5KJN5
+ tristate "Samsung S5KJN5 sensor support"
+ depends on GPIOLIB
+ select V4L2_CCI_I2C
+ help
+ This is a V4L2 sensor driver for Samsung S5KJN5 50MP GBRG
+ 10-bit RAW MIPI CSI-2 camera sensor.
+
+ To compile this driver as a module, choose M here: the
+ module will be called s5kjn5.
+
config VIDEO_T4KA3
tristate "Toshiba T4KA3 sensor support"
depends on ACPI || COMPILE_TEST
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index d04bd5724552e88fc2ad39f9bbaf9b4ce1763939..45019ce20a6c34c8139b8247b6904c3abb1a8fe7 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -133,6 +133,7 @@ obj-$(CONFIG_VIDEO_S5K3M5) += s5k3m5.o
obj-$(CONFIG_VIDEO_S5K5BAF) += s5k5baf.o
obj-$(CONFIG_VIDEO_S5K6A3) += s5k6a3.o
obj-$(CONFIG_VIDEO_S5KJN1) += s5kjn1.o
+obj-$(CONFIG_VIDEO_S5KJN5) += s5kjn5.o
obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o
obj-$(CONFIG_VIDEO_SAA6752HS) += saa6752hs.o
obj-$(CONFIG_VIDEO_SAA7110) += saa7110.o
diff --git a/drivers/media/i2c/s5kjn5.c b/drivers/media/i2c/s5kjn5.c
new file mode 100644
index 0000000000000000000000000000000000000000..294a4c3c5d2c5ff1b864b83b876a965ff70f8dfc
--- /dev/null
+++ b/drivers/media/i2c/s5kjn5.c
@@ -0,0 +1,2835 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung S5KJN5 50 MP GBRG 10-bit RAW MIPI CSI-2 sensor driver
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-cci.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+
+#define S5KJN5_REG_CHIP_ID CCI_REG16(0x0000)
+#define S5KJN5_CHIP_ID 0x38e5
+
+#define S5KJN5_REG_STREAMING CCI_REG8(0x0100)
+#define S5KJN5_STREAMING_ON 0x01
+#define S5KJN5_STREAMING_OFF 0x00
+
+#define S5KJN5_REG_FRAME_COUNT CCI_REG8(0x0005)
+#define S5KJN5_FRAME_COUNT_STANDBY 0xff
+#define S5KJN5_STANDBY_POLL_ITERS 20
+
+#define S5KJN5_REG_VTS CCI_REG16(0x0340)
+#define S5KJN5_VTS_MAX 65535
+
+#define S5KJN5_REG_EXPOSURE CCI_REG16(0x0202)
+
+/* Analogue gain: linear, reg = real * 32 */
+#define S5KJN5_REG_AGAIN CCI_REG16(0x0204)
+#define S5KJN5_AGAIN_MIN 0x0020 /* 1x */
+#define S5KJN5_AGAIN_MAX 0x0a00 /* 80x */
+#define S5KJN5_AGAIN_DEFAULT S5KJN5_AGAIN_MIN
+#define S5KJN5_AGAIN_STEP 1
+
+/* Digital gain: reg = real * 256 */
+#define S5KJN5_REG_DGAIN CCI_REG16(0x020e)
+#define S5KJN5_DGAIN_MIN 0x0100 /* 1x */
+#define S5KJN5_DGAIN_MAX 0x1000 /* 16x */
+#define S5KJN5_DGAIN_DEFAULT S5KJN5_DGAIN_MIN
+#define S5KJN5_DGAIN_STEP 1
+
+#define S5KJN5_REG_TEST_PATTERN CCI_REG16(0x0600)
+
+#define S5KJN5_EXPOSURE_MIN 4
+#define S5KJN5_EXPOSURE_DEFAULT 0x0100
+
+#define S5KJN5_XVCLK_RATE 19200000
+
+#define S5KJN5_DATA_LANES 4
+
+static const s64 s5kjn5_link_freqs[] = {
+ 1248000000LL,
+};
+
+static const char * const s5kjn5_supply_names[] = {
+ "vddio", /* Digital I/O power, 1.2 V */
+ "vddd", /* Digital core power, 1.0 V */
+ "vdda", /* Analog power, 2.2 V */
+ "vdda2", /* Analog power, 1.8 V */
+ "afvdd", /* Autofocus actuator power, 2.8 V */
+};
+
+#define S5KJN5_NUM_SUPPLIES ARRAY_SIZE(s5kjn5_supply_names)
+
+struct s5kjn5_mode {
+ u32 width;
+ u32 height;
+ u32 hts;
+ u32 vts_min;
+ u64 pixel_rate;
+ u32 exposure_margin;
+ const struct cci_reg_sequence *regs;
+ u32 num_regs;
+};
+
+/*
+ * Large blocks of contiguous registers, written as I2C bursts as
+ * directed by the vendor initialisation sequence.
+ */
+static const u8 s5kjn5_data_a614[] = {
+ 0x82, 0x80, 0x01, 0x00, 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0x83, 0xea,
+ 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87, 0x83, 0xa4, 0x87, 0x0d,
+ 0x03, 0xa4, 0xc7, 0x0d, 0x01, 0x46, 0xa6, 0x85, 0x22, 0x85, 0x97, 0x40,
+ 0x01, 0xfc, 0xe7, 0x80, 0xe0, 0x40, 0x97, 0xb0, 0xfe, 0xfb, 0xe7, 0x80,
+ 0x60, 0xdc, 0x05, 0x46, 0xa6, 0x85, 0x22, 0x85, 0x97, 0x40, 0x01, 0xfc,
+ 0xe7, 0x80, 0x80, 0x3f, 0x37, 0xa7, 0x02, 0x24, 0x93, 0x07, 0x87, 0x54,
+ 0x03, 0xc6, 0xc7, 0x02, 0x85, 0x46, 0x63, 0x01, 0xd6, 0x02, 0x83, 0xc6,
+ 0x07, 0x00, 0x09, 0x47, 0x63, 0x84, 0xe6, 0x08, 0xb7, 0xc7, 0x02, 0x24,
+ 0x83, 0xa7, 0x07, 0xb7, 0x05, 0x45, 0x82, 0x97, 0x17, 0x53, 0x02, 0xfc,
+ 0x67, 0x00, 0x83, 0xe6, 0x03, 0xd5, 0x47, 0x05, 0x05, 0xc9, 0x83, 0xd8,
+ 0x27, 0x05, 0xb7, 0xe6, 0x01, 0x24, 0x83, 0xd5, 0x66, 0x5f, 0x13, 0x07,
+ 0x87, 0x54, 0x81, 0x46, 0x25, 0x48, 0x03, 0x56, 0xe7, 0x02, 0x09, 0x07,
+ 0x63, 0xe0, 0xc5, 0x0e, 0x85, 0x06, 0xe3, 0x9a, 0x06, 0xff, 0x37, 0x07,
+ 0x00, 0x40, 0x3a, 0x95, 0x23, 0x10, 0x15, 0x01, 0x03, 0xd5, 0x67, 0x05,
+ 0x4d, 0xd5, 0x83, 0xd8, 0x27, 0x05, 0x37, 0xe7, 0x01, 0x24, 0x83, 0x55,
+ 0x67, 0x5f, 0xbe, 0x86, 0x01, 0x47, 0x25, 0x48, 0x03, 0xd6, 0xe6, 0x02,
+ 0x89, 0x06, 0x63, 0xee, 0xc5, 0x0a, 0x05, 0x07, 0xe3, 0x1a, 0x07, 0xff,
+ 0x37, 0x07, 0x00, 0x40, 0x3a, 0x95, 0x23, 0x10, 0x15, 0x01, 0x83, 0xc6,
+ 0x07, 0x00, 0x09, 0x47, 0xe3, 0x90, 0xe6, 0xf8, 0x03, 0xd5, 0x87, 0x02,
+ 0x1d, 0xc5, 0x83, 0xd8, 0x67, 0x02, 0x37, 0xf7, 0x01, 0x24, 0x83, 0x55,
+ 0xa7, 0x81, 0xbe, 0x86, 0x01, 0x47, 0x25, 0x48, 0x03, 0xd6, 0x26, 0x00,
+ 0x89, 0x06, 0x63, 0xe3, 0xc5, 0x06, 0x05, 0x07, 0xe3, 0x1a, 0x07, 0xff,
+ 0x37, 0x07, 0x00, 0x40, 0x3a, 0x95, 0x23, 0x10, 0x15, 0x01, 0x03, 0xd5,
+ 0xa7, 0x02, 0x39, 0xd1, 0x83, 0xd8, 0x67, 0x02, 0x37, 0xf7, 0x01, 0x24,
+ 0x83, 0x55, 0xa7, 0x81, 0xbe, 0x86, 0x01, 0x47, 0x25, 0x48, 0x03, 0xd6,
+ 0x26, 0x00, 0x89, 0x06, 0x63, 0xe4, 0xc5, 0x02, 0x05, 0x07, 0xe3, 0x1a,
+ 0x07, 0xff, 0xb7, 0x07, 0x00, 0x40, 0x3e, 0x95, 0xb7, 0xc7, 0x02, 0x24,
+ 0x83, 0xa7, 0x07, 0xb7, 0x23, 0x10, 0x15, 0x01, 0x05, 0x45, 0x82, 0x97,
+ 0x17, 0x53, 0x02, 0xfc, 0x67, 0x00, 0x03, 0xd8, 0x21, 0x07, 0x06, 0x07,
+ 0xba, 0x97, 0x83, 0xd8, 0x47, 0x00, 0xe1, 0xbf, 0x21, 0x07, 0x06, 0x07,
+ 0x3e, 0x97, 0x83, 0x58, 0x47, 0x00, 0x69, 0xbf, 0x13, 0x87, 0x06, 0x02,
+ 0x06, 0x07, 0x3e, 0x97, 0x83, 0x58, 0x07, 0x00, 0x39, 0xbf, 0x13, 0x07,
+ 0x07, 0x02, 0x06, 0x07, 0x3e, 0x97, 0x83, 0x58, 0x07, 0x00, 0x89, 0xb7,
+ 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0x83, 0xcf, 0x32, 0x84, 0xb7, 0xe7,
+ 0x01, 0x24, 0x03, 0x2b, 0x46, 0x00, 0x83, 0x2a, 0x46, 0x09, 0x03, 0x2a,
+ 0xc6, 0x04, 0x03, 0x48, 0x86, 0x00, 0x93, 0x87, 0x07, 0x87, 0x03, 0x46,
+ 0x86, 0x09, 0x03, 0x47, 0x04, 0x05, 0x83, 0xab, 0x07, 0x0e, 0x03, 0xac,
+ 0x47, 0x0e, 0x33, 0x18, 0x0b, 0x01, 0x33, 0x17, 0xea, 0x00, 0x33, 0x96,
+ 0xca, 0x00, 0x23, 0x22, 0x04, 0x01, 0x78, 0xc4, 0xaa, 0x84, 0x2e, 0x89,
+ 0x23, 0x2a, 0xc4, 0x08, 0xde, 0x85, 0x62, 0x85, 0x01, 0x46, 0xb6, 0x89,
+ 0x97, 0x40, 0x01, 0xfc, 0xe7, 0x80, 0x00, 0x25, 0xce, 0x86, 0x22, 0x86,
+ 0xca, 0x85, 0x26, 0x85, 0x97, 0xb0, 0xfd, 0xfb, 0xe7, 0x80, 0x00, 0xb0,
+ 0x62, 0x85, 0x05, 0x46, 0xde, 0x85, 0x97, 0x40, 0x01, 0xfc, 0xe7, 0x80,
+ 0x20, 0x23, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x23, 0x22,
+ 0x64, 0x01, 0x23, 0x2a, 0x54, 0x09, 0x23, 0x26, 0x44, 0x05, 0x01, 0x45,
+ 0x82, 0x97, 0x17, 0x53, 0x02, 0xfc, 0x67, 0x00, 0xe3, 0xc9, 0x01, 0x00,
+ 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0x43, 0xc8, 0x2a, 0x84, 0xef, 0xe0,
+ 0xef, 0xa9, 0xa1, 0x47, 0x63, 0x06, 0xf4, 0x00, 0x17, 0x53, 0x02, 0xfc,
+ 0x67, 0x00, 0x43, 0xc9, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x00, 0x0c,
+ 0x39, 0xc5, 0xb7, 0x37, 0x01, 0x24, 0x83, 0xc7, 0x27, 0x1a, 0xfd, 0xd3,
+ 0x37, 0x84, 0x00, 0x40, 0x83, 0x55, 0xe4, 0xf3, 0x0d, 0x45, 0x93, 0xe5,
+ 0x05, 0x24, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80, 0xa0, 0x0a, 0x83, 0x55,
+ 0x24, 0xf7, 0xb7, 0xa7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53, 0x03, 0xd7,
+ 0x47, 0xb6, 0xc2, 0x05, 0xc1, 0x81, 0x13, 0x77, 0xf7, 0xdb, 0x93, 0xf5,
+ 0xf5, 0xdb, 0x41, 0x45, 0x23, 0x92, 0xe7, 0xb6, 0x97, 0xd0, 0xff, 0xfb,
+ 0xe7, 0x80, 0x00, 0x08, 0x55, 0xb7, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80,
+ 0xa0, 0x03, 0x55, 0xd5, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x80, 0x7d,
+ 0x19, 0xc9, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0xd7, 0x03, 0xc7,
+ 0x87, 0x03, 0x83, 0xc7, 0x27, 0x06, 0x63, 0x06, 0xf7, 0x06, 0x97, 0x70,
+ 0xff, 0xfb, 0xe7, 0x80, 0xa0, 0x7b, 0x51, 0xd1, 0xb7, 0x97, 0x01, 0x24,
+ 0x93, 0x87, 0x07, 0xd7, 0x03, 0xc7, 0xc7, 0x01, 0x83, 0xc7, 0x27, 0x06,
+ 0xe3, 0x19, 0xf7, 0xf6, 0xb7, 0x27, 0x02, 0x24, 0x05, 0x64, 0x93, 0x87,
+ 0x07, 0x6b, 0xa2, 0x97, 0x03, 0xc7, 0xf7, 0x80, 0x85, 0x47, 0x63, 0x17,
+ 0xf7, 0x00, 0xb7, 0x37, 0x01, 0x24, 0x83, 0xc7, 0x57, 0xa5, 0xb1, 0xc3,
+ 0xb7, 0x87, 0x00, 0x40, 0x83, 0xd5, 0xe7, 0xf3, 0x0d, 0x45, 0x93, 0xe5,
+ 0x05, 0x01, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80, 0x20, 0x00, 0xb7, 0xa7,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0x53, 0x03, 0xd7, 0x47, 0xb6, 0x3d, 0x9b,
+ 0x23, 0x92, 0xe7, 0xb6, 0x1d, 0xb7, 0xb7, 0x27, 0x02, 0x24, 0x05, 0x64,
+ 0x93, 0x87, 0x07, 0x6b, 0xa2, 0x97, 0x03, 0xc7, 0xf7, 0x80, 0x91, 0x47,
+ 0xe3, 0x0d, 0xf7, 0xfa, 0xc1, 0xb7, 0xb7, 0x87, 0x00, 0x40, 0x83, 0xd5,
+ 0xe7, 0xf3, 0x0d, 0x45, 0x93, 0xe5, 0x05, 0x04, 0x97, 0xd0, 0xff, 0xfb,
+ 0xe7, 0x80, 0x00, 0xfc, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53,
+ 0xa2, 0x97, 0x03, 0xd7, 0x47, 0xb6, 0x13, 0x77, 0xf7, 0xfb, 0x23, 0x92,
+ 0xe7, 0xb6, 0xc5, 0xb5, 0x35, 0x71, 0x22, 0xcf, 0x26, 0xcd, 0x73, 0x24,
+ 0x20, 0x34, 0xf3, 0x24, 0x10, 0x34, 0x73, 0x60, 0x04, 0x30, 0x06, 0xcb,
+ 0x16, 0xc9, 0x1a, 0xc7, 0x1e, 0xc5, 0x2a, 0xc3, 0x2e, 0xc1, 0xb2, 0xde,
+ 0xb6, 0xdc, 0xba, 0xda, 0xbe, 0xd8, 0xc2, 0xd6, 0xc6, 0xd4, 0xf2, 0xd2,
+ 0xf6, 0xd0, 0xfa, 0xce, 0xfe, 0xcc, 0x82, 0xe2, 0x86, 0xe0, 0x0a, 0xfe,
+ 0x0e, 0xfc, 0x12, 0xfa, 0x16, 0xf8, 0x1a, 0xf6, 0x1e, 0xf4, 0x2a, 0xf2,
+ 0x2e, 0xf0, 0x32, 0xee, 0x36, 0xec, 0x3a, 0xea, 0x3e, 0xe8, 0x42, 0xe6,
+ 0x46, 0xe4, 0x72, 0xe2, 0x76, 0xe0, 0x27, 0x2e, 0xe1, 0xff, 0x27, 0x2c,
+ 0xf1, 0xff, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x60, 0xf3, 0x19, 0xc5,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0xef, 0x63, 0x1c, 0x05, 0x12,
+ 0x93, 0x05, 0x00, 0x24, 0x41, 0x45, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80,
+ 0x60, 0xf9, 0x81, 0x45, 0x93, 0x77, 0x15, 0x00, 0x85, 0xc7, 0x37, 0xd7,
+ 0x01, 0x24, 0xb7, 0xa7, 0x01, 0x24, 0x13, 0x07, 0x07, 0xc4, 0x93, 0x87,
+ 0x07, 0x53, 0x03, 0x56, 0x47, 0x07, 0x83, 0xd6, 0xa7, 0xb6, 0x05, 0x06,
+ 0x93, 0xe6, 0x16, 0x00, 0x23, 0x1a, 0xc7, 0x06, 0x23, 0x95, 0xd7, 0xb6,
+ 0x93, 0x77, 0x25, 0x00, 0x85, 0xc7, 0x37, 0xd7, 0x01, 0x24, 0xb7, 0xa7,
+ 0x01, 0x24, 0x13, 0x07, 0x07, 0xc4, 0x93, 0x87, 0x07, 0x53, 0x03, 0x56,
+ 0xc7, 0x0c, 0x83, 0xd6, 0xa7, 0xb6, 0x05, 0x06, 0x93, 0xe6, 0x26, 0x00,
+ 0x23, 0x16, 0xc7, 0x0c, 0x23, 0x95, 0xd7, 0xb6, 0x93, 0x77, 0x05, 0x20,
+ 0x13, 0x75, 0x05, 0x04, 0xc5, 0xc3, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87,
+ 0x07, 0xc4, 0x03, 0xd7, 0x67, 0x08, 0x05, 0x07, 0x23, 0x93, 0xe7, 0x08,
+ 0xd1, 0xc5, 0x37, 0xa7, 0x01, 0x24, 0x13, 0x07, 0x07, 0x53, 0x83, 0x56,
+ 0xa7, 0xb6, 0x93, 0xe6, 0x06, 0x20, 0x23, 0x15, 0xd7, 0xb6, 0x11, 0xc9,
+ 0x03, 0xd6, 0xa7, 0x08, 0x05, 0x06, 0x23, 0x95, 0xc7, 0x08, 0x93, 0xe6,
+ 0x06, 0x04, 0x23, 0x15, 0xd7, 0xb6, 0xda, 0x40, 0xca, 0x42, 0x3a, 0x43,
+ 0xaa, 0x43, 0x1a, 0x45, 0x8a, 0x45, 0x76, 0x56, 0xe6, 0x56, 0x56, 0x57,
+ 0xc6, 0x57, 0x36, 0x58, 0xa6, 0x58, 0x16, 0x5e, 0x86, 0x5e, 0x76, 0x4f,
+ 0xe6, 0x4f, 0x16, 0x60, 0x86, 0x60, 0x72, 0x71, 0xe2, 0x71, 0x52, 0x72,
+ 0xc2, 0x72, 0x32, 0x73, 0xa2, 0x73, 0x12, 0x75, 0x82, 0x75, 0x72, 0x66,
+ 0xe2, 0x66, 0x52, 0x67, 0xc2, 0x67, 0x32, 0x68, 0xa2, 0x68, 0x12, 0x6e,
+ 0x82, 0x6e, 0x07, 0x2f, 0xc1, 0xff, 0x87, 0x2f, 0x81, 0xff, 0x73, 0x70,
+ 0x04, 0x30, 0x73, 0x90, 0x14, 0x34, 0x73, 0x10, 0x24, 0x34, 0x7a, 0x44,
+ 0xea, 0x44, 0x0d, 0x61, 0x73, 0x00, 0x20, 0x30, 0x59, 0xdd, 0xb7, 0xd7,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4, 0x03, 0xd7, 0xa7, 0x08, 0x05, 0x07,
+ 0x23, 0x95, 0xe7, 0x08, 0xc9, 0xd5, 0x37, 0xa7, 0x01, 0x24, 0x13, 0x07,
+ 0x07, 0x53, 0x83, 0x56, 0xa7, 0xb6, 0x95, 0xbf, 0xb7, 0xa7, 0x01, 0x24,
+ 0x83, 0xd5, 0x87, 0x09, 0x41, 0x45, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80,
+ 0xe0, 0xe5, 0x85, 0x45, 0xe1, 0xb5, 0x01, 0x00, 0x82, 0x80, 0x01, 0x00,
+ 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0x83, 0x97, 0x37, 0xe4, 0x01, 0x24,
+ 0x13, 0x04, 0x04, 0x4c, 0x83, 0x44, 0xe4, 0x0a, 0x85, 0x47, 0x23, 0x07,
+ 0xf4, 0x0a, 0x97, 0xa0, 0xfd, 0xfb, 0xe7, 0x80, 0x20, 0xe3, 0x23, 0x07,
+ 0x94, 0x0a, 0x17, 0x53, 0x02, 0xfc, 0x67, 0x00, 0x63, 0x97, 0x01, 0x00,
+ 0xb7, 0xa7, 0x02, 0x24, 0x83, 0xc7, 0x07, 0x5a, 0x05, 0x47, 0x63, 0x83,
+ 0xe7, 0x00, 0x82, 0x80, 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0xe3, 0x91,
+ 0x37, 0x94, 0x01, 0x24, 0x13, 0x04, 0x04, 0x53, 0x03, 0x47, 0x04, 0x1b,
+ 0x41, 0x11, 0x63, 0x07, 0xf7, 0x00, 0x41, 0x01, 0x17, 0x53, 0x02, 0xfc,
+ 0x67, 0x00, 0x63, 0x93, 0x89, 0x47, 0xe3, 0x1a, 0xf5, 0xfe, 0x83, 0x47,
+ 0x34, 0x41, 0xad, 0xc3, 0x83, 0xa9, 0x05, 0x00, 0x2e, 0xc6, 0x97, 0xc0,
+ 0x01, 0xfc, 0xe7, 0x80, 0x20, 0xb8, 0xaa, 0x84, 0x97, 0x80, 0x01, 0xfc,
+ 0xe7, 0x80, 0x80, 0xc7, 0xb2, 0x45, 0x2a, 0x89, 0x9c, 0x41, 0x63, 0xf3,
+ 0x97, 0x00, 0xa6, 0x87, 0x88, 0x51, 0x9c, 0xc1, 0x2e, 0xc6, 0x4a, 0x95,
+ 0x97, 0xb0, 0x00, 0xfc, 0xe7, 0x80, 0x00, 0xc5, 0xb2, 0x45, 0xaa, 0x84,
+ 0xe8, 0xc9, 0x33, 0x85, 0x29, 0x01, 0x97, 0xb0, 0x00, 0xfc, 0xe7, 0x80,
+ 0xe0, 0xc3, 0x85, 0x67, 0x3e, 0x94, 0x83, 0x27, 0xc4, 0x83, 0x26, 0x95,
+ 0xb2, 0x45, 0x63, 0xf3, 0xa7, 0x00, 0xaa, 0x87, 0x23, 0x22, 0xf4, 0x98,
+ 0xe8, 0xc5, 0x71, 0xb7, 0x01, 0x45, 0x2e, 0xc6, 0x97, 0xb0, 0x01, 0xfc,
+ 0xe7, 0x80, 0x80, 0x35, 0xb2, 0x45, 0xaa, 0x89, 0x51, 0xbf, 0x01, 0x00,
+ 0x17, 0x53, 0x02, 0xfc, 0xe7, 0x02, 0x43, 0x89, 0x2a, 0x84, 0xef, 0xe0,
+ 0xaf, 0xfc, 0x01, 0xe8, 0xb7, 0xd7, 0x01, 0x24, 0x03, 0xa7, 0x87, 0xc1,
+ 0x91, 0x47, 0x63, 0x06, 0xf7, 0x00, 0x17, 0x53, 0x02, 0xfc, 0x67, 0x00,
+ 0xa3, 0x89, 0xb7, 0xd7, 0x01, 0x24, 0x83, 0xc7, 0x07, 0xfa, 0xe5, 0xdb,
+ 0xb7, 0x47, 0x01, 0x24, 0x83, 0xc7, 0x27, 0xc4, 0xfd, 0xf3, 0x97, 0xe0,
+ 0x00, 0xfc, 0xe7, 0x80, 0xa0, 0x97, 0xb7, 0x87, 0x02, 0x24, 0x05, 0x47,
+ 0xa3, 0x80, 0xe7, 0x4e, 0xc9, 0xbf, 0x01, 0x00, 0x17, 0x53, 0x02, 0xfc,
+ 0xe7, 0x02, 0x43, 0x84, 0x37, 0x84, 0x02, 0x24, 0x13, 0x04, 0xc4, 0x49,
+ 0x83, 0x47, 0x54, 0x04, 0x99, 0xe7, 0xef, 0xe0, 0x7f, 0x82, 0x17, 0x53,
+ 0x02, 0xfc, 0x67, 0x00, 0xe3, 0x84, 0x97, 0xe0, 0x00, 0xfc, 0xe7, 0x80,
+ 0x20, 0xaf, 0xa3, 0x02, 0x04, 0x04, 0xef, 0xe0, 0xff, 0x80, 0x17, 0x53,
+ 0x02, 0xfc, 0x67, 0x00, 0x63, 0x83, 0x01, 0x00, 0x17, 0x53, 0x02, 0xfc,
+ 0xe7, 0x02, 0x83, 0x80, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87,
+ 0x03, 0xa9, 0x87, 0x0e, 0x83, 0xa4, 0xc7, 0x0e, 0x01, 0x46, 0xca, 0x85,
+ 0x2a, 0x84, 0x26, 0x85, 0x97, 0x40, 0x01, 0xfc, 0xe7, 0x80, 0xc0, 0xd6,
+ 0x22, 0x85, 0x97, 0xa0, 0xff, 0xfb, 0xe7, 0x80, 0x60, 0x3e, 0x05, 0x46,
+ 0xca, 0x85, 0x26, 0x85, 0x97, 0x40, 0x01, 0xfc, 0xe7, 0x80, 0x40, 0xd5,
+ 0x85, 0x47, 0x63, 0x0f, 0xf4, 0x00, 0x91, 0x47, 0x63, 0x0c, 0xf4, 0x00,
+ 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x09, 0x45, 0x82, 0x97,
+ 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0x43, 0x7d, 0x97, 0x70, 0xff, 0xfb,
+ 0xe7, 0x80, 0x00, 0xc0, 0x75, 0xf1, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80,
+ 0x60, 0xbc, 0x69, 0xdd, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x40, 0x36,
+ 0x19, 0xc9, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0xd7, 0x03, 0xc7,
+ 0x87, 0x03, 0x83, 0xc7, 0x27, 0x06, 0x63, 0x06, 0xf7, 0x06, 0x97, 0x70,
+ 0xff, 0xfb, 0xe7, 0x80, 0x60, 0x34, 0x4d, 0xd9, 0xb7, 0x97, 0x01, 0x24,
+ 0x93, 0x87, 0x07, 0xd7, 0x03, 0xc7, 0xc7, 0x01, 0x83, 0xc7, 0x27, 0x06,
+ 0xe3, 0x10, 0xf7, 0xfa, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x47, 0xb7,
+ 0xb7, 0x06, 0x00, 0x40, 0x13, 0x86, 0x46, 0x06, 0x89, 0x65, 0x3e, 0x96,
+ 0x13, 0x87, 0x06, 0x1f, 0x93, 0x85, 0xf5, 0xf1, 0x23, 0x10, 0xb6, 0x00,
+ 0x3e, 0x97, 0x7d, 0x56, 0x23, 0x10, 0xc7, 0x00, 0x37, 0xd6, 0x01, 0x24,
+ 0x13, 0x06, 0x06, 0xe7, 0x03, 0x57, 0xc6, 0x05, 0x03, 0x56, 0x66, 0x06,
+ 0x93, 0x86, 0x86, 0x1d, 0x32, 0x97, 0x42, 0x07, 0xb6, 0x97, 0x41, 0x83,
+ 0x23, 0x90, 0xe7, 0x00, 0x91, 0xbf, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7,
+ 0x47, 0xb7, 0xb7, 0x06, 0x00, 0x40, 0x13, 0x86, 0x46, 0x06, 0x89, 0x65,
+ 0x3e, 0x96, 0x13, 0x87, 0x06, 0x1f, 0x93, 0x85, 0xf5, 0xf1, 0x23, 0x10,
+ 0xb6, 0x00, 0x3e, 0x97, 0x7d, 0x56, 0x23, 0x10, 0xc7, 0x00, 0x37, 0xd6,
+ 0x01, 0x24, 0x13, 0x06, 0x06, 0xe7, 0x03, 0x57, 0x06, 0x06, 0x93, 0x86,
+ 0xa6, 0x1d, 0x03, 0x56, 0x66, 0x06, 0x5d, 0xbf, 0x17, 0x43, 0x02, 0xfc,
+ 0xe7, 0x02, 0x03, 0x6d, 0xb7, 0xd7, 0x00, 0x24, 0x83, 0xc7, 0x47, 0x6d,
+ 0x85, 0x44, 0x63, 0x80, 0x97, 0x14, 0xb7, 0xe7, 0x00, 0x24, 0x03, 0xc4,
+ 0xc7, 0x84, 0xb7, 0xa7, 0x01, 0x24, 0x83, 0xc7, 0x67, 0x92, 0x33, 0x34,
+ 0x80, 0x00, 0x33, 0x04, 0x80, 0x40, 0x79, 0x98, 0x13, 0x04, 0x64, 0x02,
+ 0xed, 0xe7, 0xb7, 0x67, 0x00, 0x24, 0x93, 0x87, 0x07, 0x33, 0x03, 0xd7,
+ 0xe7, 0x5b, 0x19, 0xc7, 0x13, 0x47, 0xf7, 0xff, 0x61, 0x8f, 0x13, 0x14,
+ 0x07, 0x01, 0x41, 0x80, 0x83, 0xd7, 0x07, 0x5c, 0x0d, 0x45, 0x5d, 0x8c,
+ 0x42, 0x04, 0x41, 0x80, 0xa2, 0x85, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80,
+ 0xa0, 0xbb, 0x93, 0x15, 0x05, 0x01, 0xc1, 0x81, 0xaa, 0x84, 0x63, 0x09,
+ 0xb4, 0x00, 0x05, 0x65, 0xa1, 0x8d, 0x2d, 0x05, 0x97, 0xa0, 0xff, 0xfb,
+ 0xe7, 0x80, 0x80, 0x46, 0x13, 0x95, 0x04, 0x01, 0x93, 0xf7, 0x14, 0x00,
+ 0x41, 0x81, 0x91, 0xcb, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0x47, 0x07, 0x05, 0x07, 0x23, 0x9a, 0xe7, 0x06, 0x93, 0x77,
+ 0x25, 0x00, 0x91, 0xcb, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0xc7, 0x0c, 0x05, 0x07, 0x23, 0x96, 0xe7, 0x0c, 0x93, 0x77,
+ 0x45, 0x00, 0x91, 0xcb, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0xe7, 0x0c, 0x05, 0x07, 0x23, 0x97, 0xe7, 0x0c, 0x93, 0x77,
+ 0x05, 0x02, 0x91, 0xcb, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0x07, 0x0f, 0x05, 0x07, 0x23, 0x98, 0xe7, 0x0e, 0x93, 0x77,
+ 0x05, 0x20, 0x91, 0xcb, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0x67, 0x08, 0x05, 0x07, 0x23, 0x93, 0xe7, 0x08, 0x13, 0x75,
+ 0x05, 0x04, 0x11, 0xc9, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4,
+ 0x03, 0xd7, 0xa7, 0x08, 0x05, 0x07, 0x23, 0x95, 0xe7, 0x08, 0x17, 0x43,
+ 0x02, 0xfc, 0x67, 0x00, 0xe3, 0x5d, 0xb7, 0xd7, 0x01, 0x24, 0x83, 0xd7,
+ 0xa7, 0xe7, 0x81, 0xdb, 0x97, 0x60, 0xfe, 0xfb, 0xe7, 0x80, 0x80, 0x68,
+ 0x63, 0x11, 0x95, 0x06, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0xd7,
+ 0x03, 0xc7, 0xc7, 0x01, 0x83, 0xc7, 0x27, 0x06, 0x63, 0x07, 0xf7, 0x04,
+ 0x13, 0x64, 0x04, 0x24, 0x42, 0x04, 0x41, 0x80, 0x11, 0xa0, 0x01, 0x44,
+ 0xb7, 0x67, 0x00, 0x24, 0x93, 0x87, 0x07, 0x33, 0x03, 0xc7, 0x27, 0x3b,
+ 0xe3, 0x0f, 0x07, 0xec, 0x37, 0xa7, 0x01, 0x24, 0x03, 0x47, 0x67, 0x92,
+ 0xe3, 0x09, 0x07, 0xec, 0x37, 0xd7, 0x01, 0x24, 0x03, 0x57, 0xa7, 0xe7,
+ 0xe3, 0x03, 0x07, 0xec, 0x37, 0x97, 0x01, 0x24, 0x03, 0x47, 0x17, 0x00,
+ 0xe3, 0x0d, 0x07, 0xea, 0x13, 0x74, 0xf4, 0xdf, 0x42, 0x04, 0x41, 0x80,
+ 0x7d, 0xb5, 0x97, 0x60, 0xfe, 0xfb, 0xe7, 0x80, 0xe0, 0x61, 0x85, 0x47,
+ 0xe3, 0x1c, 0xf5, 0xfa, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0xd7,
+ 0x03, 0xc7, 0xc7, 0x01, 0x83, 0xc7, 0x27, 0x06, 0xe3, 0x12, 0xf7, 0xfa,
+ 0x13, 0x64, 0x04, 0x20, 0x42, 0x04, 0x41, 0x80, 0x61, 0xbf, 0x01, 0x00,
+ 0x71, 0x71, 0x22, 0xd7, 0x26, 0xd5, 0x73, 0x24, 0x20, 0x34, 0xf3, 0x24,
+ 0x10, 0x34, 0x73, 0x60, 0x04, 0x30, 0x2e, 0xc5, 0xa5, 0x65, 0xbe, 0xdc,
+ 0x06, 0xd3, 0x16, 0xd1, 0x1a, 0xcf, 0x1e, 0xcd, 0x22, 0xcb, 0x2a, 0xc7,
+ 0x32, 0xc3, 0x36, 0xc1, 0xba, 0xde, 0xc2, 0xda, 0xc6, 0xd8, 0xf2, 0xd0,
+ 0xf6, 0xce, 0xfa, 0xcc, 0xfe, 0xca, 0x82, 0xe2, 0x86, 0xe0, 0x0a, 0xfe,
+ 0x0e, 0xfc, 0x12, 0xfa, 0x16, 0xf8, 0x1a, 0xf6, 0x1e, 0xf4, 0x2a, 0xf2,
+ 0x2e, 0xf0, 0x32, 0xee, 0x26, 0xc9, 0xca, 0xd6, 0xce, 0xd4, 0xd2, 0xd2,
+ 0x93, 0x85, 0x05, 0x40, 0x05, 0x45, 0x36, 0xec, 0x3a, 0xea, 0x3e, 0xe8,
+ 0x42, 0xe6, 0x46, 0xe4, 0x72, 0xe2, 0x76, 0xe0, 0x27, 0x2e, 0xe1, 0xff,
+ 0x27, 0x2c, 0xf1, 0xff, 0x97, 0xd0, 0xff, 0xfb, 0xe7, 0x80, 0x40, 0x97,
+ 0xa1, 0x67, 0xe9, 0x8f, 0x2a, 0x84, 0x63, 0x94, 0x07, 0x18, 0xb7, 0x64,
+ 0x01, 0x24, 0x93, 0x84, 0x04, 0x40, 0x85, 0x67, 0xe1, 0x8f, 0xcd, 0xcf,
+ 0x37, 0xd7, 0x01, 0x24, 0x37, 0x89, 0x02, 0x24, 0x13, 0x07, 0x07, 0xc4,
+ 0x13, 0x09, 0xc9, 0x49, 0x83, 0x56, 0x67, 0x0e, 0x83, 0x27, 0x09, 0x05,
+ 0x85, 0x06, 0x85, 0x07, 0x23, 0x28, 0xf9, 0x04, 0x23, 0x13, 0xd7, 0x0e,
+ 0x85, 0x8b, 0x63, 0x9f, 0x07, 0x1a, 0x85, 0x47, 0xa3, 0x0a, 0xf9, 0x04,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x00, 0xff, 0x19, 0xc5, 0x03, 0x57,
+ 0x49, 0x05, 0x93, 0x07, 0x10, 0x10, 0x63, 0x06, 0xf7, 0x24, 0xdc, 0x50,
+ 0x09, 0x45, 0x82, 0x97, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0x85,
+ 0x11, 0xc5, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x20, 0x88, 0x55, 0xc5,
+ 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80, 0x40, 0x5a, 0xb7, 0x87, 0x00, 0x24,
+ 0x83, 0xc7, 0x07, 0x8c, 0xaa, 0x89, 0x63, 0x92, 0x07, 0x1c, 0xb7, 0xd7,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0xe7, 0xbc, 0x5f, 0x63, 0x9a, 0x07, 0x16,
+ 0x37, 0x99, 0x01, 0x24, 0x13, 0x09, 0x09, 0x53, 0xb7, 0x27, 0x00, 0x24,
+ 0x83, 0xc7, 0x77, 0x52, 0x63, 0x96, 0x07, 0x1e, 0x03, 0x45, 0xc9, 0x18,
+ 0x63, 0x1d, 0x05, 0x1c, 0xdc, 0x50, 0x0d, 0x45, 0x82, 0x97, 0x4e, 0x85,
+ 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80, 0x00, 0x5a, 0x85, 0x67, 0x3e, 0x99,
+ 0x23, 0x20, 0xa9, 0xa2, 0x13, 0x74, 0x04, 0x40, 0x21, 0xc4, 0xb7, 0xd7,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0xc4, 0x37, 0xa7, 0x01, 0x24, 0x83, 0xd6,
+ 0x67, 0x0e, 0x13, 0x07, 0x07, 0x53, 0x03, 0x47, 0x17, 0x9b, 0x85, 0x06,
+ 0x37, 0x84, 0x02, 0x24, 0x13, 0x04, 0xc4, 0x49, 0x13, 0x37, 0x17, 0x00,
+ 0x23, 0x93, 0xd7, 0x0e, 0x23, 0x0a, 0xe4, 0x04, 0x97, 0x70, 0xff, 0xfb,
+ 0xe7, 0x80, 0x40, 0xf3, 0x63, 0x06, 0x05, 0x10, 0x03, 0x57, 0x44, 0x05,
+ 0x93, 0x07, 0x10, 0x10, 0x63, 0x00, 0xf7, 0x10, 0xdc, 0x50, 0x1d, 0x45,
+ 0x82, 0x97, 0x9a, 0x50, 0x8a, 0x52, 0x7a, 0x43, 0xea, 0x43, 0x5a, 0x44,
+ 0xca, 0x44, 0x3a, 0x45, 0xaa, 0x45, 0x1a, 0x46, 0x8a, 0x46, 0x76, 0x57,
+ 0xe6, 0x57, 0x56, 0x58, 0xc6, 0x58, 0x36, 0x59, 0xa6, 0x59, 0x16, 0x5a,
+ 0x06, 0x5e, 0xf6, 0x4e, 0x66, 0x4f, 0xd6, 0x4f, 0x16, 0x60, 0x86, 0x60,
+ 0x72, 0x71, 0xe2, 0x71, 0x52, 0x72, 0xc2, 0x72, 0x32, 0x73, 0xa2, 0x73,
+ 0x12, 0x75, 0x82, 0x75, 0x72, 0x66, 0xe2, 0x66, 0x52, 0x67, 0xc2, 0x67,
+ 0x32, 0x68, 0xa2, 0x68, 0x12, 0x6e, 0x82, 0x6e, 0x07, 0x2f, 0xc1, 0xff,
+ 0x87, 0x2f, 0x81, 0xff, 0x73, 0x70, 0x04, 0x30, 0x73, 0x90, 0x14, 0x34,
+ 0x73, 0x10, 0x24, 0x34, 0x3a, 0x54, 0xaa, 0x54, 0x4d, 0x61, 0x73, 0x00,
+ 0x20, 0x30, 0x37, 0xd9, 0x01, 0x24, 0x13, 0x09, 0x09, 0xc4, 0x83, 0x57,
+ 0x49, 0x0e, 0xb7, 0x64, 0x01, 0x24, 0x93, 0x84, 0x04, 0x40, 0xd8, 0x50,
+ 0x85, 0x07, 0x01, 0x45, 0x23, 0x12, 0xf9, 0x0e, 0x02, 0x97, 0x97, 0x60,
+ 0xff, 0xfb, 0xe7, 0x80, 0x20, 0x71, 0x25, 0xe5, 0xb7, 0x29, 0x00, 0x24,
+ 0x37, 0x99, 0x01, 0x24, 0x93, 0x89, 0x09, 0x33, 0x13, 0x09, 0x09, 0x53,
+ 0x05, 0x6a, 0x83, 0xc7, 0x79, 0x1f, 0x4a, 0x9a, 0x23, 0x20, 0x0a, 0xa2,
+ 0xb9, 0xef, 0x03, 0x45, 0xc9, 0x18, 0x2d, 0xe5, 0x83, 0xc7, 0x09, 0x20,
+ 0x89, 0xc7, 0x03, 0x27, 0x4a, 0xb3, 0x63, 0x0a, 0xf7, 0x00, 0x97, 0xe0,
+ 0x00, 0xfc, 0xe7, 0x80, 0xe0, 0xd2, 0xdc, 0x50, 0x05, 0x45, 0x82, 0x97,
+ 0x29, 0xbd, 0x01, 0xa0, 0x85, 0x47, 0x23, 0x0a, 0x09, 0x04, 0xa3, 0x0a,
+ 0x09, 0x04, 0x23, 0x28, 0xf9, 0x04, 0x3d, 0xbd, 0x7d, 0x55, 0x97, 0x70,
+ 0x01, 0xfc, 0xe7, 0x80, 0xa0, 0x04, 0x59, 0xb5, 0xef, 0xe0, 0x5f, 0xd9,
+ 0x01, 0xb7, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80, 0x20, 0x6d, 0x49, 0xf9,
+ 0x83, 0x57, 0x49, 0x0e, 0x85, 0x8b, 0xc9, 0xf7, 0xcd, 0xbd, 0x97, 0x70,
+ 0x01, 0xfc, 0xe7, 0x80, 0x20, 0x03, 0x23, 0x11, 0xa9, 0x4e, 0x03, 0x45,
+ 0xc9, 0x18, 0x49, 0xdd, 0x97, 0xc0, 0xff, 0xfb, 0xe7, 0x80, 0x40, 0xb4,
+ 0x41, 0xbf, 0x97, 0x70, 0x01, 0xfc, 0xe7, 0x80, 0x60, 0x01, 0x37, 0x99,
+ 0x01, 0x24, 0x13, 0x09, 0x09, 0x53, 0x8d, 0x67, 0xca, 0x97, 0x03, 0xc7,
+ 0xd7, 0x6f, 0x23, 0x2e, 0xa9, 0x4e, 0x85, 0x47, 0x63, 0x06, 0xf7, 0x00,
+ 0x83, 0x27, 0x09, 0x4f, 0xe3, 0x77, 0xf5, 0xea, 0x97, 0x60, 0x00, 0xfc,
+ 0xe7, 0x80, 0x80, 0xfc, 0x97, 0x70, 0x01, 0xfc, 0xe7, 0x80, 0x40, 0xfe,
+ 0x23, 0x20, 0xa9, 0x50, 0x21, 0xbd, 0x97, 0xc0, 0xff, 0xfb, 0xe7, 0x80,
+ 0xa0, 0xb2, 0x0d, 0xb5, 0x97, 0x70, 0x01, 0xfc, 0xe7, 0x80, 0xc0, 0xfc,
+ 0x23, 0x12, 0xa9, 0x4e, 0x31, 0xb5, 0xef, 0xe0, 0x7f, 0xd0, 0x55, 0xbb,
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0xc3, 0x1e, 0x2a, 0x84, 0xef, 0xd0,
+ 0xbf, 0xa7, 0x89, 0x47, 0x63, 0x06, 0xf4, 0x00, 0x17, 0x43, 0x02, 0xfc,
+ 0x67, 0x00, 0xc3, 0x1f, 0xb7, 0xe7, 0x00, 0x24, 0x03, 0xd7, 0xc7, 0xc8,
+ 0x85, 0x64, 0x93, 0x87, 0xf4, 0xb3, 0xe3, 0x15, 0xf7, 0xfe, 0x37, 0xa9,
+ 0x02, 0x24, 0x13, 0x09, 0x89, 0x54, 0x83, 0x47, 0x19, 0x0c, 0xe9, 0xff,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x00, 0xe3, 0x61, 0xf9, 0x97, 0x70,
+ 0xff, 0xfb, 0xe7, 0x80, 0xa0, 0xe3, 0x79, 0xf1, 0x37, 0x25, 0x02, 0x24,
+ 0x13, 0x05, 0x05, 0xed, 0x97, 0x00, 0xff, 0xfb, 0xe7, 0x80, 0x80, 0xfa,
+ 0xb7, 0x97, 0x01, 0x24, 0x37, 0x67, 0x01, 0x24, 0x03, 0x27, 0x07, 0x40,
+ 0x93, 0x87, 0x07, 0x53, 0xa6, 0x97, 0x85, 0x44, 0x1d, 0x45, 0x23, 0x8d,
+ 0x97, 0xce, 0x02, 0x97, 0xa3, 0x00, 0x99, 0x0c, 0x97, 0x80, 0x01, 0xfc,
+ 0xe7, 0x80, 0x00, 0x83, 0x51, 0xf5, 0xb7, 0x27, 0x01, 0x24, 0x23, 0x80,
+ 0x87, 0x54, 0x97, 0xb0, 0xfe, 0xfb, 0xe7, 0x80, 0x60, 0x02, 0x23, 0x01,
+ 0x99, 0x0c, 0x9d, 0xbf, 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0xc3, 0x14,
+ 0x37, 0xa4, 0x02, 0x24, 0x13, 0x04, 0x84, 0x54, 0x03, 0x47, 0x24, 0x0c,
+ 0x85, 0x47, 0x63, 0x0a, 0xf7, 0x00, 0x97, 0xb0, 0xfe, 0xfb, 0xe7, 0x80,
+ 0xe0, 0x69, 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0xe3, 0x14, 0x97, 0x70,
+ 0x01, 0xfc, 0xe7, 0x80, 0x60, 0x7e, 0x65, 0xf5, 0x97, 0xb0, 0xfe, 0xfb,
+ 0xe7, 0x80, 0x80, 0x0f, 0x23, 0x01, 0x04, 0x0c, 0xe9, 0xbf, 0x01, 0x00,
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x83, 0x10, 0x9d, 0x47, 0x63, 0x1f,
+ 0xf5, 0x00, 0x37, 0x94, 0x01, 0x24, 0x13, 0x04, 0x04, 0x53, 0x85, 0x67,
+ 0xa2, 0x97, 0x83, 0xc7, 0xa7, 0xcf, 0x9d, 0xe7, 0x17, 0x43, 0x02, 0xfc,
+ 0x67, 0x00, 0xc3, 0x10, 0x2a, 0x84, 0xef, 0xd0, 0x7f, 0xdd, 0x85, 0x47,
+ 0xe3, 0x18, 0xf4, 0xfe, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x4c,
+ 0x23, 0xae, 0x07, 0x10, 0x23, 0xa4, 0x07, 0x7e, 0x17, 0x43, 0x02, 0xfc,
+ 0x67, 0x00, 0x83, 0x0e, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0xd3,
+ 0x71, 0xf5, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x60, 0xd4, 0x69, 0xf1,
+ 0x8d, 0x67, 0x3e, 0x94, 0x83, 0x27, 0x84, 0x6d, 0xb7, 0x24, 0x01, 0x24,
+ 0x93, 0x84, 0x04, 0x5f, 0x91, 0xef, 0x83, 0xa7, 0x44, 0x0e, 0x99, 0xcb,
+ 0xb7, 0xd7, 0x01, 0x24, 0x83, 0xc7, 0x07, 0xfa, 0xc5, 0xd3, 0x97, 0x00,
+ 0xff, 0xfb, 0xe7, 0x80, 0x20, 0xe3, 0x59, 0xbf, 0x83, 0xa7, 0xc4, 0x0a,
+ 0xc1, 0xdb, 0x05, 0x45, 0x97, 0x30, 0xfe, 0xfb, 0xe7, 0x80, 0x80, 0x51,
+ 0xb7, 0x35, 0x20, 0x2d, 0x75, 0x78, 0x37, 0xf5, 0x20, 0x2d, 0x93, 0x85,
+ 0x05, 0x60, 0x13, 0x08, 0x08, 0xa0, 0x91, 0x68, 0x13, 0x05, 0x05, 0x60,
+ 0xb3, 0x87, 0x05, 0x01, 0x03, 0xc7, 0x07, 0x00, 0x93, 0x06, 0xf0, 0x0f,
+ 0x13, 0x16, 0x87, 0x01, 0x61, 0x86, 0x06, 0x07, 0x63, 0x44, 0x06, 0x00,
+ 0x93, 0x76, 0xf7, 0x0f, 0x23, 0x80, 0xd7, 0x00, 0x85, 0x07, 0xe3, 0x91,
+ 0xb7, 0xfe, 0xb3, 0x85, 0x17, 0x01, 0xe3, 0x9b, 0xa5, 0xfc, 0xb7, 0xa7,
+ 0x02, 0x24, 0x05, 0x47, 0x01, 0x45, 0xa3, 0x84, 0xe7, 0x60, 0x97, 0x30,
+ 0xfe, 0xfb, 0xe7, 0x80, 0xe0, 0x4b, 0xb7, 0xd7, 0x01, 0x24, 0x83, 0xc7,
+ 0x07, 0xfa, 0x8d, 0xd3, 0x83, 0x27, 0x84, 0x6d, 0x91, 0xff, 0x83, 0xa7,
+ 0x44, 0x0e, 0x99, 0xdb, 0x9d, 0xbf, 0x01, 0x00, 0x17, 0x43, 0x02, 0xfc,
+ 0xe7, 0x02, 0x83, 0xff, 0xb7, 0xd7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xf4,
+ 0x03, 0xc7, 0x17, 0x05, 0x2a, 0x84, 0x11, 0xc7, 0x03, 0xc7, 0x17, 0x00,
+ 0x89, 0x47, 0x63, 0x07, 0xf7, 0x04, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87,
+ 0x07, 0x87, 0x83, 0xa4, 0x87, 0x0f, 0x03, 0xa9, 0xc7, 0x0f, 0x01, 0x46,
+ 0xa6, 0x85, 0x4a, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0x40, 0x54,
+ 0x22, 0x85, 0x97, 0xd0, 0xfe, 0xfb, 0xe7, 0x80, 0x20, 0xd7, 0x4a, 0x85,
+ 0x05, 0x46, 0xa6, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0xc0, 0x52,
+ 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x11, 0x45, 0x82, 0x97,
+ 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0x83, 0xfb, 0xb7, 0xe7, 0x00, 0x24,
+ 0x83, 0xd6, 0xc7, 0xc8, 0x85, 0x67, 0x13, 0x87, 0xf7, 0xb3, 0xe3, 0x94,
+ 0xe6, 0xfa, 0x37, 0x97, 0x01, 0x24, 0x13, 0x07, 0x07, 0x53, 0xba, 0x97,
+ 0x03, 0xa5, 0x07, 0xb2, 0x81, 0x45, 0x33, 0x25, 0xa0, 0x00, 0x97, 0xd0,
+ 0x00, 0xfc, 0xe7, 0x80, 0x60, 0xbb, 0x61, 0xb7, 0x17, 0x43, 0x02, 0xfc,
+ 0xe7, 0x02, 0xc3, 0xf5, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0x37,
+ 0x11, 0xc5, 0xb7, 0xe7, 0x00, 0x24, 0x83, 0xc7, 0xc7, 0x84, 0xbd, 0xef,
+ 0x13, 0x84, 0x81, 0xe7, 0x03, 0x47, 0x84, 0x00, 0x85, 0x47, 0x63, 0x03,
+ 0xf7, 0x06, 0x03, 0x57, 0x24, 0x03, 0xb7, 0x67, 0x00, 0x40, 0x23, 0x98,
+ 0xe7, 0x18, 0x83, 0x57, 0x44, 0x03, 0x37, 0x67, 0x00, 0x40, 0x23, 0x14,
+ 0xf7, 0x20, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80, 0x20, 0x34, 0x19, 0xc5,
+ 0xb7, 0xe7, 0x00, 0x24, 0x03, 0xc7, 0xc7, 0x84, 0x81, 0x47, 0x09, 0xeb,
+ 0x83, 0x46, 0x84, 0x00, 0x05, 0x47, 0x81, 0x47, 0x63, 0x84, 0xe6, 0x00,
+ 0x83, 0x57, 0xc4, 0x05, 0x37, 0xa7, 0x00, 0x40, 0x23, 0x12, 0xf7, 0x10,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0xb6, 0x35, 0xc1, 0x97, 0x70,
+ 0xff, 0xfb, 0xe7, 0x80, 0x60, 0xb7, 0x05, 0xc9, 0x17, 0x43, 0x02, 0xfc,
+ 0x67, 0x00, 0xc3, 0xef, 0xb7, 0x67, 0x00, 0x40, 0x23, 0x98, 0x07, 0x18,
+ 0x81, 0x47, 0x55, 0xb7, 0xb7, 0x67, 0x00, 0x40, 0x23, 0x98, 0x07, 0x18,
+ 0x13, 0x84, 0x81, 0xe7, 0x83, 0x46, 0x84, 0x00, 0x05, 0x47, 0x81, 0x47,
+ 0xe3, 0x95, 0xe6, 0xf8, 0x69, 0xb7, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80,
+ 0x20, 0x2d, 0x31, 0xed, 0x83, 0x46, 0x84, 0x00, 0x05, 0x47, 0x81, 0x47,
+ 0x63, 0x84, 0xe6, 0x00, 0x83, 0x57, 0x44, 0x08, 0x37, 0x87, 0x00, 0x40,
+ 0x23, 0x14, 0xf7, 0x10, 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0xc3, 0xea,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0x40, 0xb1, 0x59, 0xf9, 0x97, 0x60,
+ 0xff, 0xfb, 0xe7, 0x80, 0xe0, 0x29, 0x19, 0xc5, 0xb7, 0xe7, 0x00, 0x24,
+ 0x03, 0xc7, 0xc7, 0x84, 0x81, 0x47, 0x09, 0xeb, 0x83, 0x46, 0x84, 0x00,
+ 0x05, 0x47, 0x81, 0x47, 0x63, 0x84, 0xe6, 0x00, 0x83, 0x57, 0x64, 0x07,
+ 0x37, 0x07, 0x01, 0x40, 0x23, 0x14, 0xf7, 0x10, 0x9d, 0xb7, 0xb7, 0xe7,
+ 0x00, 0x24, 0x03, 0xc7, 0xc7, 0x84, 0x81, 0x47, 0x55, 0xf7, 0x69, 0xbf,
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x03, 0xe1, 0x41, 0x11, 0x3a, 0x84,
+ 0x22, 0xe6, 0x26, 0xe4, 0x4a, 0xe2, 0x4e, 0xe0, 0xaa, 0x84, 0x36, 0x89,
+ 0x97, 0xa0, 0xfe, 0xfb, 0xe7, 0x80, 0x80, 0x66, 0xb7, 0x27, 0x02, 0x24,
+ 0x93, 0x87, 0x07, 0x6b, 0xa2, 0x97, 0x05, 0x67, 0xba, 0x97, 0x83, 0xc7,
+ 0x07, 0x8d, 0x63, 0x9d, 0x07, 0x18, 0x83, 0xc7, 0x04, 0x00, 0x63, 0x99,
+ 0x07, 0x18, 0xb7, 0xa7, 0x02, 0x24, 0x93, 0x89, 0x87, 0x54, 0x03, 0xc7,
+ 0x99, 0x05, 0x63, 0x01, 0x07, 0x18, 0x03, 0xca, 0xa9, 0x05, 0x03, 0xd6,
+ 0xa9, 0x0b, 0x37, 0xe7, 0x01, 0x24, 0x03, 0x55, 0x67, 0x5f, 0x93, 0x87,
+ 0x87, 0x54, 0x01, 0x47, 0xa1, 0x45, 0x63, 0x69, 0xa6, 0x22, 0x83, 0xd6,
+ 0xc7, 0x0a, 0x89, 0x07, 0x63, 0xf1, 0xa6, 0x26, 0x05, 0x07, 0xe3, 0x18,
+ 0xb7, 0xfe, 0x37, 0xcb, 0x02, 0x24, 0x53, 0x09, 0x00, 0xf0, 0x87, 0x27,
+ 0x8b, 0xb7, 0x9d, 0x46, 0x43, 0x79, 0xf9, 0x90, 0x13, 0x07, 0x07, 0x05,
+ 0x06, 0x07, 0x4e, 0x97, 0x83, 0x57, 0xc7, 0x00, 0x11, 0x8d, 0x53, 0x77,
+ 0x05, 0xd0, 0x91, 0x8f, 0xd3, 0xf7, 0x07, 0xd0, 0x93, 0x17, 0x3a, 0x00,
+ 0xb6, 0x97, 0x53, 0x77, 0xf7, 0x18, 0x93, 0x87, 0x87, 0x02, 0x86, 0x07,
+ 0xce, 0x97, 0x83, 0xd7, 0xc7, 0x00, 0x07, 0x26, 0x8b, 0xb7, 0x13, 0xf7,
+ 0xf7, 0x0f, 0xa1, 0x83, 0xd3, 0x77, 0x07, 0xd0, 0xd3, 0xf6, 0x07, 0xd0,
+ 0xc3, 0xf7, 0xc7, 0x68, 0x53, 0x79, 0xf9, 0x08, 0x43, 0x79, 0xe9, 0x78,
+ 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0x8a, 0xaa, 0x8a, 0x93, 0xda,
+ 0x8a, 0x40, 0x97, 0x70, 0xff, 0xfb, 0xe7, 0x80, 0xe0, 0x89, 0xc2, 0x0a,
+ 0x93, 0x07, 0x8a, 0x04, 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xda, 0x0a, 0x41,
+ 0xd3, 0xf7, 0x0a, 0xd0, 0xd3, 0x74, 0x05, 0xd0, 0x07, 0x27, 0x8b, 0xb7,
+ 0x86, 0x07, 0xce, 0x97, 0x03, 0xdc, 0xc7, 0x00, 0xc3, 0xf4, 0xe4, 0x78,
+ 0xdc, 0x4c, 0x53, 0x74, 0x0c, 0xd0, 0xd3, 0x07, 0x00, 0xf0, 0x83, 0xd4,
+ 0xc7, 0x00, 0x53, 0xf4, 0x84, 0x08, 0x13, 0x0a, 0x0a, 0x05, 0x06, 0x0a,
+ 0x4e, 0x9a, 0x03, 0x5a, 0x4a, 0x00, 0xd3, 0x17, 0xf4, 0xa0, 0x99, 0xc3,
+ 0x53, 0x14, 0x84, 0x20, 0xb7, 0xcb, 0x02, 0x24, 0x83, 0xa7, 0x0b, 0xb7,
+ 0x0d, 0x45, 0x82, 0x97, 0xd3, 0x97, 0x14, 0xc0, 0xc2, 0x07, 0xc1, 0x83,
+ 0x63, 0x95, 0x87, 0x0b, 0xb7, 0x47, 0x01, 0x24, 0x93, 0x87, 0x07, 0x27,
+ 0x03, 0xd7, 0x67, 0x12, 0x83, 0xd6, 0xe7, 0x10, 0x89, 0x47, 0x7d, 0x17,
+ 0xb3, 0x97, 0xe7, 0x00, 0xd3, 0xf7, 0x07, 0xd0, 0x53, 0xf7, 0x16, 0xd0,
+ 0x53, 0x04, 0x00, 0xf0, 0xd3, 0xf7, 0x27, 0x11, 0x37, 0xca, 0x02, 0x24,
+ 0xd3, 0xf7, 0xe7, 0x18, 0xb7, 0xc7, 0x02, 0x24, 0x07, 0xa7, 0xc7, 0xb7,
+ 0x83, 0xa7, 0x0b, 0xb7, 0x25, 0x45, 0xd3, 0xf7, 0xe7, 0x00, 0xd3, 0x9a,
+ 0x17, 0xc0, 0x82, 0x97, 0x87, 0x27, 0x0a, 0xb8, 0xc2, 0x0a, 0x93, 0xda,
+ 0x0a, 0x01, 0x53, 0x74, 0xf4, 0x10, 0xd6, 0x94, 0xc2, 0x04, 0x23, 0x93,
+ 0x59, 0x0d, 0xc1, 0x80, 0xd3, 0x17, 0x14, 0xc0, 0x23, 0x92, 0xf9, 0x0c,
+ 0xb7, 0x07, 0x00, 0x40, 0x19, 0xec, 0x93, 0x87, 0xe7, 0x03, 0xca, 0x97,
+ 0x23, 0x90, 0x97, 0x00, 0x32, 0x64, 0xa2, 0x64, 0x12, 0x69, 0x82, 0x69,
+ 0x41, 0x01, 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0x23, 0xc7, 0x93, 0x87,
+ 0x07, 0x04, 0x32, 0x64, 0xa2, 0x64, 0x12, 0x69, 0x82, 0x69, 0xca, 0x97,
+ 0x23, 0x90, 0x97, 0x00, 0x41, 0x01, 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00,
+ 0x63, 0xc5, 0x93, 0x77, 0xfa, 0x0f, 0x13, 0x5a, 0x8a, 0x00, 0x87, 0x29,
+ 0x8b, 0xb7, 0xd3, 0xf7, 0x07, 0xd0, 0xd3, 0x76, 0x0a, 0xd0, 0x37, 0xca,
+ 0x02, 0x24, 0x07, 0x27, 0x0a, 0xb8, 0xc3, 0xf7, 0x37, 0x69, 0x53, 0x74,
+ 0xf4, 0x18, 0x53, 0x74, 0xe4, 0x10, 0x53, 0x1b, 0x14, 0xc0, 0x42, 0x0b,
+ 0x13, 0x5b, 0x0b, 0x01, 0x5a, 0x85, 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80,
+ 0xa0, 0x1a, 0xaa, 0x8a, 0x5a, 0x85, 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80,
+ 0xe0, 0x19, 0x93, 0xda, 0x8a, 0x00, 0xd3, 0x97, 0x04, 0xc0, 0xc2, 0x0a,
+ 0x13, 0x75, 0xf5, 0x0f, 0x93, 0xda, 0x0a, 0x01, 0x53, 0x74, 0x05, 0xd0,
+ 0xd3, 0xf7, 0x0a, 0xd0, 0xc2, 0x07, 0xc1, 0x87, 0x43, 0x74, 0x34, 0x79,
+ 0x63, 0xd7, 0x87, 0x03, 0x53, 0x74, 0x89, 0x18, 0xb7, 0x47, 0x01, 0x24,
+ 0x93, 0x87, 0x07, 0x27, 0x03, 0xd7, 0x67, 0x12, 0x83, 0xd6, 0xe7, 0x10,
+ 0x89, 0x47, 0x7d, 0x17, 0xb3, 0x97, 0xe7, 0x00, 0xd3, 0xf7, 0x07, 0xd0,
+ 0x53, 0xf7, 0x16, 0xd0, 0xd3, 0xf7, 0x87, 0x10, 0xc5, 0xbd, 0x53, 0x74,
+ 0x89, 0x10, 0xd9, 0xbf, 0x93, 0x17, 0x4a, 0x00, 0xce, 0x97, 0x83, 0xd7,
+ 0xa7, 0x06, 0x93, 0xf6, 0xf7, 0x0f, 0x37, 0xcb, 0x02, 0x24, 0xa1, 0x83,
+ 0x53, 0xf9, 0x06, 0xd0, 0xd3, 0xf7, 0x07, 0xd0, 0x07, 0x27, 0x8b, 0xb7,
+ 0x43, 0x79, 0xe9, 0x78, 0xe3, 0x0e, 0x07, 0xe0, 0x93, 0x07, 0xf7, 0x04,
+ 0x86, 0x07, 0xce, 0x97, 0x03, 0xd6, 0xc7, 0x00, 0x93, 0x06, 0xf7, 0xff,
+ 0x75, 0xbb, 0x93, 0x17, 0x3a, 0x00, 0xba, 0x97, 0x93, 0x87, 0x87, 0x02,
+ 0x86, 0x07, 0xce, 0x97, 0x83, 0xd7, 0xc7, 0x00, 0x7d, 0xbf, 0x01, 0x00,
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x63, 0xb3, 0xb7, 0x47, 0x01, 0x24,
+ 0x03, 0xd7, 0xc7, 0xe1, 0x89, 0x47, 0x2a, 0x84, 0xae, 0x84, 0x63, 0x19,
+ 0xf7, 0x00, 0xb7, 0xa7, 0x01, 0x24, 0x03, 0xa7, 0x47, 0x06, 0xfd, 0x57,
+ 0x63, 0x04, 0xf7, 0x04, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87,
+ 0x03, 0xa9, 0x87, 0x10, 0x83, 0xa9, 0xc7, 0x10, 0x01, 0x46, 0xca, 0x85,
+ 0x4e, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0x60, 0x09, 0xa6, 0x85,
+ 0x22, 0x85, 0x97, 0xc0, 0x00, 0xfc, 0xe7, 0x80, 0x60, 0x75, 0x4e, 0x85,
+ 0x05, 0x46, 0xca, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0xc0, 0x07,
+ 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x15, 0x45, 0x82, 0x97,
+ 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0xe3, 0xaf, 0xb7, 0xc7, 0x02, 0x24,
+ 0x03, 0xa6, 0x47, 0xb7, 0xb7, 0x07, 0x00, 0x40, 0x93, 0x87, 0x07, 0x06,
+ 0x3e, 0x96, 0x09, 0x67, 0x13, 0x08, 0x05, 0x02, 0xaa, 0x87, 0x09, 0x8e,
+ 0x13, 0x07, 0xf7, 0xf1, 0x23, 0x90, 0xe7, 0x00, 0xb3, 0x06, 0xf6, 0x00,
+ 0x23, 0x90, 0xe6, 0x00, 0x89, 0x07, 0xe3, 0x99, 0x07, 0xff, 0x83, 0xc7,
+ 0xc5, 0x00, 0xb1, 0xcb, 0x83, 0xaf, 0x05, 0x00, 0x09, 0x63, 0x13, 0x88,
+ 0xe5, 0x00, 0x81, 0x47, 0x0d, 0x4f, 0x85, 0x4e, 0x09, 0x4e, 0x13, 0x03,
+ 0x03, 0xf0, 0x33, 0x17, 0xff, 0x00, 0x33, 0x77, 0xf7, 0x01, 0x33, 0x96,
+ 0xfe, 0x00, 0xb3, 0x16, 0xfe, 0x00, 0x79, 0x8e, 0xb3, 0x08, 0xf5, 0x00,
+ 0xf9, 0x8e, 0x89, 0x07, 0x7d, 0x47, 0x19, 0xc2, 0x03, 0x47, 0x08, 0x00,
+ 0x1a, 0x86, 0x81, 0xc6, 0x03, 0x46, 0x18, 0x00, 0x22, 0x06, 0x51, 0x8f,
+ 0x23, 0x90, 0xe8, 0x00, 0x03, 0xc7, 0xc5, 0x00, 0x09, 0x08, 0xe3, 0xc4,
+ 0xe7, 0xfc, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x1d, 0x45,
+ 0x82, 0x87, 0x01, 0x00, 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x43, 0xa4,
+ 0xb7, 0xa7, 0x02, 0x24, 0x03, 0xc7, 0x67, 0x60, 0x85, 0x47, 0x63, 0x0c,
+ 0xf7, 0x00, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xa7, 0x07, 0xb7, 0x21, 0x45,
+ 0x82, 0x97, 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0x63, 0xa4, 0x97, 0x60,
+ 0xff, 0xfb, 0xe7, 0x80, 0xe0, 0xe8, 0x75, 0xd1, 0xb7, 0xe7, 0x00, 0x24,
+ 0x83, 0xc7, 0xb7, 0xad, 0xe9, 0xff, 0xb7, 0xb7, 0x00, 0x24, 0x03, 0xd7,
+ 0x47, 0x33, 0xb7, 0x07, 0x01, 0x40, 0x23, 0x99, 0xe7, 0xdc, 0xe1, 0xb7,
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x43, 0x9f, 0xb7, 0xb7, 0x02, 0x24,
+ 0x93, 0x87, 0x87, 0xb4, 0x23, 0xae, 0xf1, 0x94, 0x37, 0x64, 0x01, 0x24,
+ 0x9d, 0x66, 0xb7, 0xb5, 0x02, 0x24, 0xb7, 0xb7, 0x02, 0x24, 0x13, 0x04,
+ 0x04, 0x40, 0x93, 0x87, 0xc7, 0x83, 0x93, 0x86, 0xf6, 0xbf, 0x11, 0x46,
+ 0x93, 0x85, 0x05, 0xfb, 0x05, 0x45, 0x5c, 0xc4, 0x97, 0xe0, 0xff, 0xfb,
+ 0xe7, 0x80, 0xc0, 0xe8, 0xc1, 0x66, 0xb7, 0xb5, 0x02, 0x24, 0xfd, 0x16,
+ 0x31, 0x46, 0x93, 0x85, 0x45, 0x98, 0x41, 0x45, 0x97, 0xe0, 0xff, 0xfb,
+ 0xe7, 0x80, 0x40, 0xe7, 0x37, 0xb7, 0x02, 0x24, 0x13, 0x07, 0x87, 0xb7,
+ 0xb7, 0xa7, 0x02, 0x24, 0x93, 0x87, 0x87, 0x54, 0x78, 0xc8, 0x37, 0xb7,
+ 0x02, 0x24, 0xa3, 0x80, 0x07, 0x0c, 0x23, 0x81, 0x07, 0x0c, 0x13, 0x07,
+ 0xc7, 0xc2, 0xb7, 0xb7, 0x02, 0x24, 0x18, 0xd4, 0x93, 0x87, 0x47, 0x2d,
+ 0x37, 0xb7, 0x02, 0x24, 0x7c, 0xc4, 0x13, 0x07, 0x87, 0x3b, 0xb7, 0xb7,
+ 0x02, 0x24, 0x18, 0xc0, 0x93, 0x87, 0x47, 0x37, 0x23, 0xaa, 0xf1, 0xa4,
+ 0x17, 0x43, 0x02, 0xfc, 0x67, 0x00, 0xc3, 0x97, 0x14, 0xa6, 0x02, 0x24,
+ 0x00, 0x8d, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3b, 0x00, 0x00, 0x00, 0x3f,
+ 0x00, 0x00, 0x80, 0x43,
+};
+
+static const u8 s5kjn5_data_bc98[] = {
+ 0x17, 0x43, 0x02, 0xfc, 0xe7, 0x02, 0x83, 0x82, 0x2a, 0x84, 0xef, 0xe0,
+ 0xbf, 0xb9, 0xa1, 0x47, 0x63, 0x06, 0xf4, 0x00, 0x17, 0x43, 0x02, 0xfc,
+ 0x67, 0x00, 0x83, 0x83, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xc7, 0x87, 0xb8,
+ 0xe5, 0xdb, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53, 0x05, 0x67,
+ 0x3e, 0x97, 0x83, 0x46, 0x07, 0xb9, 0xf9, 0xde, 0x83, 0xc7, 0x67, 0x3f,
+ 0xe1, 0xdf, 0x83, 0x57, 0x47, 0xb6, 0x93, 0xe7, 0x07, 0x20, 0x23, 0x12,
+ 0xf7, 0xb6, 0xe9, 0xb7, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x43, 0x7b,
+ 0x37, 0xc8, 0x02, 0x24, 0x13, 0x08, 0x48, 0xb8, 0x83, 0x48, 0x48, 0x00,
+ 0x2a, 0x8b, 0xae, 0x8b, 0x32, 0x84, 0xb6, 0x84, 0x3a, 0x89, 0xbe, 0x89,
+ 0x63, 0x80, 0x08, 0x02, 0xb7, 0xa7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53,
+ 0x03, 0xc7, 0x07, 0xb9, 0x83, 0xc7, 0xb7, 0x92, 0x11, 0xc7, 0x03, 0x47,
+ 0x58, 0x00, 0xbd, 0x8b, 0x63, 0x06, 0xf7, 0x04, 0x37, 0xe8, 0x01, 0x24,
+ 0x13, 0x08, 0x08, 0x87, 0x83, 0x2a, 0x08, 0x12, 0x03, 0x2a, 0x48, 0x12,
+ 0x01, 0x46, 0xd6, 0x85, 0x52, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80,
+ 0xa0, 0xd0, 0xce, 0x87, 0x4a, 0x87, 0xa6, 0x86, 0x22, 0x86, 0xde, 0x85,
+ 0x5a, 0x85, 0x97, 0x40, 0x00, 0xfc, 0xe7, 0x80, 0xa0, 0x66, 0x05, 0x46,
+ 0xd6, 0x85, 0x52, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0x80, 0xce,
+ 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0xc3, 0x76, 0x23, 0x15, 0x06, 0x00,
+ 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80, 0x80, 0xba, 0x01, 0xcd, 0xb7, 0x97,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0xd7, 0x03, 0xc7, 0xc7, 0x00, 0x59, 0xdf,
+ 0x7d, 0x17, 0x23, 0x86, 0xe7, 0x00, 0x59, 0xbf, 0x97, 0x60, 0xff, 0xfb,
+ 0xe7, 0x80, 0x80, 0xb5, 0x6d, 0xd1, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87,
+ 0x07, 0xd7, 0x03, 0xc7, 0xd7, 0x00, 0x3d, 0xdf, 0x7d, 0x17, 0xa3, 0x86,
+ 0xe7, 0x00, 0x9d, 0xbf, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x63, 0x6f,
+ 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87, 0x03, 0xaa, 0x87, 0x12,
+ 0x83, 0xa9, 0xc7, 0x12, 0xae, 0x84, 0x2a, 0x84, 0x32, 0x89, 0xd2, 0x85,
+ 0x01, 0x46, 0x4e, 0x85, 0x97, 0x30, 0x01, 0xfc, 0xe7, 0x80, 0x00, 0xc7,
+ 0xa6, 0x85, 0x4a, 0x86, 0x22, 0x85, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80,
+ 0x20, 0x6a, 0xaa, 0x84, 0x05, 0x46, 0xd2, 0x85, 0x4e, 0x85, 0x97, 0x30,
+ 0x01, 0xfc, 0xe7, 0x80, 0x20, 0xc5, 0xb7, 0xc7, 0x02, 0x24, 0x93, 0x87,
+ 0x47, 0xb8, 0x03, 0xc7, 0xe7, 0x10, 0x15, 0xc3, 0x37, 0xa7, 0x01, 0x24,
+ 0x13, 0x07, 0x07, 0x53, 0x03, 0x46, 0x37, 0xb9, 0x89, 0x46, 0x63, 0x1a,
+ 0xd6, 0x00, 0x83, 0x56, 0x87, 0xba, 0xe1, 0x8e, 0x89, 0xc6, 0x93, 0x06,
+ 0x00, 0x40, 0x63, 0x07, 0xd4, 0x00, 0x26, 0x85, 0x17, 0x33, 0x02, 0xfc,
+ 0x67, 0x00, 0xe3, 0x6a, 0x83, 0x26, 0x47, 0xb3, 0x7d, 0x57, 0xe3, 0x88,
+ 0xe6, 0xfe, 0x03, 0xd7, 0x27, 0x11, 0x93, 0x96, 0x04, 0x01, 0xc1, 0x82,
+ 0x11, 0xe3, 0x36, 0x87, 0xba, 0x84, 0x23, 0x99, 0xd7, 0x10, 0xe1, 0xbf,
+ 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x23, 0x65, 0x37, 0x29, 0x00, 0x24,
+ 0xb7, 0xa4, 0x01, 0x24, 0x13, 0x09, 0x09, 0x33, 0x93, 0x84, 0x04, 0x53,
+ 0x83, 0x47, 0x49, 0x1a, 0x03, 0xc7, 0x24, 0xb7, 0x2a, 0x84, 0xd9, 0x8f,
+ 0x63, 0x82, 0x07, 0x14, 0x83, 0x47, 0xe4, 0x00, 0x05, 0x47, 0x23, 0x05,
+ 0xe4, 0x00, 0x99, 0xe7, 0x83, 0x47, 0xc4, 0x00, 0xd1, 0xcf, 0x83, 0xc7,
+ 0x24, 0xb7, 0xc5, 0xcb, 0xb7, 0x6a, 0x01, 0x24, 0x13, 0x0a, 0x04, 0x03,
+ 0x03, 0x47, 0x04, 0x00, 0xa1, 0x69, 0xfd, 0x19, 0xa3, 0x01, 0xe4, 0x00,
+ 0x83, 0xa7, 0x0a, 0x4b, 0x23, 0x02, 0xe4, 0x00, 0x05, 0x67, 0xba, 0x97,
+ 0x83, 0xd7, 0x47, 0xe0, 0x23, 0x03, 0x04, 0x00, 0xb3, 0xf7, 0x37, 0x01,
+ 0x23, 0x1c, 0xf4, 0x00, 0x97, 0x40, 0xfd, 0xfb, 0xe7, 0x80, 0x00, 0x67,
+ 0x03, 0x58, 0x84, 0x01, 0xa3, 0x08, 0xa4, 0x00, 0x63, 0x01, 0x08, 0x06,
+ 0x37, 0x36, 0x05, 0x20, 0x13, 0x06, 0x06, 0xc8, 0x81, 0x46, 0x81, 0x47,
+ 0x41, 0x45, 0xb3, 0x05, 0xf4, 0x00, 0x33, 0x57, 0xf8, 0x40, 0x23, 0x80,
+ 0xd5, 0x02, 0x05, 0x8b, 0x85, 0x07, 0x11, 0xc7, 0x03, 0x47, 0x06, 0x00,
+ 0xba, 0x96, 0x93, 0xf6, 0xf6, 0x0f, 0x05, 0x06, 0xe3, 0x91, 0xa7, 0xfe,
+ 0x23, 0x08, 0xd4, 0x00, 0x83, 0x47, 0x49, 0x1a, 0x03, 0xc7, 0x24, 0xb7,
+ 0xd9, 0x8f, 0xc9, 0xc3, 0x23, 0x07, 0x04, 0x00, 0x23, 0x2e, 0x44, 0x01,
+ 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0xa3, 0x5b, 0x83, 0x47, 0xb4, 0x00,
+ 0xa5, 0xd7, 0x83, 0xc7, 0x24, 0xb7, 0xad, 0xf3, 0x39, 0xa0, 0x01, 0x48,
+ 0x45, 0xf1, 0x23, 0x1c, 0x34, 0x01, 0x4e, 0x88, 0x61, 0xbf, 0xb7, 0x6a,
+ 0x01, 0x24, 0x83, 0xa5, 0x0a, 0x4b, 0x85, 0x67, 0x13, 0x0a, 0x04, 0x03,
+ 0x93, 0x87, 0x07, 0xe1, 0x13, 0x06, 0x80, 0x07, 0xbe, 0x95, 0x52, 0x85,
+ 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80, 0x40, 0x0a, 0x21, 0xc9, 0x23, 0x05,
+ 0x04, 0x00, 0x03, 0x47, 0x24, 0x01, 0x83, 0x47, 0x64, 0x00, 0x83, 0x56,
+ 0x44, 0x01, 0xa3, 0x08, 0xe4, 0x00, 0x05, 0x47, 0x23, 0x1c, 0xd4, 0x00,
+ 0x23, 0x07, 0xe4, 0x00, 0xa3, 0x01, 0xf4, 0x00, 0x23, 0x03, 0x04, 0x00,
+ 0x23, 0x2e, 0x44, 0x01, 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0xa3, 0x54,
+ 0x83, 0xa5, 0x0a, 0x4b, 0x85, 0x67, 0x93, 0x87, 0x07, 0xe1, 0x13, 0x06,
+ 0x00, 0x0f, 0xbe, 0x95, 0x52, 0x85, 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80,
+ 0x20, 0x05, 0x9d, 0xb7, 0x83, 0x47, 0xa4, 0x00, 0xcd, 0xdb, 0xcd, 0xb5,
+ 0x37, 0xa5, 0x01, 0x24, 0x13, 0x05, 0x05, 0x0c, 0x97, 0x60, 0xff, 0xfb,
+ 0xe7, 0x80, 0x80, 0x43, 0x45, 0xbd, 0x01, 0x00, 0x17, 0x33, 0x02, 0xfc,
+ 0xe7, 0x02, 0x03, 0x4f, 0x83, 0x47, 0x15, 0x01, 0xa3, 0x04, 0x05, 0x00,
+ 0x2a, 0x84, 0x91, 0xef, 0x83, 0x57, 0x85, 0x01, 0x99, 0xeb, 0x83, 0x47,
+ 0xf5, 0x00, 0xa3, 0x07, 0x05, 0x00, 0xa3, 0x04, 0xf5, 0x00, 0x17, 0x33,
+ 0x02, 0xfc, 0x67, 0x00, 0xe3, 0x4e, 0x22, 0x85, 0x97, 0x90, 0xff, 0xfb,
+ 0xe7, 0x80, 0xc0, 0xc4, 0x83, 0x47, 0x34, 0x00, 0x03, 0x47, 0x64, 0x00,
+ 0x83, 0x46, 0x74, 0x00, 0xfd, 0x17, 0x05, 0x07, 0x93, 0xf7, 0xf7, 0x0f,
+ 0x23, 0x03, 0xe4, 0x00, 0xa3, 0x01, 0xf4, 0x00, 0x99, 0xc2, 0xa3, 0x03,
+ 0x04, 0x00, 0xb1, 0xef, 0x03, 0x47, 0x14, 0x01, 0x83, 0x56, 0x84, 0x01,
+ 0x83, 0x47, 0x54, 0x00, 0x23, 0x09, 0xe4, 0x00, 0x05, 0x47, 0x23, 0x1a,
+ 0xd4, 0x00, 0x23, 0x04, 0xe4, 0x00, 0x23, 0x1c, 0x04, 0x00, 0xa3, 0x08,
+ 0x04, 0x00, 0xc5, 0xe3, 0x83, 0x47, 0x14, 0x00, 0x13, 0xf7, 0x27, 0x00,
+ 0x19, 0xc7, 0x03, 0x47, 0x04, 0x00, 0x01, 0xc7, 0x03, 0x47, 0x24, 0x00,
+ 0x4d, 0xc3, 0x85, 0x8b, 0xa5, 0xcf, 0xb7, 0x27, 0x00, 0x24, 0x83, 0xc7,
+ 0x27, 0x4d, 0xd1, 0xd3, 0xb7, 0x67, 0x01, 0x24, 0x83, 0xa7, 0x07, 0x4b,
+ 0x05, 0x67, 0xba, 0x97, 0x23, 0x80, 0x07, 0xe0, 0x8d, 0xbf, 0x03, 0x47,
+ 0x04, 0x01, 0x5c, 0x4c, 0x93, 0x16, 0x17, 0x00, 0xb6, 0x97, 0x5c, 0xcc,
+ 0xb7, 0x27, 0x00, 0x24, 0x93, 0x87, 0x07, 0x33, 0x83, 0xc6, 0x37, 0x1a,
+ 0x89, 0xea, 0x83, 0x46, 0x64, 0x01, 0xa1, 0xda, 0xb7, 0xa6, 0x01, 0x24,
+ 0x83, 0xc6, 0x26, 0x0a, 0xb9, 0xf2, 0x83, 0xc7, 0x47, 0x1a, 0xa1, 0xf3,
+ 0x03, 0x46, 0x04, 0x00, 0xb7, 0x67, 0x01, 0x24, 0x83, 0xa5, 0x07, 0x4b,
+ 0x33, 0x06, 0xe6, 0x02, 0x85, 0x67, 0x93, 0x87, 0x07, 0xe1, 0xbe, 0x95,
+ 0x13, 0x05, 0x04, 0x03, 0x06, 0x06, 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80,
+ 0x60, 0xf2, 0x21, 0xbf, 0x85, 0x47, 0xa3, 0x04, 0xf4, 0x00, 0x17, 0x33,
+ 0x02, 0xfc, 0x67, 0x00, 0xe3, 0x3f, 0xfd, 0x17, 0xa3, 0x02, 0xf4, 0x00,
+ 0x22, 0x85, 0x97, 0x60, 0xff, 0xfb, 0xe7, 0x80, 0x60, 0x11, 0x17, 0x33,
+ 0x02, 0xfc, 0x67, 0x00, 0x63, 0x3e, 0x22, 0x85, 0x97, 0x60, 0xff, 0xfb,
+ 0xe7, 0x80, 0x40, 0x10, 0xdd, 0xb5, 0x01, 0x00, 0x89, 0x47, 0x63, 0x03,
+ 0xf5, 0x00, 0x82, 0x80, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0xa3, 0x38,
+ 0xb7, 0x84, 0x01, 0x24, 0x93, 0x84, 0x04, 0xaa, 0x87, 0xa7, 0x04, 0x0a,
+ 0x41, 0x11, 0x37, 0xc5, 0x02, 0x24, 0x53, 0x96, 0x17, 0xc0, 0x74, 0x00,
+ 0x91, 0x45, 0x13, 0x05, 0xa5, 0xb8, 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80,
+ 0x60, 0xc3, 0x37, 0x19, 0x01, 0x40, 0x42, 0x05, 0x41, 0x81, 0x13, 0x0a,
+ 0x49, 0x24, 0xb7, 0x89, 0x01, 0x24, 0x37, 0xc4, 0x02, 0x24, 0xb7, 0xca,
+ 0x02, 0x24, 0x23, 0x17, 0xa1, 0x00, 0x93, 0x89, 0x89, 0xb1, 0x13, 0x04,
+ 0x24, 0xb9, 0x93, 0x8a, 0xaa, 0xbb, 0x33, 0x0a, 0x9a, 0x40, 0x06, 0x05,
+ 0x22, 0x95, 0x83, 0x55, 0x25, 0x00, 0x03, 0x56, 0xc1, 0x00, 0x03, 0x55,
+ 0x05, 0x00, 0x21, 0x04, 0x97, 0x60, 0x00, 0xfc, 0xe7, 0x80, 0x80, 0x82,
+ 0x42, 0x05, 0x41, 0x81, 0x23, 0x90, 0xa9, 0x00, 0xb3, 0x87, 0x49, 0x01,
+ 0x23, 0x90, 0xa7, 0x00, 0x89, 0x09, 0x63, 0x05, 0x54, 0x01, 0x03, 0x55,
+ 0xe1, 0x00, 0xf1, 0xb7, 0xb7, 0x89, 0x01, 0x24, 0x37, 0xca, 0x02, 0x24,
+ 0x13, 0x09, 0x09, 0x26, 0x93, 0x89, 0xa9, 0xaf, 0x13, 0x0a, 0x2a, 0xc3,
+ 0x83, 0x57, 0xe1, 0x00, 0x03, 0x56, 0xc1, 0x00, 0x85, 0x09, 0x86, 0x07,
+ 0xa2, 0x97, 0x83, 0xd5, 0x27, 0x00, 0x03, 0xd5, 0x07, 0x00, 0x09, 0x09,
+ 0x21, 0x04, 0x97, 0x50, 0x00, 0xfc, 0xe7, 0x80, 0x60, 0x7d, 0x13, 0x75,
+ 0xf5, 0x0f, 0xa3, 0x8f, 0xa9, 0xfe, 0x42, 0x05, 0x41, 0x81, 0x23, 0x1f,
+ 0xa9, 0xfe, 0xe3, 0x17, 0x44, 0xfd, 0xb7, 0x19, 0x01, 0x40, 0x37, 0x89,
+ 0x01, 0x24, 0x37, 0xca, 0x02, 0x24, 0x93, 0x89, 0x29, 0x1f, 0x13, 0x09,
+ 0xc9, 0xb2, 0x13, 0x0a, 0x2a, 0xc6, 0xb3, 0x89, 0x99, 0x40, 0x83, 0x57,
+ 0xe1, 0x00, 0x03, 0x56, 0xc1, 0x00, 0x86, 0x07, 0xa2, 0x97, 0x83, 0xd5,
+ 0x27, 0x00, 0x03, 0xd5, 0x07, 0x00, 0x21, 0x04, 0x97, 0x50, 0x00, 0xfc,
+ 0xe7, 0x80, 0x80, 0x78, 0x42, 0x05, 0x41, 0x81, 0x23, 0x10, 0xa9, 0x00,
+ 0xb3, 0x07, 0x39, 0x01, 0x23, 0x90, 0xa7, 0x00, 0x09, 0x09, 0xe3, 0x18,
+ 0x44, 0xfd, 0xb7, 0x17, 0x01, 0x40, 0x37, 0x89, 0x01, 0x24, 0xb7, 0xc9,
+ 0x02, 0x24, 0x93, 0x87, 0xa7, 0x20, 0x13, 0x09, 0x69, 0xb4, 0x93, 0x89,
+ 0x29, 0xc9, 0xb3, 0x84, 0x97, 0x40, 0x83, 0x57, 0xe1, 0x00, 0x03, 0x56,
+ 0xc1, 0x00, 0x86, 0x07, 0xa2, 0x97, 0x83, 0xd5, 0x27, 0x00, 0x03, 0xd5,
+ 0x07, 0x00, 0x21, 0x04, 0x97, 0x50, 0x00, 0xfc, 0xe7, 0x80, 0x80, 0x73,
+ 0x42, 0x05, 0x41, 0x81, 0x23, 0x10, 0xa9, 0x00, 0xb3, 0x07, 0x99, 0x00,
+ 0x23, 0x90, 0xa7, 0x00, 0x09, 0x09, 0xe3, 0x18, 0x34, 0xfd, 0x41, 0x01,
+ 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0x23, 0x24, 0x17, 0x33, 0x02, 0xfc,
+ 0xe7, 0x02, 0x03, 0x22, 0x2a, 0x84, 0xef, 0xe0, 0x3f, 0x98, 0x1d, 0xe0,
+ 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53, 0x0d, 0x67, 0x3e, 0x97,
+ 0x03, 0x27, 0x87, 0x6e, 0x05, 0x8b, 0x09, 0xcb, 0x37, 0x87, 0x00, 0x40,
+ 0x03, 0x57, 0x87, 0xf4, 0xa1, 0x46, 0x61, 0x8b, 0x63, 0x06, 0xd7, 0x00,
+ 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0x03, 0x21, 0x05, 0x67, 0xba, 0x97,
+ 0x23, 0x89, 0x07, 0xb6, 0xc5, 0xbf, 0x01, 0x00, 0x91, 0x47, 0x63, 0x03,
+ 0xf5, 0x00, 0x82, 0x80, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x03, 0x1d,
+ 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0x63, 0x09, 0xc5, 0x17, 0x33,
+ 0x02, 0xfc, 0x67, 0x00, 0x23, 0x1e, 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80,
+ 0xe0, 0x5d, 0x65, 0xf9, 0xb7, 0xc7, 0x02, 0x24, 0x03, 0xd7, 0x67, 0xb8,
+ 0xb7, 0xf7, 0x00, 0x40, 0x23, 0x90, 0xe7, 0x3e, 0xf9, 0xbf, 0x01, 0x00,
+ 0x37, 0xc7, 0x02, 0x24, 0x13, 0x07, 0x47, 0xb8, 0x83, 0x45, 0x07, 0x00,
+ 0xb7, 0xa7, 0x02, 0x24, 0xb7, 0xd6, 0x01, 0x24, 0x03, 0xd6, 0x47, 0x60,
+ 0x23, 0xa8, 0xb6, 0xda, 0xb7, 0x67, 0x01, 0x24, 0xb7, 0xc6, 0x02, 0x24,
+ 0x93, 0x87, 0x07, 0x40, 0x93, 0x86, 0x86, 0xc9, 0xd4, 0xc7, 0x09, 0xca,
+ 0xb7, 0xb6, 0x02, 0x24, 0x37, 0x26, 0x00, 0x24, 0x93, 0x86, 0x86, 0x68,
+ 0x23, 0x20, 0xd6, 0xce, 0x23, 0x19, 0x07, 0x10, 0x37, 0xc7, 0x02, 0x24,
+ 0x13, 0x07, 0x07, 0x2a, 0xb7, 0xc6, 0x02, 0x24, 0x98, 0xd7, 0x37, 0xc7,
+ 0x02, 0x24, 0x93, 0x86, 0x46, 0x11, 0x13, 0x07, 0x87, 0x2e, 0x23, 0xa4,
+ 0xd1, 0xa4, 0xd8, 0xc3, 0x82, 0x80, 0x00, 0x00,
+};
+
+static const u8 s5kjn5_data_c398[] = {
+ 0x29, 0xe1, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x63, 0x12, 0xb7, 0x97,
+ 0x01, 0x24, 0x93, 0x87, 0x07, 0x53, 0x85, 0x64, 0xbe, 0x94, 0x03, 0xc7,
+ 0xe4, 0xb6, 0x8d, 0x66, 0x33, 0x84, 0xd7, 0x00, 0x83, 0x27, 0x84, 0x6e,
+ 0x05, 0xc3, 0x85, 0x8b, 0x89, 0xcb, 0xb7, 0x87, 0x00, 0x40, 0x83, 0xd7,
+ 0x87, 0xf4, 0x21, 0x47, 0xe1, 0x8b, 0x63, 0x8b, 0xe7, 0x02, 0x17, 0x33,
+ 0x02, 0xfc, 0x67, 0x00, 0x23, 0x11, 0x82, 0x80, 0x11, 0x47, 0xe3, 0x90,
+ 0xe7, 0xfe, 0xb7, 0xd7, 0x01, 0x24, 0x83, 0xc7, 0x07, 0xfa, 0xe5, 0xd7,
+ 0x97, 0xc0, 0x00, 0xfc, 0xe7, 0x80, 0x40, 0x1f, 0x37, 0x87, 0x02, 0x24,
+ 0x85, 0x46, 0x83, 0x27, 0x84, 0x6e, 0xa3, 0x00, 0xd7, 0x4e, 0x75, 0xbf,
+ 0x23, 0x89, 0x04, 0xb6, 0xe9, 0xb7, 0x01, 0x00, 0x09, 0xe5, 0xb7, 0xa7,
+ 0x01, 0x24, 0xa3, 0x83, 0x07, 0x0c, 0x49, 0xb0, 0x17, 0x33, 0x02, 0xfc,
+ 0xe7, 0x02, 0xe3, 0x08, 0x2a, 0x84, 0x2e, 0x8a, 0x97, 0x50, 0xff, 0xfb,
+ 0xe7, 0x80, 0x40, 0x4c, 0x1d, 0xc5, 0xb7, 0x97, 0x01, 0x24, 0x93, 0x87,
+ 0x07, 0x53, 0x05, 0x67, 0x3e, 0x97, 0x83, 0x46, 0x37, 0xb7, 0x05, 0x47,
+ 0x63, 0x85, 0xe6, 0x00, 0x83, 0xc7, 0x27, 0x41, 0x89, 0xcb, 0xb7, 0x87,
+ 0x02, 0x24, 0x03, 0xc7, 0xb7, 0x4a, 0x85, 0x47, 0xa2, 0x84, 0x63, 0x0f,
+ 0xf7, 0x02, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87, 0x83, 0xa9,
+ 0x87, 0x0a, 0x03, 0xa9, 0xc7, 0x0a, 0x01, 0x46, 0xce, 0x85, 0x4a, 0x85,
+ 0x97, 0x20, 0x01, 0xfc, 0xe7, 0x80, 0x40, 0x5d, 0xd2, 0x85, 0x22, 0x85,
+ 0x97, 0x80, 0x01, 0xfc, 0xe7, 0x80, 0x40, 0x1a, 0xaa, 0x84, 0x05, 0x46,
+ 0xce, 0x85, 0x4a, 0x85, 0x97, 0x20, 0x01, 0xfc, 0xe7, 0x80, 0x80, 0x5b,
+ 0x26, 0x85, 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0x43, 0x04, 0x01, 0x00,
+ 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0x03, 0x02, 0x97, 0x50, 0xff, 0xfb,
+ 0xe7, 0x80, 0x00, 0x44, 0x09, 0xcd, 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80,
+ 0x60, 0x46, 0x01, 0xe9, 0xb7, 0xa7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x53,
+ 0x83, 0xa7, 0x47, 0xb2, 0x95, 0xef, 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80,
+ 0xe0, 0x41, 0x0d, 0xed, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87,
+ 0x84, 0x57, 0xc0, 0x57, 0x01, 0x46, 0xa6, 0x85, 0x22, 0x85, 0x97, 0x20,
+ 0x01, 0xfc, 0xe7, 0x80, 0xe0, 0x55, 0x97, 0x50, 0x00, 0xfc, 0xe7, 0x80,
+ 0xa0, 0xd7, 0x05, 0x46, 0xa6, 0x85, 0x22, 0x85, 0x97, 0x20, 0x01, 0xfc,
+ 0xe7, 0x80, 0x80, 0x54, 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0x03, 0xfe,
+ 0x97, 0x50, 0xff, 0xfb, 0xe7, 0x80, 0xc0, 0x40, 0x61, 0xf1, 0x97, 0x60,
+ 0x01, 0xfc, 0xe7, 0x80, 0x60, 0xd7, 0xb7, 0xd7, 0x01, 0x24, 0x03, 0xd4,
+ 0x07, 0xed, 0xaa, 0x84, 0x97, 0xc0, 0x01, 0xfc, 0xe7, 0x80, 0x00, 0x51,
+ 0x33, 0x14, 0xa4, 0x00, 0x97, 0xc0, 0x01, 0xfc, 0xe7, 0x80, 0x00, 0x52,
+ 0x33, 0x54, 0xa4, 0x40, 0xe3, 0xfa, 0x84, 0xf8, 0xc1, 0xb7, 0x01, 0x00,
+ 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0xe3, 0xf5, 0x37, 0x84, 0x02, 0x24,
+ 0x13, 0x04, 0xc4, 0x49, 0x83, 0x57, 0x04, 0x00, 0xaa, 0x84, 0x2e, 0x89,
+ 0x91, 0xcf, 0x19, 0xe9, 0xb7, 0xa9, 0x01, 0x24, 0x93, 0x89, 0x09, 0x53,
+ 0x03, 0xc7, 0x09, 0xd0, 0x83, 0xc7, 0x19, 0xd0, 0x63, 0x08, 0xf7, 0x06,
+ 0xef, 0xc0, 0x9f, 0xaf, 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87,
+ 0x03, 0xaa, 0x07, 0x02, 0x83, 0xa9, 0x47, 0x02, 0x01, 0x46, 0xd2, 0x85,
+ 0x4e, 0x85, 0x97, 0x20, 0x01, 0xfc, 0xe7, 0x80, 0x20, 0x4b, 0xca, 0x85,
+ 0x26, 0x85, 0x97, 0xb0, 0x00, 0xfc, 0xe7, 0x80, 0xa0, 0x1a, 0x2a, 0x89,
+ 0x05, 0x46, 0xd2, 0x85, 0x4e, 0x85, 0x97, 0x20, 0x01, 0xfc, 0xe7, 0x80,
+ 0x60, 0x49, 0x83, 0x57, 0x04, 0x00, 0x85, 0xc3, 0x99, 0xe8, 0xb7, 0xa9,
+ 0x01, 0x24, 0x93, 0x89, 0x09, 0x53, 0x03, 0xc7, 0x09, 0xd0, 0x83, 0xc7,
+ 0x19, 0xd0, 0x63, 0x06, 0xf7, 0x00, 0x97, 0x70, 0x01, 0xfc, 0xe7, 0x80,
+ 0xe0, 0xda, 0x4a, 0x85, 0x17, 0x33, 0x02, 0xfc, 0x67, 0x00, 0xe3, 0xef,
+ 0xb7, 0xe7, 0x01, 0x24, 0x93, 0x87, 0x07, 0x87, 0x03, 0xaa, 0x07, 0x02,
+ 0xc4, 0x53, 0x01, 0x46, 0xd2, 0x85, 0x26, 0x85, 0x97, 0x20, 0x01, 0xfc,
+ 0xe7, 0x80, 0xc0, 0x44, 0xca, 0x85, 0x01, 0x45, 0x97, 0xb0, 0x00, 0xfc,
+ 0xe7, 0x80, 0x40, 0x14, 0x2a, 0x89, 0x05, 0x46, 0xd2, 0x85, 0x26, 0x85,
+ 0x97, 0x20, 0x01, 0xfc, 0xe7, 0x80, 0x00, 0x43, 0x83, 0x57, 0x04, 0x00,
+ 0xcd, 0xdf, 0x55, 0xb7, 0xb7, 0xc7, 0x02, 0x24, 0x83, 0xc6, 0x07, 0x39,
+ 0x37, 0xd7, 0x01, 0x24, 0xb7, 0x67, 0x01, 0x24, 0x23, 0x28, 0xd7, 0xda,
+ 0x37, 0xc7, 0x02, 0x24, 0x93, 0x87, 0x07, 0x40, 0x13, 0x07, 0x87, 0x39,
+ 0x98, 0xd7, 0x37, 0xc7, 0x02, 0x24, 0x13, 0x07, 0xc7, 0x40, 0xd8, 0xc7,
+ 0x82, 0x80, 0x01, 0x00, 0x17, 0x33, 0x02, 0xfc, 0xe7, 0x02, 0xc3, 0xe6,
+ 0xb7, 0xc6, 0x02, 0x24, 0xb7, 0x87, 0x03, 0x24, 0x93, 0x86, 0x06, 0x6b,
+ 0x37, 0xa7, 0x01, 0x24, 0x93, 0x87, 0x07, 0xff, 0x13, 0x07, 0x07, 0x53,
+ 0x95, 0x8f, 0x23, 0x2c, 0xd7, 0xb4, 0x23, 0x2e, 0xf7, 0xb4, 0x97, 0x20,
+ 0x01, 0xfc, 0xe7, 0x80, 0x20, 0xe0, 0x19, 0xc5, 0xef, 0xd0, 0xdf, 0xd3,
+ 0xef, 0xf0, 0x0f, 0xc4, 0x61, 0x39, 0x49, 0x3f, 0x17, 0x33, 0x02, 0xfc,
+ 0x67, 0x00, 0x03, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x10, 0xe5, 0x38,
+ 0x00, 0x00, 0x00, 0x00, 0xbe, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+static const u8 s5kjn5_data_a548[] = {
+ 0x00, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f,
+ 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
+};
+
+static const u8 s5kjn5_data_bb84[] = {
+ 0x00, 0xab, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x10, 0x00,
+ 0x20, 0x00, 0x9a, 0x00, 0x9a, 0x00, 0x9a, 0x00, 0x9a, 0x00, 0x96, 0x00,
+ 0x96, 0x00, 0x96, 0x00, 0x96, 0x00, 0x93, 0x00, 0x93, 0x00, 0x93, 0x00,
+ 0x93, 0x00, 0x90, 0x00, 0x90, 0x00, 0x90, 0x00, 0x90, 0x00, 0x8d, 0x00,
+ 0x8d, 0x00, 0x8d, 0x00, 0x8d, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00,
+ 0x3f, 0x00, 0x1e, 0x00, 0x1e, 0x00, 0x1e, 0x00, 0x1e, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0x00,
+ 0x3f, 0x00, 0x3f, 0x00, 0x3f, 0x00, 0x34, 0x00, 0x34, 0x00, 0x34, 0x00,
+ 0x34, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x10, 0x00,
+ 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00,
+ 0x06, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00,
+ 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00,
+ 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x06, 0x00, 0x06, 0x00, 0x06, 0x00,
+ 0x06, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x1c, 0x00, 0x06, 0x00,
+ 0x06, 0x00, 0x06, 0x00, 0x06, 0x00, 0x2a, 0x00, 0x2a, 0x00, 0x2a, 0x00,
+ 0x2a, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, 0x10, 0x00,
+ 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x0e, 0x00, 0x0e, 0x00, 0x0e, 0x00,
+ 0x0e, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x18, 0x00,
+ 0x18, 0x00, 0x18, 0x00, 0x18, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00,
+ 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00,
+ 0x24, 0x00, 0x24, 0x00, 0x24, 0x00, 0x00, 0x4d,
+};
+
+static const u8 s5kjn5_data_5634[] = {
+ 0x04, 0x1d, 0x04, 0x20, 0x3c, 0x85, 0x02, 0x24, 0x3c, 0xe6, 0x03, 0x20,
+ 0xd8, 0x85, 0x02, 0x24, 0xd0, 0x6e, 0x03, 0x20, 0xc4, 0x8d, 0x02, 0x24,
+ 0x48, 0x77, 0x03, 0x20, 0x48, 0xc5, 0x02, 0x24, 0x68, 0x12, 0x03, 0x20,
+ 0xa0, 0xc4, 0x02, 0x24, 0xe8, 0xfe, 0x02, 0x20, 0x54, 0x91, 0x02, 0x24,
+ 0xa4, 0x62, 0x03, 0x20, 0x9c, 0x95, 0x02, 0x24, 0x90, 0x1b, 0x00, 0x20,
+ 0x28, 0x96, 0x02, 0x24, 0xc4, 0x46, 0x03, 0x20, 0xe8, 0x96, 0x02, 0x24,
+ 0x14, 0x27, 0x03, 0x20, 0xc4, 0x98, 0x02, 0x24, 0x30, 0x4c, 0x02, 0x20,
+ 0x74, 0x9b, 0x02, 0x24, 0xc8, 0x2c, 0x02, 0x20, 0xd0, 0x9b, 0x02, 0x24,
+ 0x48, 0x4f, 0x02, 0x20, 0x28, 0x9c, 0x02, 0x24, 0xb0, 0x41, 0x02, 0x20,
+ 0x3c, 0x9a, 0x02, 0x24, 0xc8, 0x1d, 0x04, 0x20, 0xfc, 0x9a, 0x02, 0x24,
+ 0xac, 0x7f, 0x04, 0x20, 0x8c, 0x86, 0x02, 0x24, 0x7c, 0x80, 0x04, 0x20,
+ 0x10, 0x86, 0x02, 0x24, 0xf8, 0x87, 0x03, 0x20, 0x7c, 0xac, 0x02, 0x24,
+ 0x10, 0x07, 0x03, 0x20, 0xe0, 0x8e, 0x02, 0x24, 0x14, 0x09, 0x00, 0x20,
+ 0x24, 0x95, 0x02, 0x24, 0x20, 0x46, 0x04, 0x20, 0x18, 0xc4, 0x02, 0x24,
+ 0xb0, 0x5b, 0x04, 0x20, 0x40, 0x88, 0x02, 0x24, 0x50, 0x5c, 0x03, 0x20,
+ 0x44, 0x8a, 0x02, 0x24, 0xa4, 0x5b, 0x03, 0x20, 0x50, 0x89, 0x02, 0x24,
+ 0x30, 0x6a, 0x04, 0x20, 0x14, 0x85, 0x02, 0x24, 0x90, 0xf8, 0x02, 0x20,
+ 0x44, 0xa1, 0x02, 0x24, 0x04, 0x54, 0x01, 0x20, 0x18, 0xa6, 0x02, 0x24,
+ 0x04, 0x53, 0x00, 0x20, 0xa0, 0xa7, 0x02, 0x24, 0xc8, 0x50, 0x02, 0x20,
+ 0xb8, 0xac, 0x02, 0x24, 0x2c, 0x88, 0x02, 0x20, 0xf0, 0xad, 0x02, 0x24,
+ 0x7c, 0x82, 0x01, 0x20, 0xc8, 0xb4, 0x02, 0x24, 0xac, 0xf3, 0x03, 0x20,
+ 0x64, 0xb5, 0x02, 0x24, 0x10, 0x81, 0x03, 0x20, 0x70, 0xb9, 0x02, 0x24,
+ 0xbc, 0xfd, 0x02, 0x20, 0xe4, 0xb9, 0x02, 0x24, 0xbc, 0xa5, 0x04, 0x20,
+ 0x7c, 0xba, 0x02, 0x24, 0xb8, 0x03, 0x03, 0x20, 0xe4, 0xbc, 0x02, 0x24,
+ 0x84, 0x24, 0x02, 0x20, 0xb0, 0xbd, 0x02, 0x24, 0x9c, 0x4c, 0x02, 0x20,
+ 0xd0, 0xbf, 0x02, 0x24, 0x0c, 0x22, 0x02, 0x20, 0x54, 0xbe, 0x02, 0x24,
+};
+
+static const u8 s5kjn5_data_bb8a[] = {
+ 0x01, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0xc8, 0x00, 0xc8, 0x00,
+ 0xc8, 0x00, 0xc8, 0x00, 0xc4, 0x00, 0xc4, 0x00, 0xc4, 0x00, 0xc4, 0x00,
+ 0xc2, 0x00, 0xc2, 0x00, 0xc2, 0x00, 0xc2, 0x00, 0xbe, 0x00, 0xbe, 0x00,
+ 0xbe, 0x00, 0xbe, 0x00, 0xbc, 0x00, 0xbc, 0x00, 0xbc, 0x00, 0xbc, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x16, 0x00, 0x16, 0x00,
+ 0x16, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x14, 0x00, 0x14, 0x00,
+ 0x14, 0x00, 0x14, 0x00, 0x2a, 0x00, 0x2a, 0x00, 0x2a, 0x00, 0x2a, 0x00,
+ 0x2a, 0x00, 0x2a, 0x00, 0x2a, 0x00, 0x2a, 0x00, 0x01, 0x00, 0x01, 0x00,
+ 0x01, 0x00, 0x01, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x0f, 0x00,
+ 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, 0x19, 0x00, 0x19, 0x00,
+ 0x19, 0x00, 0x19, 0x00, 0x14, 0x00, 0x14, 0x00, 0x14, 0x00, 0x14, 0x00,
+ 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x3a, 0x00, 0x0a, 0x00, 0x0a, 0x00,
+ 0x0a, 0x00, 0x0a, 0x00, 0x4b, 0x00, 0x4b, 0x00, 0x4b, 0x00, 0x4b, 0x00,
+ 0x02, 0x00, 0x06, 0x00, 0x0c, 0x00, 0x0c, 0x00, 0x2a, 0x00, 0x25, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x10, 0x00, 0x23, 0x00, 0x23, 0x00,
+ 0x3f, 0x00, 0x31, 0x00, 0x21, 0x00, 0x21, 0x00, 0x0a, 0x00, 0x1b, 0x00,
+ 0x30, 0x00, 0x30, 0x00, 0x19, 0x00, 0x15, 0x00, 0x11, 0x00, 0x11, 0x00,
+ 0x0f, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x19, 0x00, 0x19, 0x00,
+ 0x19, 0x00, 0x19, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x0a, 0x00,
+ 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00,
+};
+
+struct s5kjn5_init_op {
+ u32 reg;
+ u64 val;
+ const u8 *burst;
+ u16 burst_addr;
+ u16 burst_len;
+ u16 delay_us;
+};
+
+static const struct s5kjn5_init_op s5kjn5_init_ops[] = {
+ { .reg = CCI_REG16(0xfcfc), .val = 0x4000 },
+ { .reg = CCI_REG16(0x0000), .val = 0x000e },
+ { .reg = CCI_REG16(0x0000), .val = 0x38e5 },
+ { .reg = CCI_REG16(0x6018), .val = 0x0001 },
+ { .reg = CCI_REG16(0x7002), .val = 0x0408 },
+ { .reg = CCI_REG16(0x6014), .val = 0x0001 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2002 },
+ { .reg = CCI_REG16(0x1e92), .val = 0x8000 },
+ { .reg = CCI_REG8(0x1e84), .val = 0x28 },
+ { .reg = CCI_REG8(0x1e85), .val = 0x2b },
+ { .reg = CCI_REG8(0x1e86), .val = 0x03 },
+ { .reg = CCI_REG8(0x1e87), .val = 0x20 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x4000 },
+ { .reg = CCI_REG16(0x7002), .val = 0x0008 },
+ { .delay_us = 5000 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2000 },
+ { .reg = CCI_REG16(0xdcf0), .val = 0x0000 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2001 },
+ { .reg = CCI_REG16(0x3c60), .val = 0x0000 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2002 },
+ { .burst = s5kjn5_data_a614, .burst_addr = 0xa614,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_a614) },
+ { .burst = s5kjn5_data_bc98, .burst_addr = 0xbc98,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_bc98) },
+ { .burst = s5kjn5_data_c398, .burst_addr = 0xc398,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_c398) },
+ { .reg = CCI_REG8(0x849c), .val = 0x01 },
+ { .reg = CCI_REG8(0x849d), .val = 0x00 },
+ { .reg = CCI_REG8(0x849e), .val = 0x00 },
+ { .reg = CCI_REG8(0x849f), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a0), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a1), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a2), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a3), .val = 0x05 },
+ { .reg = CCI_REG8(0x84a4), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a5), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a6), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a7), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a8), .val = 0x00 },
+ { .reg = CCI_REG8(0x84a9), .val = 0x00 },
+ { .reg = CCI_REG8(0x84aa), .val = 0x00 },
+ { .reg = CCI_REG8(0x84ab), .val = 0x01 },
+ { .reg = CCI_REG8(0x84ac), .val = 0x01 },
+ { .reg = CCI_REG8(0x84ad), .val = 0xff },
+ { .reg = CCI_REG8(0x84b0), .val = 0x80 },
+ { .reg = CCI_REG8(0x84b1), .val = 0x89 },
+ { .reg = CCI_REG8(0x84b2), .val = 0x00 },
+ { .reg = CCI_REG8(0x84b3), .val = 0x00 },
+ { .reg = CCI_REG8(0x84b4), .val = 0x88 },
+ { .reg = CCI_REG8(0x84b5), .val = 0x89 },
+ { .reg = CCI_REG8(0x84b6), .val = 0x00 },
+ { .reg = CCI_REG8(0x84b7), .val = 0x00 },
+ { .reg = CCI_REG8(0x84b8), .val = 0xc0 },
+ { .reg = CCI_REG8(0x84b9), .val = 0x97 },
+ { .reg = CCI_REG8(0x84ba), .val = 0x00 },
+ { .reg = CCI_REG8(0x84bb), .val = 0x00 },
+ { .reg = CCI_REG8(0x84bc), .val = 0xa6 },
+ { .reg = CCI_REG8(0x84bd), .val = 0x0e },
+ { .reg = CCI_REG8(0x84be), .val = 0x00 },
+ { .reg = CCI_REG8(0x84bf), .val = 0x00 },
+ { .reg = CCI_REG8(0x84c0), .val = 0x22 },
+ { .reg = CCI_REG8(0x84c1), .val = 0x06 },
+ { .reg = CCI_REG8(0x84c2), .val = 0x00 },
+ { .reg = CCI_REG8(0x84c3), .val = 0x00 },
+ { .reg = CCI_REG8(0x84c4), .val = 0x00 },
+ { .reg = CCI_REG8(0x84c5), .val = 0x2d },
+ { .reg = CCI_REG8(0x84c8), .val = 0x54 },
+ { .reg = CCI_REG8(0x84c9), .val = 0xc6 },
+ { .reg = CCI_REG8(0x84ca), .val = 0x02 },
+ { .reg = CCI_REG8(0x84cb), .val = 0x24 },
+ { .reg = CCI_REG8(0x84cc), .val = 0x44 },
+ { .reg = CCI_REG8(0x84cd), .val = 0xab },
+ { .reg = CCI_REG8(0x84ce), .val = 0x02 },
+ { .reg = CCI_REG8(0x84cf), .val = 0x24 },
+ { .reg = CCI_REG8(0x84d0), .val = 0x44 },
+ { .reg = CCI_REG8(0x84d1), .val = 0xab },
+ { .reg = CCI_REG8(0x84d2), .val = 0x02 },
+ { .reg = CCI_REG8(0x84d3), .val = 0x24 },
+ { .reg = CCI_REG8(0x84d4), .val = 0x44 },
+ { .reg = CCI_REG8(0x84d5), .val = 0xab },
+ { .reg = CCI_REG8(0x84d6), .val = 0x02 },
+ { .reg = CCI_REG8(0x84d7), .val = 0x24 },
+ { .reg = CCI_REG8(0x84d8), .val = 0x44 },
+ { .reg = CCI_REG8(0x84d9), .val = 0xab },
+ { .reg = CCI_REG8(0x84da), .val = 0x02 },
+ { .reg = CCI_REG8(0x84db), .val = 0x24 },
+ { .reg = CCI_REG8(0x84dc), .val = 0x44 },
+ { .reg = CCI_REG8(0x84dd), .val = 0xab },
+ { .reg = CCI_REG8(0x84de), .val = 0x02 },
+ { .reg = CCI_REG8(0x84df), .val = 0x24 },
+ { .burst = s5kjn5_data_a548, .burst_addr = 0xa548,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_a548) },
+ { .burst = s5kjn5_data_bb84, .burst_addr = 0xbb84,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_bb84) },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2001 },
+ { .burst = s5kjn5_data_5634, .burst_addr = 0x5634,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_5634) },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2000 },
+ { .reg = CCI_REG8(0x2366), .val = 0x00 },
+ { .reg = CCI_REG8(0x2367), .val = 0x1c },
+ { .reg = CCI_REG8(0x2368), .val = 0x00 },
+ { .reg = CCI_REG8(0x2369), .val = 0x1c },
+ { .reg = CCI_REG16(0x238e), .val = 0x3f28 },
+ { .reg = CCI_REG16(0x2398), .val = 0x5037 },
+ { .reg = CCI_REG16(0x24b8), .val = 0x0101 },
+ { .reg = CCI_REG8(0x66e4), .val = 0x1e },
+ { .reg = CCI_REG8(0x66e5), .val = 0x8d },
+ { .reg = CCI_REG8(0x66e6), .val = 0x00 },
+ { .reg = CCI_REG8(0x66e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x6874), .val = 0x00 },
+ { .reg = CCI_REG8(0x6875), .val = 0x00 },
+ { .reg = CCI_REG8(0x6876), .val = 0x00 },
+ { .reg = CCI_REG8(0x6877), .val = 0x00 },
+ { .reg = CCI_REG8(0x6878), .val = 0x00 },
+ { .reg = CCI_REG8(0x6879), .val = 0x00 },
+ { .reg = CCI_REG8(0x687a), .val = 0x00 },
+ { .reg = CCI_REG8(0x687b), .val = 0x00 },
+ { .reg = CCI_REG8(0x6884), .val = 0x01 },
+ { .reg = CCI_REG8(0x6885), .val = 0x00 },
+ { .reg = CCI_REG8(0x6886), .val = 0x01 },
+ { .reg = CCI_REG8(0x6887), .val = 0x00 },
+ { .reg = CCI_REG8(0x6888), .val = 0x01 },
+ { .reg = CCI_REG8(0x6889), .val = 0x00 },
+ { .reg = CCI_REG8(0x688a), .val = 0x01 },
+ { .reg = CCI_REG8(0x688b), .val = 0x00 },
+ { .reg = CCI_REG16(0x77d2), .val = 0x0000 },
+ { .reg = CCI_REG16(0x780a), .val = 0x0000 },
+ { .reg = CCI_REG8(0x793e), .val = 0x01 },
+ { .reg = CCI_REG8(0x793f), .val = 0x00 },
+ { .reg = CCI_REG8(0x7940), .val = 0x70 },
+ { .reg = CCI_REG8(0x7941), .val = 0x17 },
+ { .reg = CCI_REG8(0x795c), .val = 0x04 },
+ { .reg = CCI_REG8(0x795d), .val = 0x00 },
+ { .reg = CCI_REG8(0x795e), .val = 0x04 },
+ { .reg = CCI_REG8(0x795f), .val = 0x00 },
+ { .reg = CCI_REG8(0x7960), .val = 0x08 },
+ { .reg = CCI_REG8(0x7961), .val = 0x00 },
+ { .reg = CCI_REG8(0x7962), .val = 0x10 },
+ { .reg = CCI_REG8(0x7963), .val = 0x00 },
+ { .reg = CCI_REG8(0x7964), .val = 0x08 },
+ { .reg = CCI_REG8(0x7965), .val = 0x00 },
+ { .reg = CCI_REG8(0x7966), .val = 0x10 },
+ { .reg = CCI_REG8(0x7967), .val = 0x00 },
+ { .reg = CCI_REG8(0x7968), .val = 0x08 },
+ { .reg = CCI_REG8(0x7969), .val = 0x00 },
+ { .reg = CCI_REG8(0x796a), .val = 0x08 },
+ { .reg = CCI_REG8(0x796b), .val = 0x00 },
+ { .reg = CCI_REG8(0x796c), .val = 0x08 },
+ { .reg = CCI_REG8(0x796d), .val = 0x00 },
+ { .reg = CCI_REG8(0x796e), .val = 0x08 },
+ { .reg = CCI_REG8(0x796f), .val = 0x00 },
+ { .reg = CCI_REG8(0x7972), .val = 0x04 },
+ { .reg = CCI_REG8(0x7973), .val = 0x00 },
+ { .reg = CCI_REG8(0x7974), .val = 0x04 },
+ { .reg = CCI_REG8(0x7975), .val = 0x00 },
+ { .reg = CCI_REG8(0x7976), .val = 0x08 },
+ { .reg = CCI_REG8(0x7977), .val = 0x00 },
+ { .reg = CCI_REG8(0x7978), .val = 0x10 },
+ { .reg = CCI_REG8(0x7979), .val = 0x00 },
+ { .reg = CCI_REG8(0x797a), .val = 0x08 },
+ { .reg = CCI_REG8(0x797b), .val = 0x00 },
+ { .reg = CCI_REG8(0x797c), .val = 0x10 },
+ { .reg = CCI_REG8(0x797d), .val = 0x00 },
+ { .reg = CCI_REG8(0x797e), .val = 0x08 },
+ { .reg = CCI_REG8(0x797f), .val = 0x00 },
+ { .reg = CCI_REG8(0x7980), .val = 0x08 },
+ { .reg = CCI_REG8(0x7981), .val = 0x00 },
+ { .reg = CCI_REG8(0x7982), .val = 0x08 },
+ { .reg = CCI_REG8(0x7983), .val = 0x00 },
+ { .reg = CCI_REG8(0x7984), .val = 0x08 },
+ { .reg = CCI_REG8(0x7985), .val = 0x00 },
+ { .reg = CCI_REG16(0xb3ac), .val = 0x4000 },
+ { .reg = CCI_REG16(0xb3b4), .val = 0x2000 },
+ { .reg = CCI_REG16(0xb3b8), .val = 0x1000 },
+ { .reg = CCI_REG16(0xb3f8), .val = 0x8000 },
+ { .reg = CCI_REG16(0xb400), .val = 0x4000 },
+ { .reg = CCI_REG16(0xb404), .val = 0x2000 },
+ { .reg = CCI_REG16(0xbf70), .val = 0x3a46 },
+ { .reg = CCI_REG16(0xbf7c), .val = 0x0800 },
+ { .reg = CCI_REG16(0xc4a8), .val = 0x0000 },
+ { .reg = CCI_REG8(0xc4f8), .val = 0x00 },
+ { .reg = CCI_REG8(0xc4f9), .val = 0xa8 },
+ { .reg = CCI_REG8(0xc4fa), .val = 0x00 },
+ { .reg = CCI_REG8(0xc4fb), .val = 0x00 },
+ { .reg = CCI_REG16(0xd3da), .val = 0x0d00 },
+ { .reg = CCI_REG8(0xd3e0), .val = 0x0d },
+ { .reg = CCI_REG8(0xd3e1), .val = 0x00 },
+ { .reg = CCI_REG8(0xd3e2), .val = 0x0d },
+ { .reg = CCI_REG8(0xd3e3), .val = 0x00 },
+ { .reg = CCI_REG8(0xd3e4), .val = 0x0d },
+ { .reg = CCI_REG8(0xd3e5), .val = 0x00 },
+ { .reg = CCI_REG8(0xd3e6), .val = 0x0d },
+ { .reg = CCI_REG8(0xd3e7), .val = 0x00 },
+ { .reg = CCI_REG16(0xd3ea), .val = 0x0d00 },
+ { .reg = CCI_REG16(0xd3f4), .val = 0x301c },
+ { .reg = CCI_REG16(0xd3f8), .val = 0x301c },
+ { .reg = CCI_REG8(0xdd6c), .val = 0xb4 },
+ { .reg = CCI_REG8(0xdd6d), .val = 0x7e },
+ { .reg = CCI_REG8(0xdd6e), .val = 0xb6 },
+ { .reg = CCI_REG8(0xdd6f), .val = 0x7e },
+ { .reg = CCI_REG8(0xde34), .val = 0x00 },
+ { .reg = CCI_REG8(0xde35), .val = 0x00 },
+ { .reg = CCI_REG8(0xde36), .val = 0x92 },
+ { .reg = CCI_REG8(0xde37), .val = 0x31 },
+ { .reg = CCI_REG8(0xec42), .val = 0x01 },
+ { .reg = CCI_REG8(0xec43), .val = 0x00 },
+ { .reg = CCI_REG8(0xec44), .val = 0x01 },
+ { .reg = CCI_REG8(0xec45), .val = 0x00 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2001 },
+ { .reg = CCI_REG8(0x2542), .val = 0x20 },
+ { .reg = CCI_REG8(0x2543), .val = 0x20 },
+ { .reg = CCI_REG8(0x2544), .val = 0x20 },
+ { .reg = CCI_REG8(0x2545), .val = 0x18 },
+ { .reg = CCI_REG8(0x2554), .val = 0x00 },
+ { .reg = CCI_REG8(0x2555), .val = 0x00 },
+ { .reg = CCI_REG8(0x2556), .val = 0x00 },
+ { .reg = CCI_REG8(0x2557), .val = 0x00 },
+ { .reg = CCI_REG16(0x256e), .val = 0x0000 },
+ { .reg = CCI_REG16(0x25d2), .val = 0x0102 },
+ { .reg = CCI_REG16(0x2936), .val = 0x4400 },
+ { .reg = CCI_REG8(0x2a14), .val = 0x00 },
+ { .reg = CCI_REG8(0x2a15), .val = 0x02 },
+ { .reg = CCI_REG8(0x2a16), .val = 0xdf },
+ { .reg = CCI_REG8(0x2a17), .val = 0x03 },
+ { .reg = CCI_REG8(0x2a18), .val = 0x00 },
+ { .reg = CCI_REG8(0x2a19), .val = 0x02 },
+ { .reg = CCI_REG8(0x2a1a), .val = 0x00 },
+ { .reg = CCI_REG8(0x2a1b), .val = 0x02 },
+ { .reg = CCI_REG8(0x3252), .val = 0x8c },
+ { .reg = CCI_REG8(0x3253), .val = 0x00 },
+ { .reg = CCI_REG8(0x3254), .val = 0x8c },
+ { .reg = CCI_REG8(0x3255), .val = 0x00 },
+ { .reg = CCI_REG8(0x3256), .val = 0x8c },
+ { .reg = CCI_REG8(0x3257), .val = 0x00 },
+ { .reg = CCI_REG8(0x3258), .val = 0x87 },
+ { .reg = CCI_REG8(0x3259), .val = 0x00 },
+ { .reg = CCI_REG8(0x325a), .val = 0x82 },
+ { .reg = CCI_REG8(0x325b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3e1c), .val = 0x02 },
+ { .reg = CCI_REG8(0x3e1d), .val = 0x00 },
+ { .reg = CCI_REG8(0x3e1e), .val = 0x20 },
+ { .reg = CCI_REG8(0x3e1f), .val = 0x00 },
+ { .reg = CCI_REG16(0x5acc), .val = 0x6505 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x4000 },
+ { .reg = CCI_REG16(0x1858), .val = 0x123f },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2001 },
+ { .reg = CCI_REG16(0x3eb8), .val = 0x00ff },
+ { .reg = CCI_REG16(0x3ecc), .val = 0xfe03 },
+ { .reg = CCI_REG16(0x3f12), .val = 0x9001 },
+ { .reg = CCI_REG8(0x33e0), .val = 0x1e },
+ { .reg = CCI_REG8(0x33e1), .val = 0x00 },
+ { .reg = CCI_REG8(0x33e2), .val = 0x1e },
+ { .reg = CCI_REG8(0x33e3), .val = 0x00 },
+ { .reg = CCI_REG8(0x33e4), .val = 0x1e },
+ { .reg = CCI_REG8(0x33e5), .val = 0x00 },
+ { .reg = CCI_REG8(0x33e6), .val = 0x1e },
+ { .reg = CCI_REG8(0x33e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x33e8), .val = 0x1e },
+ { .reg = CCI_REG8(0x33e9), .val = 0x00 },
+ { .reg = CCI_REG8(0x33ea), .val = 0x1e },
+ { .reg = CCI_REG8(0x33eb), .val = 0x00 },
+ { .reg = CCI_REG8(0x3440), .val = 0x05 },
+ { .reg = CCI_REG8(0x3441), .val = 0x00 },
+ { .reg = CCI_REG8(0x3442), .val = 0x05 },
+ { .reg = CCI_REG8(0x3443), .val = 0x00 },
+ { .reg = CCI_REG8(0x3444), .val = 0x05 },
+ { .reg = CCI_REG8(0x3445), .val = 0x00 },
+ { .reg = CCI_REG8(0x3446), .val = 0x05 },
+ { .reg = CCI_REG8(0x3447), .val = 0x00 },
+ { .reg = CCI_REG8(0x3448), .val = 0x05 },
+ { .reg = CCI_REG8(0x3449), .val = 0x00 },
+ { .reg = CCI_REG8(0x344a), .val = 0x05 },
+ { .reg = CCI_REG8(0x344b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3450), .val = 0x0a },
+ { .reg = CCI_REG8(0x3451), .val = 0x00 },
+ { .reg = CCI_REG8(0x3452), .val = 0x0a },
+ { .reg = CCI_REG8(0x3453), .val = 0x00 },
+ { .reg = CCI_REG8(0x3454), .val = 0x0a },
+ { .reg = CCI_REG8(0x3455), .val = 0x00 },
+ { .reg = CCI_REG8(0x3456), .val = 0x0a },
+ { .reg = CCI_REG8(0x3457), .val = 0x00 },
+ { .reg = CCI_REG8(0x3458), .val = 0x0a },
+ { .reg = CCI_REG8(0x3459), .val = 0x00 },
+ { .reg = CCI_REG8(0x345a), .val = 0x0a },
+ { .reg = CCI_REG8(0x345b), .val = 0x00 },
+ { .reg = CCI_REG8(0x34e0), .val = 0x14 },
+ { .reg = CCI_REG8(0x34e1), .val = 0x00 },
+ { .reg = CCI_REG8(0x34e2), .val = 0x14 },
+ { .reg = CCI_REG8(0x34e3), .val = 0x00 },
+ { .reg = CCI_REG8(0x34e4), .val = 0x14 },
+ { .reg = CCI_REG8(0x34e5), .val = 0x00 },
+ { .reg = CCI_REG8(0x34e6), .val = 0x14 },
+ { .reg = CCI_REG8(0x34e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x34e8), .val = 0x14 },
+ { .reg = CCI_REG8(0x34e9), .val = 0x00 },
+ { .reg = CCI_REG8(0x34ea), .val = 0x14 },
+ { .reg = CCI_REG8(0x34eb), .val = 0x00 },
+ { .reg = CCI_REG8(0x3500), .val = 0x14 },
+ { .reg = CCI_REG8(0x3501), .val = 0x00 },
+ { .reg = CCI_REG8(0x3502), .val = 0x14 },
+ { .reg = CCI_REG8(0x3503), .val = 0x00 },
+ { .reg = CCI_REG8(0x3504), .val = 0x14 },
+ { .reg = CCI_REG8(0x3505), .val = 0x00 },
+ { .reg = CCI_REG8(0x3506), .val = 0x14 },
+ { .reg = CCI_REG8(0x3507), .val = 0x00 },
+ { .reg = CCI_REG8(0x3508), .val = 0x14 },
+ { .reg = CCI_REG8(0x3509), .val = 0x00 },
+ { .reg = CCI_REG8(0x350a), .val = 0x14 },
+ { .reg = CCI_REG8(0x350b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3520), .val = 0x14 },
+ { .reg = CCI_REG8(0x3521), .val = 0x00 },
+ { .reg = CCI_REG8(0x3522), .val = 0x14 },
+ { .reg = CCI_REG8(0x3523), .val = 0x00 },
+ { .reg = CCI_REG8(0x3524), .val = 0x14 },
+ { .reg = CCI_REG8(0x3525), .val = 0x00 },
+ { .reg = CCI_REG8(0x3526), .val = 0x14 },
+ { .reg = CCI_REG8(0x3527), .val = 0x00 },
+ { .reg = CCI_REG8(0x3528), .val = 0x14 },
+ { .reg = CCI_REG8(0x3529), .val = 0x00 },
+ { .reg = CCI_REG8(0x352a), .val = 0x14 },
+ { .reg = CCI_REG8(0x352b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3580), .val = 0x23 },
+ { .reg = CCI_REG8(0x3581), .val = 0x00 },
+ { .reg = CCI_REG8(0x3582), .val = 0x23 },
+ { .reg = CCI_REG8(0x3583), .val = 0x00 },
+ { .reg = CCI_REG8(0x3584), .val = 0x23 },
+ { .reg = CCI_REG8(0x3585), .val = 0x00 },
+ { .reg = CCI_REG8(0x3586), .val = 0x23 },
+ { .reg = CCI_REG8(0x3587), .val = 0x00 },
+ { .reg = CCI_REG8(0x3588), .val = 0x23 },
+ { .reg = CCI_REG8(0x3589), .val = 0x00 },
+ { .reg = CCI_REG8(0x358a), .val = 0x23 },
+ { .reg = CCI_REG8(0x358b), .val = 0x00 },
+ { .reg = CCI_REG8(0x35a0), .val = 0x19 },
+ { .reg = CCI_REG8(0x35a1), .val = 0x00 },
+ { .reg = CCI_REG8(0x35a2), .val = 0x19 },
+ { .reg = CCI_REG8(0x35a3), .val = 0x00 },
+ { .reg = CCI_REG8(0x35a4), .val = 0x19 },
+ { .reg = CCI_REG8(0x35a5), .val = 0x00 },
+ { .reg = CCI_REG8(0x35a6), .val = 0x19 },
+ { .reg = CCI_REG8(0x35a7), .val = 0x00 },
+ { .reg = CCI_REG8(0x35a8), .val = 0x19 },
+ { .reg = CCI_REG8(0x35a9), .val = 0x00 },
+ { .reg = CCI_REG8(0x35aa), .val = 0x19 },
+ { .reg = CCI_REG8(0x35ab), .val = 0x00 },
+ { .reg = CCI_REG8(0x35d0), .val = 0x1e },
+ { .reg = CCI_REG8(0x35d1), .val = 0x00 },
+ { .reg = CCI_REG8(0x35d2), .val = 0x1e },
+ { .reg = CCI_REG8(0x35d3), .val = 0x00 },
+ { .reg = CCI_REG8(0x35d4), .val = 0x1e },
+ { .reg = CCI_REG8(0x35d5), .val = 0x00 },
+ { .reg = CCI_REG8(0x35d6), .val = 0x1e },
+ { .reg = CCI_REG8(0x35d7), .val = 0x00 },
+ { .reg = CCI_REG8(0x35d8), .val = 0x1e },
+ { .reg = CCI_REG8(0x35d9), .val = 0x00 },
+ { .reg = CCI_REG8(0x35da), .val = 0x1e },
+ { .reg = CCI_REG8(0x35db), .val = 0x00 },
+ { .reg = CCI_REG8(0x35e0), .val = 0x1e },
+ { .reg = CCI_REG8(0x35e1), .val = 0x00 },
+ { .reg = CCI_REG8(0x35e2), .val = 0x1e },
+ { .reg = CCI_REG8(0x35e3), .val = 0x00 },
+ { .reg = CCI_REG8(0x35e4), .val = 0x1e },
+ { .reg = CCI_REG8(0x35e5), .val = 0x00 },
+ { .reg = CCI_REG8(0x35e6), .val = 0x1e },
+ { .reg = CCI_REG8(0x35e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x35e8), .val = 0x1e },
+ { .reg = CCI_REG8(0x35e9), .val = 0x00 },
+ { .reg = CCI_REG8(0x35ea), .val = 0x1e },
+ { .reg = CCI_REG8(0x35eb), .val = 0x00 },
+ { .reg = CCI_REG8(0x35f0), .val = 0x1e },
+ { .reg = CCI_REG8(0x35f1), .val = 0x00 },
+ { .reg = CCI_REG8(0x35f2), .val = 0x1e },
+ { .reg = CCI_REG8(0x35f3), .val = 0x00 },
+ { .reg = CCI_REG8(0x35f4), .val = 0x1e },
+ { .reg = CCI_REG8(0x35f5), .val = 0x00 },
+ { .reg = CCI_REG8(0x35f6), .val = 0x1e },
+ { .reg = CCI_REG8(0x35f7), .val = 0x00 },
+ { .reg = CCI_REG8(0x35f8), .val = 0x1e },
+ { .reg = CCI_REG8(0x35f9), .val = 0x00 },
+ { .reg = CCI_REG8(0x35fa), .val = 0x1e },
+ { .reg = CCI_REG8(0x35fb), .val = 0x00 },
+ { .reg = CCI_REG8(0x3600), .val = 0x1e },
+ { .reg = CCI_REG8(0x3601), .val = 0x00 },
+ { .reg = CCI_REG8(0x3602), .val = 0x1e },
+ { .reg = CCI_REG8(0x3603), .val = 0x00 },
+ { .reg = CCI_REG8(0x3604), .val = 0x1e },
+ { .reg = CCI_REG8(0x3605), .val = 0x00 },
+ { .reg = CCI_REG8(0x3606), .val = 0x1e },
+ { .reg = CCI_REG8(0x3607), .val = 0x00 },
+ { .reg = CCI_REG8(0x3608), .val = 0x1e },
+ { .reg = CCI_REG8(0x3609), .val = 0x00 },
+ { .reg = CCI_REG8(0x360a), .val = 0x1e },
+ { .reg = CCI_REG8(0x360b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3610), .val = 0x1e },
+ { .reg = CCI_REG8(0x3611), .val = 0x00 },
+ { .reg = CCI_REG8(0x3612), .val = 0x1e },
+ { .reg = CCI_REG8(0x3613), .val = 0x00 },
+ { .reg = CCI_REG8(0x3614), .val = 0x1e },
+ { .reg = CCI_REG8(0x3615), .val = 0x00 },
+ { .reg = CCI_REG8(0x3616), .val = 0x1e },
+ { .reg = CCI_REG8(0x3617), .val = 0x00 },
+ { .reg = CCI_REG8(0x3618), .val = 0x1e },
+ { .reg = CCI_REG8(0x3619), .val = 0x00 },
+ { .reg = CCI_REG8(0x361a), .val = 0x1e },
+ { .reg = CCI_REG8(0x361b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3620), .val = 0x00 },
+ { .reg = CCI_REG8(0x3621), .val = 0x00 },
+ { .reg = CCI_REG8(0x3622), .val = 0x00 },
+ { .reg = CCI_REG8(0x3623), .val = 0x00 },
+ { .reg = CCI_REG8(0x3624), .val = 0x00 },
+ { .reg = CCI_REG8(0x3625), .val = 0x00 },
+ { .reg = CCI_REG8(0x3626), .val = 0x00 },
+ { .reg = CCI_REG8(0x3627), .val = 0x00 },
+ { .reg = CCI_REG8(0x3628), .val = 0x00 },
+ { .reg = CCI_REG8(0x3629), .val = 0x00 },
+ { .reg = CCI_REG8(0x362a), .val = 0x00 },
+ { .reg = CCI_REG8(0x362b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3630), .val = 0x0a },
+ { .reg = CCI_REG8(0x3631), .val = 0x00 },
+ { .reg = CCI_REG8(0x3632), .val = 0x0a },
+ { .reg = CCI_REG8(0x3633), .val = 0x00 },
+ { .reg = CCI_REG8(0x3634), .val = 0x0a },
+ { .reg = CCI_REG8(0x3635), .val = 0x00 },
+ { .reg = CCI_REG8(0x3636), .val = 0x0a },
+ { .reg = CCI_REG8(0x3637), .val = 0x00 },
+ { .reg = CCI_REG8(0x3638), .val = 0x0a },
+ { .reg = CCI_REG8(0x3639), .val = 0x00 },
+ { .reg = CCI_REG8(0x363a), .val = 0x0a },
+ { .reg = CCI_REG8(0x363b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3650), .val = 0x1e },
+ { .reg = CCI_REG8(0x3651), .val = 0x00 },
+ { .reg = CCI_REG8(0x3652), .val = 0x1e },
+ { .reg = CCI_REG8(0x3653), .val = 0x00 },
+ { .reg = CCI_REG8(0x3654), .val = 0x1e },
+ { .reg = CCI_REG8(0x3655), .val = 0x00 },
+ { .reg = CCI_REG8(0x3656), .val = 0x1e },
+ { .reg = CCI_REG8(0x3657), .val = 0x00 },
+ { .reg = CCI_REG8(0x3658), .val = 0x1e },
+ { .reg = CCI_REG8(0x3659), .val = 0x00 },
+ { .reg = CCI_REG8(0x365a), .val = 0x1e },
+ { .reg = CCI_REG8(0x365b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3660), .val = 0x1e },
+ { .reg = CCI_REG8(0x3661), .val = 0x00 },
+ { .reg = CCI_REG8(0x3662), .val = 0x1e },
+ { .reg = CCI_REG8(0x3663), .val = 0x00 },
+ { .reg = CCI_REG8(0x3664), .val = 0x1e },
+ { .reg = CCI_REG8(0x3665), .val = 0x00 },
+ { .reg = CCI_REG8(0x3666), .val = 0x1e },
+ { .reg = CCI_REG8(0x3667), .val = 0x00 },
+ { .reg = CCI_REG8(0x3668), .val = 0x1e },
+ { .reg = CCI_REG8(0x3669), .val = 0x00 },
+ { .reg = CCI_REG8(0x366a), .val = 0x1e },
+ { .reg = CCI_REG8(0x366b), .val = 0x00 },
+ { .reg = CCI_REG8(0x36a0), .val = 0x64 },
+ { .reg = CCI_REG8(0x36a1), .val = 0x00 },
+ { .reg = CCI_REG8(0x36a2), .val = 0x64 },
+ { .reg = CCI_REG8(0x36a3), .val = 0x00 },
+ { .reg = CCI_REG8(0x36a4), .val = 0x64 },
+ { .reg = CCI_REG8(0x36a5), .val = 0x00 },
+ { .reg = CCI_REG8(0x36a6), .val = 0x64 },
+ { .reg = CCI_REG8(0x36a7), .val = 0x00 },
+ { .reg = CCI_REG8(0x36a8), .val = 0x64 },
+ { .reg = CCI_REG8(0x36a9), .val = 0x00 },
+ { .reg = CCI_REG8(0x36aa), .val = 0x64 },
+ { .reg = CCI_REG8(0x36ab), .val = 0x00 },
+ { .reg = CCI_REG8(0x36c0), .val = 0x8c },
+ { .reg = CCI_REG8(0x36c1), .val = 0x00 },
+ { .reg = CCI_REG8(0x36c2), .val = 0x8c },
+ { .reg = CCI_REG8(0x36c3), .val = 0x00 },
+ { .reg = CCI_REG8(0x36c4), .val = 0x8c },
+ { .reg = CCI_REG8(0x36c5), .val = 0x00 },
+ { .reg = CCI_REG8(0x36c6), .val = 0x8c },
+ { .reg = CCI_REG8(0x36c7), .val = 0x00 },
+ { .reg = CCI_REG8(0x36c8), .val = 0x8c },
+ { .reg = CCI_REG8(0x36c9), .val = 0x00 },
+ { .reg = CCI_REG8(0x36ca), .val = 0x8c },
+ { .reg = CCI_REG8(0x36cb), .val = 0x00 },
+ { .reg = CCI_REG8(0x36e0), .val = 0x64 },
+ { .reg = CCI_REG8(0x36e1), .val = 0x00 },
+ { .reg = CCI_REG8(0x36e2), .val = 0x64 },
+ { .reg = CCI_REG8(0x36e3), .val = 0x00 },
+ { .reg = CCI_REG8(0x36e4), .val = 0x64 },
+ { .reg = CCI_REG8(0x36e5), .val = 0x00 },
+ { .reg = CCI_REG8(0x36e6), .val = 0x64 },
+ { .reg = CCI_REG8(0x36e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x36e8), .val = 0x64 },
+ { .reg = CCI_REG8(0x36e9), .val = 0x00 },
+ { .reg = CCI_REG8(0x36ea), .val = 0x64 },
+ { .reg = CCI_REG8(0x36eb), .val = 0x00 },
+ { .reg = CCI_REG8(0x36f0), .val = 0x32 },
+ { .reg = CCI_REG8(0x36f1), .val = 0x00 },
+ { .reg = CCI_REG8(0x36f2), .val = 0x32 },
+ { .reg = CCI_REG8(0x36f3), .val = 0x00 },
+ { .reg = CCI_REG8(0x36f4), .val = 0x32 },
+ { .reg = CCI_REG8(0x36f5), .val = 0x00 },
+ { .reg = CCI_REG8(0x36f6), .val = 0x32 },
+ { .reg = CCI_REG8(0x36f7), .val = 0x00 },
+ { .reg = CCI_REG8(0x36f8), .val = 0x32 },
+ { .reg = CCI_REG8(0x36f9), .val = 0x00 },
+ { .reg = CCI_REG8(0x36fa), .val = 0x32 },
+ { .reg = CCI_REG8(0x36fb), .val = 0x00 },
+ { .reg = CCI_REG8(0x3700), .val = 0x32 },
+ { .reg = CCI_REG8(0x3701), .val = 0x00 },
+ { .reg = CCI_REG8(0x3702), .val = 0x32 },
+ { .reg = CCI_REG8(0x3703), .val = 0x00 },
+ { .reg = CCI_REG8(0x3704), .val = 0x32 },
+ { .reg = CCI_REG8(0x3705), .val = 0x00 },
+ { .reg = CCI_REG8(0x3706), .val = 0x32 },
+ { .reg = CCI_REG8(0x3707), .val = 0x00 },
+ { .reg = CCI_REG8(0x3708), .val = 0x32 },
+ { .reg = CCI_REG8(0x3709), .val = 0x00 },
+ { .reg = CCI_REG8(0x370a), .val = 0x32 },
+ { .reg = CCI_REG8(0x370b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3720), .val = 0x32 },
+ { .reg = CCI_REG8(0x3721), .val = 0x00 },
+ { .reg = CCI_REG8(0x3722), .val = 0x32 },
+ { .reg = CCI_REG8(0x3723), .val = 0x00 },
+ { .reg = CCI_REG8(0x3724), .val = 0x32 },
+ { .reg = CCI_REG8(0x3725), .val = 0x00 },
+ { .reg = CCI_REG8(0x3726), .val = 0x32 },
+ { .reg = CCI_REG8(0x3727), .val = 0x00 },
+ { .reg = CCI_REG8(0x3728), .val = 0x32 },
+ { .reg = CCI_REG8(0x3729), .val = 0x00 },
+ { .reg = CCI_REG8(0x372a), .val = 0x32 },
+ { .reg = CCI_REG8(0x372b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3730), .val = 0x32 },
+ { .reg = CCI_REG8(0x3731), .val = 0x00 },
+ { .reg = CCI_REG8(0x3732), .val = 0x32 },
+ { .reg = CCI_REG8(0x3733), .val = 0x00 },
+ { .reg = CCI_REG8(0x3734), .val = 0x32 },
+ { .reg = CCI_REG8(0x3735), .val = 0x00 },
+ { .reg = CCI_REG8(0x3736), .val = 0x32 },
+ { .reg = CCI_REG8(0x3737), .val = 0x00 },
+ { .reg = CCI_REG8(0x3738), .val = 0x32 },
+ { .reg = CCI_REG8(0x3739), .val = 0x00 },
+ { .reg = CCI_REG8(0x373a), .val = 0x32 },
+ { .reg = CCI_REG8(0x373b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3790), .val = 0x32 },
+ { .reg = CCI_REG8(0x3791), .val = 0x00 },
+ { .reg = CCI_REG8(0x3792), .val = 0x32 },
+ { .reg = CCI_REG8(0x3793), .val = 0x00 },
+ { .reg = CCI_REG8(0x3794), .val = 0x32 },
+ { .reg = CCI_REG8(0x3795), .val = 0x00 },
+ { .reg = CCI_REG8(0x3796), .val = 0x32 },
+ { .reg = CCI_REG8(0x3797), .val = 0x00 },
+ { .reg = CCI_REG8(0x3798), .val = 0x32 },
+ { .reg = CCI_REG8(0x3799), .val = 0x00 },
+ { .reg = CCI_REG8(0x379a), .val = 0x32 },
+ { .reg = CCI_REG8(0x379b), .val = 0x00 },
+ { .reg = CCI_REG8(0x37a0), .val = 0x50 },
+ { .reg = CCI_REG8(0x37a1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37a2), .val = 0x50 },
+ { .reg = CCI_REG8(0x37a3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37a4), .val = 0x50 },
+ { .reg = CCI_REG8(0x37a5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37a6), .val = 0x50 },
+ { .reg = CCI_REG8(0x37a7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37a8), .val = 0x50 },
+ { .reg = CCI_REG8(0x37a9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37aa), .val = 0x50 },
+ { .reg = CCI_REG8(0x37ab), .val = 0x00 },
+ { .reg = CCI_REG8(0x37b0), .val = 0x64 },
+ { .reg = CCI_REG8(0x37b1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37b2), .val = 0x64 },
+ { .reg = CCI_REG8(0x37b3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37b4), .val = 0x64 },
+ { .reg = CCI_REG8(0x37b5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37b6), .val = 0x64 },
+ { .reg = CCI_REG8(0x37b7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37b8), .val = 0x64 },
+ { .reg = CCI_REG8(0x37b9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37ba), .val = 0x64 },
+ { .reg = CCI_REG8(0x37bb), .val = 0x00 },
+ { .reg = CCI_REG8(0x37c0), .val = 0x50 },
+ { .reg = CCI_REG8(0x37c1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37c2), .val = 0x50 },
+ { .reg = CCI_REG8(0x37c3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37c4), .val = 0x50 },
+ { .reg = CCI_REG8(0x37c5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37c6), .val = 0x50 },
+ { .reg = CCI_REG8(0x37c7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37c8), .val = 0x50 },
+ { .reg = CCI_REG8(0x37c9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37ca), .val = 0x50 },
+ { .reg = CCI_REG8(0x37cb), .val = 0x00 },
+ { .reg = CCI_REG8(0x37d0), .val = 0x32 },
+ { .reg = CCI_REG8(0x37d1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37d2), .val = 0x32 },
+ { .reg = CCI_REG8(0x37d3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37d4), .val = 0x32 },
+ { .reg = CCI_REG8(0x37d5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37d6), .val = 0x32 },
+ { .reg = CCI_REG8(0x37d7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37d8), .val = 0x32 },
+ { .reg = CCI_REG8(0x37d9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37da), .val = 0x32 },
+ { .reg = CCI_REG8(0x37db), .val = 0x00 },
+ { .reg = CCI_REG8(0x37e0), .val = 0x1e },
+ { .reg = CCI_REG8(0x37e1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37e2), .val = 0x1e },
+ { .reg = CCI_REG8(0x37e3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37e4), .val = 0x1e },
+ { .reg = CCI_REG8(0x37e5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37e6), .val = 0x1e },
+ { .reg = CCI_REG8(0x37e7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37e8), .val = 0x1e },
+ { .reg = CCI_REG8(0x37e9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37ea), .val = 0x1e },
+ { .reg = CCI_REG8(0x37eb), .val = 0x00 },
+ { .reg = CCI_REG8(0x37f0), .val = 0x1e },
+ { .reg = CCI_REG8(0x37f1), .val = 0x00 },
+ { .reg = CCI_REG8(0x37f2), .val = 0x1e },
+ { .reg = CCI_REG8(0x37f3), .val = 0x00 },
+ { .reg = CCI_REG8(0x37f4), .val = 0x1e },
+ { .reg = CCI_REG8(0x37f5), .val = 0x00 },
+ { .reg = CCI_REG8(0x37f6), .val = 0x1e },
+ { .reg = CCI_REG8(0x37f7), .val = 0x00 },
+ { .reg = CCI_REG8(0x37f8), .val = 0x1e },
+ { .reg = CCI_REG8(0x37f9), .val = 0x00 },
+ { .reg = CCI_REG8(0x37fa), .val = 0x1e },
+ { .reg = CCI_REG8(0x37fb), .val = 0x00 },
+ { .reg = CCI_REG8(0x3800), .val = 0x1e },
+ { .reg = CCI_REG8(0x3801), .val = 0x00 },
+ { .reg = CCI_REG8(0x3802), .val = 0x1e },
+ { .reg = CCI_REG8(0x3803), .val = 0x00 },
+ { .reg = CCI_REG8(0x3804), .val = 0x1e },
+ { .reg = CCI_REG8(0x3805), .val = 0x00 },
+ { .reg = CCI_REG8(0x3806), .val = 0x1e },
+ { .reg = CCI_REG8(0x3807), .val = 0x00 },
+ { .reg = CCI_REG8(0x3808), .val = 0x1e },
+ { .reg = CCI_REG8(0x3809), .val = 0x00 },
+ { .reg = CCI_REG8(0x380a), .val = 0x1e },
+ { .reg = CCI_REG8(0x380b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3810), .val = 0x1e },
+ { .reg = CCI_REG8(0x3811), .val = 0x00 },
+ { .reg = CCI_REG8(0x3812), .val = 0x1e },
+ { .reg = CCI_REG8(0x3813), .val = 0x00 },
+ { .reg = CCI_REG8(0x3814), .val = 0x1e },
+ { .reg = CCI_REG8(0x3815), .val = 0x00 },
+ { .reg = CCI_REG8(0x3816), .val = 0x1e },
+ { .reg = CCI_REG8(0x3817), .val = 0x00 },
+ { .reg = CCI_REG8(0x3818), .val = 0x1e },
+ { .reg = CCI_REG8(0x3819), .val = 0x00 },
+ { .reg = CCI_REG8(0x381a), .val = 0x1e },
+ { .reg = CCI_REG8(0x381b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3820), .val = 0x1e },
+ { .reg = CCI_REG8(0x3821), .val = 0x00 },
+ { .reg = CCI_REG8(0x3822), .val = 0x1e },
+ { .reg = CCI_REG8(0x3823), .val = 0x00 },
+ { .reg = CCI_REG8(0x3824), .val = 0x1e },
+ { .reg = CCI_REG8(0x3825), .val = 0x00 },
+ { .reg = CCI_REG8(0x3826), .val = 0x1e },
+ { .reg = CCI_REG8(0x3827), .val = 0x00 },
+ { .reg = CCI_REG8(0x3828), .val = 0x1e },
+ { .reg = CCI_REG8(0x3829), .val = 0x00 },
+ { .reg = CCI_REG8(0x382a), .val = 0x1e },
+ { .reg = CCI_REG8(0x382b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3870), .val = 0x32 },
+ { .reg = CCI_REG8(0x3871), .val = 0x00 },
+ { .reg = CCI_REG8(0x3872), .val = 0x32 },
+ { .reg = CCI_REG8(0x3873), .val = 0x00 },
+ { .reg = CCI_REG8(0x3874), .val = 0x32 },
+ { .reg = CCI_REG8(0x3875), .val = 0x00 },
+ { .reg = CCI_REG8(0x3876), .val = 0x32 },
+ { .reg = CCI_REG8(0x3877), .val = 0x00 },
+ { .reg = CCI_REG8(0x3878), .val = 0x32 },
+ { .reg = CCI_REG8(0x3879), .val = 0x00 },
+ { .reg = CCI_REG8(0x387a), .val = 0x32 },
+ { .reg = CCI_REG8(0x387b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3880), .val = 0x32 },
+ { .reg = CCI_REG8(0x3881), .val = 0x00 },
+ { .reg = CCI_REG8(0x3882), .val = 0x32 },
+ { .reg = CCI_REG8(0x3883), .val = 0x00 },
+ { .reg = CCI_REG8(0x3884), .val = 0x32 },
+ { .reg = CCI_REG8(0x3885), .val = 0x00 },
+ { .reg = CCI_REG8(0x3886), .val = 0x32 },
+ { .reg = CCI_REG8(0x3887), .val = 0x00 },
+ { .reg = CCI_REG8(0x3888), .val = 0x32 },
+ { .reg = CCI_REG8(0x3889), .val = 0x00 },
+ { .reg = CCI_REG8(0x388a), .val = 0x32 },
+ { .reg = CCI_REG8(0x388b), .val = 0x00 },
+ { .reg = CCI_REG8(0x3890), .val = 0x32 },
+ { .reg = CCI_REG8(0x3891), .val = 0x00 },
+ { .reg = CCI_REG8(0x3892), .val = 0x32 },
+ { .reg = CCI_REG8(0x3893), .val = 0x00 },
+ { .reg = CCI_REG8(0x3894), .val = 0x32 },
+ { .reg = CCI_REG8(0x3895), .val = 0x00 },
+ { .reg = CCI_REG8(0x3896), .val = 0x32 },
+ { .reg = CCI_REG8(0x3897), .val = 0x00 },
+ { .reg = CCI_REG8(0x3898), .val = 0x32 },
+ { .reg = CCI_REG8(0x3899), .val = 0x00 },
+ { .reg = CCI_REG8(0x389a), .val = 0x32 },
+ { .reg = CCI_REG8(0x389b), .val = 0x00 },
+ { .reg = CCI_REG8(0x38a0), .val = 0x32 },
+ { .reg = CCI_REG8(0x38a1), .val = 0x00 },
+ { .reg = CCI_REG8(0x38a2), .val = 0x32 },
+ { .reg = CCI_REG8(0x38a3), .val = 0x00 },
+ { .reg = CCI_REG8(0x38a4), .val = 0x32 },
+ { .reg = CCI_REG8(0x38a5), .val = 0x00 },
+ { .reg = CCI_REG8(0x38a6), .val = 0x32 },
+ { .reg = CCI_REG8(0x38a7), .val = 0x00 },
+ { .reg = CCI_REG8(0x38a8), .val = 0x32 },
+ { .reg = CCI_REG8(0x38a9), .val = 0x00 },
+ { .reg = CCI_REG8(0x38aa), .val = 0x32 },
+ { .reg = CCI_REG8(0x38ab), .val = 0x00 },
+ { .reg = CCI_REG8(0x38b0), .val = 0x32 },
+ { .reg = CCI_REG8(0x38b1), .val = 0x00 },
+ { .reg = CCI_REG8(0x38b2), .val = 0x32 },
+ { .reg = CCI_REG8(0x38b3), .val = 0x00 },
+ { .reg = CCI_REG8(0x38b4), .val = 0x32 },
+ { .reg = CCI_REG8(0x38b5), .val = 0x00 },
+ { .reg = CCI_REG8(0x38b6), .val = 0x32 },
+ { .reg = CCI_REG8(0x38b7), .val = 0x00 },
+ { .reg = CCI_REG8(0x38b8), .val = 0x32 },
+ { .reg = CCI_REG8(0x38b9), .val = 0x00 },
+ { .reg = CCI_REG8(0x38ba), .val = 0x32 },
+ { .reg = CCI_REG8(0x38bb), .val = 0x00 },
+ { .reg = CCI_REG8(0x320a), .val = 0xff },
+ { .reg = CCI_REG8(0x320b), .val = 0x03 },
+ { .reg = CCI_REG8(0x320c), .val = 0x07 },
+ { .reg = CCI_REG8(0x320d), .val = 0x00 },
+ { .reg = CCI_REG8(0x320e), .val = 0xff },
+ { .reg = CCI_REG8(0x320f), .val = 0x03 },
+ { .reg = CCI_REG8(0x3210), .val = 0x07 },
+ { .reg = CCI_REG8(0x3211), .val = 0x00 },
+ { .reg = CCI_REG16(0x321e), .val = 0x0000 },
+ { .reg = CCI_REG16(0x31d4), .val = 0x00ff },
+ { .reg = CCI_REG16(0x321a), .val = 0x0406 },
+ { .reg = CCI_REG8(0x3244), .val = 0x01 },
+ { .reg = CCI_REG8(0x3245), .val = 0x01 },
+ { .reg = CCI_REG8(0x3246), .val = 0x01 },
+ { .reg = CCI_REG8(0x3247), .val = 0x01 },
+ { .reg = CCI_REG8(0x3248), .val = 0x00 },
+ { .reg = CCI_REG8(0x3249), .val = 0x10 },
+ { .reg = CCI_REG16(0x3266), .val = 0x0100 },
+ { .reg = CCI_REG16(0x3330), .val = 0x0108 },
+ { .reg = CCI_REG8(0x3334), .val = 0x01 },
+ { .reg = CCI_REG8(0x3335), .val = 0x00 },
+ { .reg = CCI_REG8(0x3336), .val = 0x00 },
+ { .reg = CCI_REG8(0x3337), .val = 0x00 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2002 },
+ { .burst = s5kjn5_data_bb8a, .burst_addr = 0xbb8a,
+ .burst_len = ARRAY_SIZE(s5kjn5_data_bb8a) },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x4000 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x2000 },
+ { .reg = CCI_REG16(0x68d8), .val = 0x0100 },
+ { .reg = CCI_REG16(0xfcfc), .val = 0x4000 },
+ { .reg = CCI_REG16(0x0e04), .val = 0x0803 },
+ { .reg = CCI_REG8(0x0e10), .val = 0x01 },
+ { .reg = CCI_REG8(0x0e11), .val = 0x00 },
+ { .reg = CCI_REG8(0x0e12), .val = 0x00 },
+ { .reg = CCI_REG8(0x0e13), .val = 0x20 },
+ { .reg = CCI_REG8(0x0e14), .val = 0x00 },
+ { .reg = CCI_REG8(0x0e15), .val = 0x2b },
+ { .reg = CCI_REG8(0x0e16), .val = 0x02 },
+ { .reg = CCI_REG8(0x0e17), .val = 0x00 },
+ { .reg = CCI_REG8(0x0e18), .val = 0x00 },
+ { .reg = CCI_REG8(0x0e19), .val = 0x40 },
+ { .reg = CCI_REG8(0x0e1a), .val = 0x01 },
+ { .reg = CCI_REG8(0x0e1b), .val = 0x2b },
+ { .reg = CCI_REG8(0x0106), .val = 0x01 },
+ { .reg = CCI_REG8(0x0bcc), .val = 0x00 },
+ { .reg = CCI_REG8(0x0101), .val = 0x03 },
+};
+
+static const struct cci_reg_sequence s5kjn5_4096x3072_regs[] = {
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x6170), 0xffff },
+ { CCI_REG16(0x6180), 0x0000 },
+ { CCI_REG16(0x6190), 0x0000 },
+ { CCI_REG16(0x6200), 0xffff },
+ { CCI_REG16(0x6202), 0xffff },
+ { CCI_REG16(0x6204), 0x0000 },
+ { CCI_REG16(0x6206), 0x0000 },
+ { CCI_REG16(0x6208), 0x0000 },
+ { CCI_REG16(0xa100), 0xffff },
+ { CCI_REG16(0xa102), 0x0000 },
+ { CCI_REG16(0xa104), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x4001 },
+ { CCI_REG16(0x0102), 0xffff },
+ { CCI_REG16(0x0104), 0x0000 },
+ { CCI_REG16(0x0108), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x8100), 0xffff },
+ { CCI_REG16(0x8104), 0x0000 },
+ { CCI_REG16(0x8108), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0x7806), 0x0001 },
+ { CCI_REG16(0x7808), 0x2408 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0344), 0x0000 },
+ { CCI_REG16(0x0348), 0x201f },
+ { CCI_REG16(0x0346), 0x0000 },
+ { CCI_REG16(0x034a), 0x181f },
+ { CCI_REG16(0x034c), 0x1000 },
+ { CCI_REG16(0x034e), 0x0c00 },
+ { CCI_REG16(0x0350), 0x0008 },
+ { CCI_REG16(0x0352), 0x0008 },
+ { CCI_REG16(0x0340), 0x14b0 },
+ { CCI_REG16(0x0342), 0x16a8 },
+ { CCI_REG16(0x0136), 0x1300 },
+ { CCI_REG16(0x013e), 0x00c8 },
+ { CCI_REG16(0x0304), 0x0002 },
+ { CCI_REG16(0x0306), 0x00c0 },
+ { CCI_REG16(0x030c), 0x0000 },
+ { CCI_REG16(0x030e), 0x0003 },
+ { CCI_REG16(0x0310), 0x00c3 },
+ { CCI_REG16(0x0312), 0x0000 },
+ { CCI_REG16(0x031a), 0x0003 },
+ { CCI_REG16(0x031c), 0x0032 },
+ { CCI_REG16(0x031e), 0x0002 },
+ { CCI_REG16(0x0202), 0x0014 },
+ { CCI_REG16(0x0226), 0x0014 },
+ { CCI_REG16(0x022c), 0x0014 },
+ { CCI_REG16(0x0702), 0x0000 },
+ { CCI_REG16(0x0704), 0x0000 },
+ { CCI_REG16(0x0114), 0x0301 },
+ { CCI_REG16(0x0118), 0x0004 },
+ { CCI_REG16(0x011a), 0x0001 },
+ { CCI_REG16(0x011c), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xb176), 0x0602 },
+ { CCI_REG16(0xb178), 0x0000 },
+ { CCI_REG16(0x7996), 0x0101 },
+ { CCI_REG16(0x7994), 0x2020 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0900), 0x2222 },
+ { CCI_REG16(0x0380), 0x0002 },
+ { CCI_REG16(0x0382), 0x0002 },
+ { CCI_REG16(0x0384), 0x0002 },
+ { CCI_REG16(0x0386), 0x0002 },
+ { CCI_REG16(0x040c), 0x0000 },
+ { CCI_REG16(0x0400), 0x1010 },
+ { CCI_REG16(0x0408), 0x0100 },
+ { CCI_REG16(0x040a), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd1f6), 0x3a00 },
+ { CCI_REG16(0xd20c), 0x0908 },
+ { CCI_REG16(0xd314), 0x2002 },
+ { CCI_REG16(0xd27a), 0x0500 },
+ { CCI_REG16(0xd3f0), 0xb01c },
+ { CCI_REG16(0xd410), 0x4802 },
+ { CCI_REG16(0xd426), 0xd204 },
+ { CCI_REG16(0xd43c), 0x0140 },
+ { CCI_REG16(0xd412), 0xd204 },
+ { CCI_REG16(0xd428), 0xea0a },
+ { CCI_REG16(0xd43e), 0x0140 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0260), 0x0001 },
+ { CCI_REG16(0x0262), 0x0000 },
+ { CCI_REG16(0x0264), 0x0106 },
+ { CCI_REG16(0x0266), 0x0700 },
+ { CCI_REG16(0x0112), 0x0a0a },
+ { CCI_REG16(0x0270), 0x2b2b },
+ { CCI_REG16(0x0272), 0x2b10 },
+ { CCI_REG16(0x0274), 0x302b },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x44c6), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0b02), 0x0102 },
+ { CCI_REG16(0x0720), 0x0001 },
+ { CCI_REG16(0x0722), 0x0800 },
+ { CCI_REG16(0x0724), 0x0000 },
+ { CCI_REG16(0x0728), 0x0000 },
+ { CCI_REG16(0x072a), 0x0000 },
+ { CCI_REG16(0x072c), 0x0000 },
+ { CCI_REG16(0x072e), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x3132), 0x0200 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x021e), 0x0000 },
+ { CCI_REG16(0x0228), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x31d0), 0x0000 },
+ { CCI_REG16(0x5a70), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xdc94), 0x0103 },
+ { CCI_REG16(0xef80), 0x0000 },
+ { CCI_REG16(0x23f0), 0x0001 },
+ { CCI_REG16(0xf3e4), 0x0300 },
+ { CCI_REG16(0xf288), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x2a30), 0x01ff },
+ { CCI_REG16(0x4270), 0x0000 },
+ { CCI_REG16(0x29ba), 0x2000 },
+ { CCI_REG16(0x29a8), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0b04), 0x0001 },
+ { CCI_REG16(0x0b06), 0x0101 },
+ { CCI_REG16(0x0b08), 0x0100 },
+ { CCI_REG16(0x0b0a), 0x0101 },
+ { CCI_REG16(0x0b0c), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xc4e0), 0x0100 },
+ { CCI_REG16(0xc4f6), 0x0000 },
+ { CCI_REG16(0xc4e2), 0x0000 },
+ { CCI_REG16(0xc53c), 0x0500 },
+ { CCI_REG16(0xc544), 0x0005 },
+ { CCI_REG16(0xc53e), 0x0000 },
+ { CCI_REG16(0xb23c), 0x6060 },
+ { CCI_REG16(0xb242), 0x6060 },
+ { CCI_REG16(0xc554), 0x0010 },
+ { CCI_REG16(0xc556), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x2920), 0x0100 },
+ { CCI_REG16(0x31f8), 0x0000 },
+ { CCI_REG16(0x31fa), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd856), 0x0507 },
+ { CCI_REG16(0xd6d4), 0x0000 },
+ { CCI_REG16(0x799a), 0x0000 },
+ { CCI_REG16(0xd8a2), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x020a), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0x78c0), 0x0101 },
+ { CCI_REG16(0x22c2), 0x0600 },
+ { CCI_REG16(0x22c4), 0xff1f },
+ { CCI_REG16(0x22ec), 0x1f00 },
+ { CCI_REG16(0x2306), 0xff3f },
+ { CCI_REG16(0x2314), 0xff00 },
+ { CCI_REG16(0x2354), 0x0300 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0936), 0x0000 },
+ { CCI_REG16(0x0c40), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0x68de), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x2540), 0x0000 },
+ { CCI_REG16(0x25e0), 0x0000 },
+ { CCI_REG16(0x25e2), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd718), 0x0002 },
+ { CCI_REG16(0xbf30), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x3c42), 0x0000 },
+ { CCI_REG16(0x3c46), 0xeb05 },
+ { CCI_REG16(0x3c52), 0x4006 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd326), 0x0110 },
+ { CCI_REG16(0xd3ec), 0xb01c },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x195e), 0x0100 },
+ { CCI_REG16(0x1966), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0086), 0x1400 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xe980), 0x9e04 },
+ { CCI_REG16(0xc4d8), 0x2000 },
+ { CCI_REG16(0x795a), 0x2000 },
+ { CCI_REG16(0x7970), 0x2000 },
+ { CCI_REG16(0xfcfc), 0x2002 },
+ { CCI_REG16(0x849e), 0x0000 },
+ { CCI_REG16(0x84a0), 0x0000 },
+ { CCI_REG16(0x84a2), 0x0005 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x2bb2), 0x1000 },
+ { CCI_REG16(0x2d32), 0x0010 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0x703c), 0x0101 },
+ { CCI_REG16(0x7046), 0x7f02 },
+ { CCI_REG16(0x7058), 0x8002 },
+ { CCI_REG16(0x71d4), 0x3f00 },
+ { CCI_REG16(0x71d6), 0x3d00 },
+ { CCI_REG16(0x71d8), 0x84f3 },
+ { CCI_REG16(0x71da), 0x0040 },
+ { CCI_REG16(0x7048), 0x1f02 },
+ { CCI_REG16(0x705a), 0x2002 },
+ { CCI_REG16(0x7274), 0x0c00 },
+ { CCI_REG16(0x7276), 0x0b00 },
+ { CCI_REG16(0x7278), 0x36d2 },
+ { CCI_REG16(0x727a), 0x0040 },
+ { CCI_REG16(0x727c), 0x0000 },
+ { CCI_REG16(0x727e), 0x0000 },
+ { CCI_REG16(0x7280), 0x0000 },
+ { CCI_REG16(0x7282), 0x0000 },
+ { CCI_REG16(0x703e), 0x0100 },
+ { CCI_REG16(0x704a), 0x000a },
+ { CCI_REG16(0x705c), 0x010a },
+ { CCI_REG16(0x7314), 0x2e00 },
+ { CCI_REG16(0x7316), 0x3000 },
+ { CCI_REG16(0x7318), 0x9efd },
+ { CCI_REG16(0x731a), 0x0040 },
+ { CCI_REG16(0xbedc), 0xc526 },
+ { CCI_REG16(0xbede), 0x903e },
+ { CCI_REG16(0xbee0), 0xc00f },
+ { CCI_REG16(0xbee2), 0x0008 },
+ { CCI_REG16(0xbee4), 0x0c00 },
+ { CCI_REG16(0xbee6), 0x8000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x2a54), 0x0000 },
+ { CCI_REG16(0x2a56), 0x0400 },
+ { CCI_REG16(0x2a42), 0x0100 },
+ { CCI_REG16(0x2a44), 0x3907 },
+ { CCI_REG16(0x2a46), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd704), 0x0278 },
+ { CCI_REG16(0x7a0e), 0x0f00 },
+ { CCI_REG16(0x7a6e), 0x1900 },
+ { CCI_REG16(0x7a86), 0x1900 },
+ { CCI_REG16(0x8c9e), 0x3500 },
+ { CCI_REG16(0x8cce), 0x9600 },
+ { CCI_REG16(0x7a10), 0x0f00 },
+ { CCI_REG16(0x7a70), 0x1900 },
+ { CCI_REG16(0x7a88), 0x1900 },
+ { CCI_REG16(0x8ca0), 0x3500 },
+ { CCI_REG16(0x8cd0), 0x9600 },
+ { CCI_REG16(0xb224), 0x0103 },
+ { CCI_REG16(0xb226), 0x0000 },
+ { CCI_REG16(0xb220), 0x0103 },
+ { CCI_REG16(0x7a12), 0x0f00 },
+ { CCI_REG16(0x7a72), 0x1900 },
+ { CCI_REG16(0x7a8a), 0x1900 },
+ { CCI_REG16(0x8ca2), 0x5000 },
+ { CCI_REG16(0x8cd2), 0xbe00 },
+ { CCI_REG16(0x7ee6), 0x2c00 },
+ { CCI_REG16(0x7ef2), 0x2c00 },
+ { CCI_REG16(0x7efe), 0x6400 },
+ { CCI_REG16(0x7f0a), 0x5800 },
+ { CCI_REG16(0x8d0e), 0x0000 },
+ { CCI_REG16(0x9032), 0x0000 },
+ { CCI_REG16(0x903e), 0x0000 },
+ { CCI_REG16(0x7a14), 0x0f00 },
+ { CCI_REG16(0x7a74), 0x1900 },
+ { CCI_REG16(0x7a8c), 0x1900 },
+ { CCI_REG16(0x8ca4), 0x3500 },
+ { CCI_REG16(0x7f0e), 0x5800 },
+ { CCI_REG16(0x8cd6), 0x9600 },
+ { CCI_REG16(0x7bda), 0x4c00 },
+ { CCI_REG16(0xd49c), 0x2100 },
+ { CCI_REG16(0xd4d0), 0x0a00 },
+ { CCI_REG16(0xd4a8), 0x0100 },
+ { CCI_REG16(0xd4d6), 0x1a00 },
+ { CCI_REG16(0xd4e2), 0x0000 },
+ { CCI_REG16(0xd4bc), 0x3700 },
+ { CCI_REG16(0xd4b0), 0x9603 },
+ { CCI_REG16(0xd4c8), 0x0100 },
+ { CCI_REG16(0xd624), 0x0000 },
+ { CCI_REG16(0xd62e), 0x0000 },
+ { CCI_REG16(0xd638), 0x0000 },
+ { CCI_REG16(0xd4ea), 0x0100 },
+ { CCI_REG16(0xd554), 0xc400 },
+ { CCI_REG16(0xd556), 0xc400 },
+ { CCI_REG16(0xd560), 0x5203 },
+ { CCI_REG16(0xd562), 0x5203 },
+ { CCI_REG16(0xd4da), 0x0000 },
+ { CCI_REG16(0xd4e6), 0x0100 },
+ { CCI_REG16(0xd4c0), 0x1400 },
+ { CCI_REG16(0xd4b4), 0x0100 },
+ { CCI_REG16(0xd4cc), 0x0000 },
+ { CCI_REG16(0xd5bc), 0x0000 },
+ { CCI_REG16(0xd5be), 0x0000 },
+ { CCI_REG16(0xd5c8), 0x0000 },
+ { CCI_REG16(0xd5ca), 0x0000 },
+ { CCI_REG16(0xd4d2), 0x0000 },
+ { CCI_REG16(0xd4de), 0x0100 },
+ { CCI_REG16(0xd4b8), 0x1400 },
+ { CCI_REG16(0xd4ac), 0x0100 },
+ { CCI_REG16(0xd4c4), 0x0000 },
+ { CCI_REG16(0xd4ec), 0x0000 },
+ { CCI_REG16(0xd4ee), 0x0000 },
+ { CCI_REG16(0xd4f8), 0x0000 },
+ { CCI_REG16(0xd4fa), 0x0000 },
+ { CCI_REG16(0xbf78), 0x5333 },
+ { CCI_REG16(0xd896), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x1c24), 0x0002 },
+ { CCI_REG16(0x1c26), 0x8001 },
+ { CCI_REG16(0x1c28), 0x8004 },
+ { CCI_REG16(0x1c2a), 0x2010 },
+ { CCI_REG16(0x1c2c), 0x2010 },
+ { CCI_REG16(0x1c2e), 0x0005 },
+ { CCI_REG16(0x1c30), 0x00a0 },
+ { CCI_REG16(0x1c32), 0x2810 },
+ { CCI_REG16(0x1c34), 0x2810 },
+ { CCI_REG16(0x1c4e), 0x8001 },
+ { CCI_REG16(0x1c50), 0x8004 },
+ { CCI_REG16(0x1c52), 0x0010 },
+ { CCI_REG16(0x1c54), 0x0010 },
+ { CCI_REG16(0x1c56), 0x0005 },
+ { CCI_REG16(0x1c58), 0x00a0 },
+ { CCI_REG16(0x1c5a), 0x2810 },
+ { CCI_REG16(0x1c5c), 0x2810 },
+ { CCI_REG16(0x1c5e), 0x0000 },
+ { CCI_REG16(0x1c60), 0x0000 },
+ { CCI_REG16(0x1c62), 0x0000 },
+ { CCI_REG16(0x1c64), 0x0000 },
+ { CCI_REG16(0x1c66), 0x0000 },
+ { CCI_REG16(0x1c68), 0x0000 },
+ { CCI_REG16(0x1c6a), 0x0000 },
+ { CCI_REG16(0x1c6c), 0x0000 },
+ { CCI_REG16(0x1c76), 0x8001 },
+ { CCI_REG16(0x1c78), 0x8004 },
+ { CCI_REG16(0x1c7a), 0x2010 },
+ { CCI_REG16(0x1c7c), 0x2010 },
+ { CCI_REG16(0x1c7e), 0x0005 },
+ { CCI_REG16(0x1c80), 0x00a0 },
+ { CCI_REG16(0x1c82), 0x2810 },
+ { CCI_REG16(0x1c84), 0x2810 },
+ { CCI_REG16(0x1c86), 0x0000 },
+ { CCI_REG16(0x1c88), 0x0000 },
+ { CCI_REG16(0x1c8a), 0x0000 },
+ { CCI_REG16(0x1c8c), 0x0000 },
+ { CCI_REG16(0x1c8e), 0x0000 },
+ { CCI_REG16(0x1c90), 0x0000 },
+ { CCI_REG16(0x1c92), 0x0000 },
+ { CCI_REG16(0x1c94), 0x0000 },
+ { CCI_REG16(0x1c9e), 0x8001 },
+ { CCI_REG16(0x1ca0), 0x8004 },
+ { CCI_REG16(0x1ca2), 0x2010 },
+ { CCI_REG16(0x1ca4), 0x2010 },
+ { CCI_REG16(0x1ca6), 0x0005 },
+ { CCI_REG16(0x1ca8), 0x00a0 },
+ { CCI_REG16(0x1caa), 0x2810 },
+ { CCI_REG16(0x1cac), 0x2810 },
+ { CCI_REG16(0x1cc6), 0x8001 },
+ { CCI_REG16(0x1cc8), 0x8004 },
+ { CCI_REG16(0x1cca), 0x2010 },
+ { CCI_REG16(0x1ccc), 0x2010 },
+ { CCI_REG16(0x1cce), 0x0005 },
+ { CCI_REG16(0x1cd0), 0x00a0 },
+ { CCI_REG16(0x1cd2), 0x2810 },
+ { CCI_REG16(0x1cd4), 0x2810 },
+ { CCI_REG16(0x1cee), 0x8001 },
+ { CCI_REG16(0x1cf0), 0x8004 },
+ { CCI_REG16(0x1cf2), 0x0010 },
+ { CCI_REG16(0x1cf4), 0x0010 },
+ { CCI_REG16(0x1cf6), 0x0005 },
+ { CCI_REG16(0x1cf8), 0x00a0 },
+ { CCI_REG16(0x1cfa), 0x2810 },
+ { CCI_REG16(0x1cfc), 0x2810 },
+ { CCI_REG16(0x1cfe), 0x0000 },
+ { CCI_REG16(0x1d00), 0x0000 },
+ { CCI_REG16(0x1d02), 0x0000 },
+ { CCI_REG16(0x1d04), 0x0000 },
+ { CCI_REG16(0x1d06), 0x0000 },
+ { CCI_REG16(0x1d08), 0x0000 },
+ { CCI_REG16(0x1d0a), 0x0000 },
+ { CCI_REG16(0x1d0c), 0x0000 },
+ { CCI_REG16(0x1d16), 0x8001 },
+ { CCI_REG16(0x1d18), 0x8004 },
+ { CCI_REG16(0x1d1a), 0x2010 },
+ { CCI_REG16(0x1d1c), 0x2010 },
+ { CCI_REG16(0x1d1e), 0x0005 },
+ { CCI_REG16(0x1d20), 0x00a0 },
+ { CCI_REG16(0x1d22), 0x2810 },
+ { CCI_REG16(0x1d24), 0x2810 },
+ { CCI_REG16(0x1d26), 0x0000 },
+ { CCI_REG16(0x1d28), 0x0000 },
+ { CCI_REG16(0x1d2a), 0x0000 },
+ { CCI_REG16(0x1d2c), 0x0000 },
+ { CCI_REG16(0x1d2e), 0x0000 },
+ { CCI_REG16(0x1d30), 0x0000 },
+ { CCI_REG16(0x1d32), 0x0000 },
+ { CCI_REG16(0x1d34), 0x0000 },
+ { CCI_REG16(0x1d3e), 0x8001 },
+ { CCI_REG16(0x1d40), 0x8004 },
+ { CCI_REG16(0x1d42), 0x2010 },
+ { CCI_REG16(0x1d44), 0x2010 },
+ { CCI_REG16(0x1d46), 0x0005 },
+ { CCI_REG16(0x1d48), 0x00a0 },
+ { CCI_REG16(0x1d4a), 0x2810 },
+ { CCI_REG16(0x1d4c), 0x2810 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xb21e), 0x0000 },
+ { CCI_REG16(0xb222), 0xc000 },
+ { CCI_REG16(0xb20c), 0x2e00 },
+ { CCI_REG16(0xb21a), 0x0402 },
+ { CCI_REG16(0xb378), 0x0100 },
+ { CCI_REG16(0xdd70), 0x0000 },
+ { CCI_REG16(0xde38), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2002 },
+ { CCI_REG16(0xa574), 0x0100 },
+ { CCI_REG16(0xa59c), 0xa2fd },
+ { CCI_REG16(0xa59e), 0xfefe },
+ { CCI_REG16(0xa576), 0x4000 },
+ { CCI_REG16(0xa588), 0x0e00 },
+ { CCI_REG16(0xa578), 0x8000 },
+ { CCI_REG16(0xa58a), 0x2000 },
+ { CCI_REG16(0xa57a), 0xa000 },
+ { CCI_REG16(0xa58c), 0x2800 },
+ { CCI_REG16(0xa57c), 0x4001 },
+ { CCI_REG16(0xa58e), 0x1400 },
+ { CCI_REG16(0xa57e), 0x8002 },
+ { CCI_REG16(0xa590), 0x2200 },
+ { CCI_REG16(0xa580), 0x0005 },
+ { CCI_REG16(0xa592), 0x2800 },
+ { CCI_REG16(0xa582), 0x000a },
+ { CCI_REG16(0xa594), 0x2c00 },
+ { CCI_REG16(0xa584), 0xa00f },
+ { CCI_REG16(0xa596), 0x2e00 },
+ { CCI_REG16(0xa586), 0x4011 },
+ { CCI_REG16(0xa598), 0x3200 },
+ { CCI_REG16(0xa59a), 0x3800 },
+ { CCI_REG16(0xa548), 0x0000 },
+ { CCI_REG16(0xa570), 0x0000 },
+ { CCI_REG16(0xa54a), 0x0000 },
+ { CCI_REG16(0xa54c), 0x0000 },
+ { CCI_REG16(0xa54e), 0x0000 },
+ { CCI_REG16(0xa550), 0x0000 },
+ { CCI_REG16(0xa552), 0x0000 },
+ { CCI_REG16(0xa554), 0x0000 },
+ { CCI_REG16(0xa556), 0x0000 },
+ { CCI_REG16(0xa55c), 0x0000 },
+ { CCI_REG16(0xa55e), 0x0000 },
+ { CCI_REG16(0xa560), 0x0000 },
+ { CCI_REG16(0xa562), 0x0000 },
+ { CCI_REG16(0xa564), 0x0000 },
+ { CCI_REG16(0xa566), 0x0000 },
+ { CCI_REG16(0xa568), 0x0000 },
+ { CCI_REG16(0xa56a), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x1e16), 0x0000 },
+ { CCI_REG16(0x1e1e), 0x0000 },
+ { CCI_REG16(0x1e56), 0x0000 },
+ { CCI_REG16(0x1e5e), 0x0000 },
+ { CCI_REG16(0x1df2), 0x0000 },
+ { CCI_REG16(0x1dfa), 0x0000 },
+ { CCI_REG16(0x1e32), 0x0000 },
+ { CCI_REG16(0x1e3a), 0x0000 },
+ { CCI_REG16(0x1e12), 0x0000 },
+ { CCI_REG16(0x1e1a), 0x0000 },
+ { CCI_REG16(0x1e52), 0x0000 },
+ { CCI_REG16(0x1e5a), 0x0000 },
+ { CCI_REG16(0x1df6), 0x0000 },
+ { CCI_REG16(0x1dfe), 0x0000 },
+ { CCI_REG16(0x1e36), 0x0000 },
+ { CCI_REG16(0x1e3e), 0x0000 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0x82ba), 0x3300 },
+ { CCI_REG16(0x82a2), 0x1400 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x427c), 0x2000 },
+ { CCI_REG16(0x4280), 0x1000 },
+ { CCI_REG16(0x4362), 0x0100 },
+ { CCI_REG16(0x43aa), 0x0000 },
+ { CCI_REG16(0x43ac), 0x0000 },
+ { CCI_REG16(0x43c6), 0x010a },
+ { CCI_REG16(0x43b4), 0x0000 },
+ { CCI_REG16(0x43b6), 0x0000 },
+ { CCI_REG16(0x4396), 0x0d00 },
+ { CCI_REG16(0x4398), 0x0e00 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xb322), 0x0101 },
+ { CCI_REG16(0xb324), 0x0100 },
+ { CCI_REG16(0xb330), 0x2828 },
+ { CCI_REG16(0xb34a), 0x2828 },
+ { CCI_REG16(0xb360), 0x2828 },
+ { CCI_REG16(0xfcfc), 0x2001 },
+ { CCI_REG16(0x4292), 0x0000 },
+ { CCI_REG16(0x4364), 0x0000 },
+ { CCI_REG16(0x4366), 0x0000 },
+ { CCI_REG16(0x4370), 0x0000 },
+ { CCI_REG16(0x4290), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2002 },
+ { CCI_REG16(0x84c4), 0x0100 },
+ { CCI_REG16(0xfcfc), 0x2000 },
+ { CCI_REG16(0xd684), 0x80f3 },
+ { CCI_REG16(0xb268), 0x80f3 },
+ { CCI_REG16(0xf09a), 0x00ff },
+ { CCI_REG16(0xf2e0), 0x0000 },
+ { CCI_REG16(0xf372), 0x0000 },
+ { CCI_REG16(0xf0aa), 0xffff },
+ { CCI_REG16(0xf0ac), 0xffff },
+ { CCI_REG16(0xf2ea), 0x4000 },
+ { CCI_REG16(0xdada), 0x0001 },
+ { CCI_REG16(0xdb3c), 0x12d2 },
+ { CCI_REG16(0xdadc), 0x0000 },
+ { CCI_REG16(0xdb0c), 0x0000 },
+ { CCI_REG16(0xdb3e), 0x12d2 },
+ { CCI_REG16(0xdade), 0x4000 },
+ { CCI_REG16(0xdb0e), 0x0040 },
+ { CCI_REG16(0xdb40), 0x12d2 },
+ { CCI_REG16(0xdae0), 0xe001 },
+ { CCI_REG16(0xdb10), 0x0000 },
+ { CCI_REG16(0xdb42), 0x12d2 },
+ { CCI_REG16(0xdae2), 0x2003 },
+ { CCI_REG16(0xdb12), 0x00b0 },
+ { CCI_REG16(0xdb44), 0x12d2 },
+ { CCI_REG16(0xdae4), 0x8007 },
+ { CCI_REG16(0xdb14), 0x00d0 },
+ { CCI_REG16(0xdb46), 0x12d2 },
+ { CCI_REG16(0xdae6), 0x000b },
+ { CCI_REG16(0xdb16), 0x00f0 },
+ { CCI_REG16(0xdbcc), 0x0000 },
+ { CCI_REG16(0xdb6c), 0x0000 },
+ { CCI_REG16(0xdb9c), 0x0000 },
+ { CCI_REG16(0xdbce), 0x0000 },
+ { CCI_REG16(0xdb6e), 0x0000 },
+ { CCI_REG16(0xdb9e), 0x0000 },
+ { CCI_REG16(0xdbd0), 0x0000 },
+ { CCI_REG16(0xdb70), 0x0000 },
+ { CCI_REG16(0xdba0), 0x0000 },
+ { CCI_REG16(0xdbd2), 0x0000 },
+ { CCI_REG16(0xdb72), 0x0000 },
+ { CCI_REG16(0xdba2), 0x0000 },
+ { CCI_REG16(0xdbd4), 0x0000 },
+ { CCI_REG16(0xdb74), 0x0000 },
+ { CCI_REG16(0xdba4), 0x0000 },
+ { CCI_REG16(0xdbd6), 0x0000 },
+ { CCI_REG16(0xdb76), 0x0000 },
+ { CCI_REG16(0xdba6), 0x0000 },
+ { CCI_REG16(0xf370), 0x0203 },
+ { CCI_REG16(0xf3e4), 0x0301 },
+ { CCI_REG16(0xf3f4), 0x7310 },
+ { CCI_REG16(0xf3f6), 0x1f20 },
+ { CCI_REG16(0xf014), 0x0600 },
+ { CCI_REG16(0xb270), 0x8708 },
+ { CCI_REG16(0xb266), 0xc004 },
+ { CCI_REG16(0xd682), 0xc004 },
+ { CCI_REG16(0xbf16), 0x0baa },
+ { CCI_REG16(0xdc8c), 0x3f0b },
+ { CCI_REG16(0xfcfc), 0x4000 },
+ { CCI_REG16(0x0808), 0x0000 },
+ { CCI_REG16(0x0e00), 0x0003 },
+};
+
+static const struct s5kjn5_mode s5kjn5_modes[] = {
+ {
+ .width = 4096,
+ .height = 3072,
+ .hts = 5800,
+ .vts_min = 5296,
+ .pixel_rate = 998400000ULL,
+ .exposure_margin = 12,
+ .regs = s5kjn5_4096x3072_regs,
+ .num_regs = ARRAY_SIZE(s5kjn5_4096x3072_regs),
+ },
+};
+
+struct s5kjn5 {
+ struct v4l2_subdev sd;
+ struct media_pad pad;
+ struct regmap *regmap;
+ struct clk *inclk;
+ struct gpio_desc *reset_gpio;
+ struct regulator_bulk_data supplies[S5KJN5_NUM_SUPPLIES];
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct v4l2_ctrl *link_freq;
+ struct v4l2_ctrl *pixel_rate;
+ struct v4l2_ctrl *vblank;
+ struct v4l2_ctrl *hblank;
+ struct v4l2_ctrl *exposure;
+ struct v4l2_ctrl *gain;
+ struct v4l2_ctrl *digital_gain;
+ struct v4l2_ctrl *test_pattern;
+};
+
+static inline struct s5kjn5 *sd_to_s5kjn5(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct s5kjn5, sd);
+}
+
+static int s5kjn5_write_init(struct s5kjn5 *s5kjn5)
+{
+ const struct s5kjn5_init_op *op;
+ int ret;
+
+ for (op = s5kjn5_init_ops;
+ op < s5kjn5_init_ops + ARRAY_SIZE(s5kjn5_init_ops); op++) {
+ if (op->burst)
+ ret = regmap_bulk_write(s5kjn5->regmap, op->burst_addr,
+ op->burst, op->burst_len);
+ else if (op->reg)
+ ret = cci_write(s5kjn5->regmap, op->reg, op->val, NULL);
+ else
+ ret = 0;
+ if (ret)
+ return ret;
+
+ if (op->delay_us)
+ fsleep(op->delay_us);
+ }
+
+ return 0;
+}
+
+static int s5kjn5_power_on(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
+ int ret;
+
+ ret = regulator_bulk_enable(S5KJN5_NUM_SUPPLIES, s5kjn5->supplies);
+ if (ret) {
+ dev_err(dev, "failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
+ gpiod_set_value_cansleep(s5kjn5->reset_gpio, 0);
+ usleep_range(8000, 10000);
+
+ ret = clk_prepare_enable(s5kjn5->inclk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock: %d\n", ret);
+ gpiod_set_value_cansleep(s5kjn5->reset_gpio, 1);
+ goto err_regulators;
+ }
+
+ usleep_range(10000, 12000);
+
+ return 0;
+
+err_regulators:
+ regulator_bulk_disable(S5KJN5_NUM_SUPPLIES, s5kjn5->supplies);
+ return ret;
+}
+
+static int s5kjn5_power_off(struct device *dev)
+{
+ struct v4l2_subdev *sd = dev_get_drvdata(dev);
+ struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
+
+ clk_disable_unprepare(s5kjn5->inclk);
+ gpiod_set_value_cansleep(s5kjn5->reset_gpio, 1);
+ regulator_bulk_disable(S5KJN5_NUM_SUPPLIES, s5kjn5->supplies);
+
+ return 0;
+}
+
+static int s5kjn5_check_id(struct s5kjn5 *s5kjn5)
+{
+ struct device *dev = s5kjn5->sd.dev;
+ u64 chip_id;
+ int ret;
+
+ ret = cci_read(s5kjn5->regmap, S5KJN5_REG_CHIP_ID, &chip_id, NULL);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to read chip ID\n");
+
+ if (chip_id != S5KJN5_CHIP_ID)
+ return dev_err_probe(dev, -ENODEV,
+ "unexpected chip ID 0x%04llx, expected 0x%04x\n",
+ chip_id, S5KJN5_CHIP_ID);
+
+ return 0;
+}
+
+static int s5kjn5_check_hwcfg(struct device *dev)
+{
+ struct fwnode_handle *fwnode = dev_fwnode(dev), *ep;
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY,
+ };
+ unsigned long freq_bitmap;
+ int ret;
+
+ if (!fwnode)
+ return -ENODEV;
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return dev_err_probe(dev, -EINVAL, "no endpoint found\n");
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to parse endpoint\n");
+
+ if (bus_cfg.bus.mipi_csi2.num_data_lanes != S5KJN5_DATA_LANES) {
+ ret = dev_err_probe(dev, -EINVAL,
+ "only %u data lanes supported\n",
+ S5KJN5_DATA_LANES);
+ goto out;
+ }
+
+ ret = v4l2_link_freq_to_bitmap(dev, bus_cfg.link_frequencies,
+ bus_cfg.nr_of_link_frequencies,
+ s5kjn5_link_freqs,
+ ARRAY_SIZE(s5kjn5_link_freqs),
+ &freq_bitmap);
+
+out:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+}
+
+static int s5kjn5_init(struct s5kjn5 *s5kjn5,
+ const struct s5kjn5_mode *mode)
+{
+ int ret;
+
+ ret = s5kjn5_write_init(s5kjn5);
+ if (ret)
+ return ret;
+
+ return cci_multi_reg_write(s5kjn5->regmap, mode->regs,
+ mode->num_regs, NULL);
+}
+
+static const char * const s5kjn5_test_pattern_menu[] = {
+ "Disabled",
+ "Solid Color",
+ "Color Bars",
+ "Fade To Grey Color Bars",
+ "PN9",
+};
+
+static int s5kjn5_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct s5kjn5 *s5kjn5 =
+ container_of(ctrl->handler, struct s5kjn5, ctrl_handler);
+ const struct s5kjn5_mode *mode = &s5kjn5_modes[0];
+ struct device *dev = s5kjn5->sd.dev;
+ u32 exposure_max;
+ int ret = 0;
+
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Update max exposure while meeting expected vblanking */
+ exposure_max = mode->height + ctrl->val - mode->exposure_margin;
+ __v4l2_ctrl_modify_range(s5kjn5->exposure,
+ s5kjn5->exposure->minimum,
+ exposure_max,
+ s5kjn5->exposure->step,
+ s5kjn5->exposure->default_value);
+ }
+
+ if (pm_runtime_get_if_active(dev) <= 0)
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_EXPOSURE,
+ ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_AGAIN,
+ ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_DIGITAL_GAIN:
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_DGAIN,
+ ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_VBLANK:
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_VTS,
+ mode->height + ctrl->val, NULL);
+ break;
+
+ case V4L2_CID_TEST_PATTERN:
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_TEST_PATTERN,
+ ctrl->val, NULL);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ pm_runtime_put_autosuspend(dev);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops s5kjn5_ctrl_ops = {
+ .s_ctrl = s5kjn5_s_ctrl,
+};
+
+static int s5kjn5_init_controls(struct s5kjn5 *s5kjn5)
+{
+ const struct s5kjn5_mode *mode = &s5kjn5_modes[0];
+ struct v4l2_ctrl_handler *hdlr = &s5kjn5->ctrl_handler;
+ struct v4l2_fwnode_device_properties props;
+ u32 vblank_min, vblank_def, vblank_max, hblank;
+ int ret;
+
+ v4l2_ctrl_handler_init(hdlr, 10);
+
+ s5kjn5->link_freq =
+ v4l2_ctrl_new_int_menu(hdlr, NULL, V4L2_CID_LINK_FREQ,
+ ARRAY_SIZE(s5kjn5_link_freqs) - 1, 0,
+ s5kjn5_link_freqs);
+ if (s5kjn5->link_freq)
+ s5kjn5->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ s5kjn5->pixel_rate =
+ v4l2_ctrl_new_std(hdlr, NULL, V4L2_CID_PIXEL_RATE,
+ mode->pixel_rate, mode->pixel_rate, 1,
+ mode->pixel_rate);
+
+ vblank_min = mode->vts_min - mode->height;
+ vblank_def = mode->vts_min - mode->height;
+ vblank_max = S5KJN5_VTS_MAX - mode->height;
+ s5kjn5->vblank =
+ v4l2_ctrl_new_std(hdlr, &s5kjn5_ctrl_ops, V4L2_CID_VBLANK,
+ vblank_min, vblank_max, 1, vblank_def);
+
+ hblank = mode->hts - mode->width;
+ s5kjn5->hblank =
+ v4l2_ctrl_new_std(hdlr, NULL, V4L2_CID_HBLANK,
+ hblank, hblank, 1, hblank);
+ if (s5kjn5->hblank)
+ s5kjn5->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ s5kjn5->exposure =
+ v4l2_ctrl_new_std(hdlr, &s5kjn5_ctrl_ops, V4L2_CID_EXPOSURE,
+ S5KJN5_EXPOSURE_MIN,
+ mode->vts_min - mode->exposure_margin,
+ 1, S5KJN5_EXPOSURE_DEFAULT);
+
+ s5kjn5->gain =
+ v4l2_ctrl_new_std(hdlr, &s5kjn5_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN,
+ S5KJN5_AGAIN_MIN, S5KJN5_AGAIN_MAX,
+ S5KJN5_AGAIN_STEP, S5KJN5_AGAIN_DEFAULT);
+
+ s5kjn5->digital_gain =
+ v4l2_ctrl_new_std(hdlr, &s5kjn5_ctrl_ops,
+ V4L2_CID_DIGITAL_GAIN,
+ S5KJN5_DGAIN_MIN, S5KJN5_DGAIN_MAX,
+ S5KJN5_DGAIN_STEP, S5KJN5_DGAIN_DEFAULT);
+
+ s5kjn5->test_pattern =
+ v4l2_ctrl_new_std_menu_items(hdlr, &s5kjn5_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(s5kjn5_test_pattern_menu) - 1,
+ 0, 0, s5kjn5_test_pattern_menu);
+
+ ret = v4l2_fwnode_device_parse(s5kjn5->sd.dev, &props);
+ if (ret) {
+ v4l2_ctrl_handler_free(hdlr);
+ return ret;
+ }
+
+ ret = v4l2_ctrl_new_fwnode_properties(hdlr, &s5kjn5_ctrl_ops, &props);
+ if (ret) {
+ v4l2_ctrl_handler_free(hdlr);
+ return ret;
+ }
+
+ if (hdlr->error) {
+ ret = hdlr->error;
+ v4l2_ctrl_handler_free(hdlr);
+ return ret;
+ }
+
+ s5kjn5->sd.ctrl_handler = hdlr;
+
+ return 0;
+}
+
+static int s5kjn5_enable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ u32 pad, u64 streams_mask)
+{
+ struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
+ struct device *dev = sd->dev;
+ const struct s5kjn5_mode *mode = &s5kjn5_modes[0];
+ int ret;
+
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret < 0)
+ return ret;
+
+ ret = s5kjn5_init(s5kjn5, mode);
+ if (ret) {
+ dev_err(dev, "failed to write init registers: %d\n", ret);
+ goto err_pm;
+ }
+
+ ret = __v4l2_ctrl_handler_setup(&s5kjn5->ctrl_handler);
+ if (ret)
+ goto err_pm;
+
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_STREAMING,
+ S5KJN5_STREAMING_ON, NULL);
+ if (ret) {
+ dev_err(dev, "failed to start streaming: %d\n", ret);
+ goto err_pm;
+ }
+
+ return 0;
+
+err_pm:
+ pm_runtime_put_autosuspend(dev);
+ return ret;
+}
+
+static int s5kjn5_disable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ u32 pad, u64 streams_mask)
+{
+ struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
+ struct device *dev = sd->dev;
+ u64 val;
+ int ret, i;
+
+ ret = cci_write(s5kjn5->regmap, S5KJN5_REG_STREAMING,
+ S5KJN5_STREAMING_OFF, NULL);
+ if (ret)
+ dev_warn(dev, "failed to stop streaming: %d\n", ret);
+
+ /* Poll frame count register until it reads standby */
+ for (i = 0; i < S5KJN5_STANDBY_POLL_ITERS; i++) {
+ usleep_range(5000, 6000);
+ ret = cci_read(s5kjn5->regmap, S5KJN5_REG_FRAME_COUNT,
+ &val, NULL);
+ if (!ret && val == S5KJN5_FRAME_COUNT_STANDBY)
+ break;
+ }
+ if (i == S5KJN5_STANDBY_POLL_ITERS)
+ dev_warn(dev, "timed out waiting for standby\n");
+
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
+}
+
+static int s5kjn5_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->index != 0)
+ return -EINVAL;
+
+ code->code = MEDIA_BUS_FMT_SGBRG10_1X10;
+
+ return 0;
+}
+
+static int s5kjn5_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->code != MEDIA_BUS_FMT_SGBRG10_1X10 ||
+ fse->index >= ARRAY_SIZE(s5kjn5_modes))
+ return -EINVAL;
+
+ fse->min_width = s5kjn5_modes[fse->index].width;
+ fse->max_width = s5kjn5_modes[fse->index].width;
+ fse->min_height = s5kjn5_modes[fse->index].height;
+ fse->max_height = s5kjn5_modes[fse->index].height;
+
+ return 0;
+}
+
+static void s5kjn5_fill_format(const struct s5kjn5_mode *mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = mode->width;
+ fmt->height = mode->height;
+ fmt->code = MEDIA_BUS_FMT_SGBRG10_1X10;
+ fmt->field = V4L2_FIELD_NONE;
+ fmt->colorspace = V4L2_COLORSPACE_RAW;
+ fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
+ fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
+ fmt->xfer_func = V4L2_XFER_FUNC_NONE;
+}
+
+static int s5kjn5_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state,
+ struct v4l2_subdev_format *fmt)
+{
+ const struct s5kjn5_mode *mode = &s5kjn5_modes[0];
+ struct v4l2_mbus_framefmt *format;
+
+ s5kjn5_fill_format(mode, &fmt->format);
+
+ format = v4l2_subdev_state_get_format(state, 0);
+ *format = fmt->format;
+
+ return 0;
+}
+
+static int s5kjn5_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct v4l2_mbus_framefmt *fmt =
+ v4l2_subdev_state_get_format(state, 0);
+
+ s5kjn5_fill_format(&s5kjn5_modes[0], fmt);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops s5kjn5_video_ops = {
+ .s_stream = v4l2_subdev_s_stream_helper,
+};
+
+static const struct v4l2_subdev_pad_ops s5kjn5_pad_ops = {
+ .enum_mbus_code = s5kjn5_enum_mbus_code,
+ .enum_frame_size = s5kjn5_enum_frame_size,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = s5kjn5_set_fmt,
+ .enable_streams = s5kjn5_enable_streams,
+ .disable_streams = s5kjn5_disable_streams,
+};
+
+static const struct v4l2_subdev_ops s5kjn5_subdev_ops = {
+ .video = &s5kjn5_video_ops,
+ .pad = &s5kjn5_pad_ops,
+};
+
+static const struct v4l2_subdev_internal_ops s5kjn5_internal_ops = {
+ .init_state = s5kjn5_init_state,
+};
+
+static const struct media_entity_operations s5kjn5_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static int s5kjn5_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct s5kjn5 *s5kjn5;
+ unsigned int i;
+ int ret;
+
+ s5kjn5 = devm_kzalloc(dev, sizeof(*s5kjn5), GFP_KERNEL);
+ if (!s5kjn5)
+ return -ENOMEM;
+
+ ret = s5kjn5_check_hwcfg(dev);
+ if (ret)
+ return ret;
+
+ v4l2_i2c_subdev_init(&s5kjn5->sd, client, &s5kjn5_subdev_ops);
+
+ s5kjn5->inclk = devm_v4l2_sensor_clk_get(dev, NULL);
+ if (IS_ERR(s5kjn5->inclk))
+ return dev_err_probe(dev, PTR_ERR(s5kjn5->inclk),
+ "failed to get clock\n");
+
+ if (clk_get_rate(s5kjn5->inclk) != S5KJN5_XVCLK_RATE)
+ return dev_err_probe(dev, -EINVAL,
+ "clock rate %lu Hz != required %u Hz\n",
+ clk_get_rate(s5kjn5->inclk),
+ S5KJN5_XVCLK_RATE);
+
+ s5kjn5->reset_gpio = devm_gpiod_get_optional(dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(s5kjn5->reset_gpio))
+ return dev_err_probe(dev, PTR_ERR(s5kjn5->reset_gpio),
+ "failed to get reset GPIO\n");
+
+ for (i = 0; i < S5KJN5_NUM_SUPPLIES; i++)
+ s5kjn5->supplies[i].supply = s5kjn5_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, S5KJN5_NUM_SUPPLIES,
+ s5kjn5->supplies);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to get regulators\n");
+
+ s5kjn5->regmap = devm_cci_regmap_init_i2c(client, 16);
+ if (IS_ERR(s5kjn5->regmap))
+ return dev_err_probe(dev, PTR_ERR(s5kjn5->regmap),
+ "failed to init CCI regmap\n");
+
+ ret = s5kjn5_power_on(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to power on\n");
+
+ ret = s5kjn5_check_id(s5kjn5);
+ if (ret)
+ goto err_power_off;
+
+ ret = s5kjn5_init_controls(s5kjn5);
+ if (ret)
+ goto err_power_off;
+
+ s5kjn5->sd.internal_ops = &s5kjn5_internal_ops;
+ s5kjn5->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ s5kjn5->sd.entity.ops = &s5kjn5_entity_ops;
+ s5kjn5->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ s5kjn5->pad.flags = MEDIA_PAD_FL_SOURCE;
+
+ ret = media_entity_pads_init(&s5kjn5->sd.entity, 1, &s5kjn5->pad);
+ if (ret)
+ goto err_controls;
+
+ s5kjn5->sd.state_lock = s5kjn5->ctrl_handler.lock;
+
+ ret = v4l2_subdev_init_finalize(&s5kjn5->sd);
+ if (ret)
+ goto err_entity;
+
+ pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+
+ ret = v4l2_async_register_subdev_sensor(&s5kjn5->sd);
+ if (ret) {
+ dev_err(dev, "failed to register subdev: %d\n", ret);
+ goto err_pm;
+ }
+
+ pm_runtime_set_autosuspend_delay(dev, 1000);
+ pm_runtime_use_autosuspend(dev);
+ pm_runtime_idle(dev);
+
+ dev_info(dev, "S5KJN5 sensor detected (chip ID 0x%04x)\n",
+ S5KJN5_CHIP_ID);
+
+ return 0;
+
+err_pm:
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+err_entity:
+ media_entity_cleanup(&s5kjn5->sd.entity);
+ v4l2_subdev_cleanup(&s5kjn5->sd);
+err_controls:
+ v4l2_ctrl_handler_free(&s5kjn5->ctrl_handler);
+err_power_off:
+ s5kjn5_power_off(dev);
+ return ret;
+}
+
+static void s5kjn5_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct device *dev = &client->dev;
+
+ v4l2_async_unregister_subdev(sd);
+ v4l2_subdev_cleanup(sd);
+ v4l2_ctrl_handler_free(sd->ctrl_handler);
+ media_entity_cleanup(&sd->entity);
+
+ pm_runtime_dont_use_autosuspend(dev);
+ pm_runtime_disable(dev);
+
+ if (!pm_runtime_status_suspended(dev)) {
+ s5kjn5_power_off(dev);
+ pm_runtime_set_suspended(dev);
+ }
+}
+
+static const struct dev_pm_ops s5kjn5_pm_ops = {
+ SET_RUNTIME_PM_OPS(s5kjn5_power_off, s5kjn5_power_on, NULL)
+};
+
+static const struct of_device_id s5kjn5_of_match[] = {
+ { .compatible = "samsung,s5kjn5" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, s5kjn5_of_match);
+
+static struct i2c_driver s5kjn5_i2c_driver = {
+ .driver = {
+ .name = "s5kjn5",
+ .pm = pm_ptr(&s5kjn5_pm_ops),
+ .of_match_table = s5kjn5_of_match,
+ },
+ .probe = s5kjn5_probe,
+ .remove = s5kjn5_remove,
+};
+
+module_i2c_driver(s5kjn5_i2c_driver);
+
+MODULE_AUTHOR("Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>");
+MODULE_DESCRIPTION("Samsung S5KJN5 50 MP GBRG 10-bit RAW sensor driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2 4/5] riscv: dts: thead: Add IO labels for the IO expansion on I2C1
From: Icenowy Zheng @ 2026-07-17 4:11 UTC (permalink / raw)
To: Drew Fustini, Icenowy Zheng
Cc: Guo Ren, Fu Wei, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
MoeLeak, Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv,
devicetree, linux-kernel, Emil Renner Berthing
In-Reply-To: <allEg/A+Gt/em0Hs@x1>
于 2026年7月17日 GMT+08:00 04:52:19，Drew Fustini <fustini@kernel.org> 写道：
>On Tue, Jul 14, 2026 at 03:45:14PM +0800, Icenowy Zheng wrote:
>> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>>
>> Add labels for GPIOs on the IO expansion chip on the I2C1 bus.
>>
>> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> [Icenowy: Splitted off the patch adding all 3 IO expansions]
>> Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
>> ---
>> arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>> index 74b120c6b063a..78f5979a56c14 100644
>> --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>> @@ -128,6 +128,14 @@ ioexp2: gpio@18 {
>> reg = <0x18>;
>> gpio-controller;
>> #gpio-cells = <2>;
>> + gpio-line-names = "",
>> + "cam0_reset",
>> + "cam1_reset",
>> + "cam2_reset",
>> + "wl_host_wake",
>
>I am not sure the line name really matters all that, but it seems that
>pin 4 is also used as a reset gpio:
The "host" here is subject, which means "this pins is used by the host to wake the wl".
Maybe I should take the schematics name, "wl_host_wake_dev"? Or use another name on the page for Wi-Fi, "wl_reg_on"?
Thanks,
Icenowy
>
> wifi_pwrseq: wifi-pwrseq {
> compatible = "mmc-pwrseq-simple";
> reset-gpios = <&ioexp2 4 GPIO_ACTIVE_LOW>;
> post-power-on-delay-ms = <200>;
> };
>
>Did you notice that too?
>
>Thanks,
>Drew
^ permalink raw reply
* [PATCH v3 0/2] clk: qcom: Add video clock controller support for Qualcomm Maili SoC
From: Jagadeesh Kona @ 2026-07-17 4:14 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Taniya Das,
Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona, Konrad Dybcio
This series adds support for the video clock controller (videocc)
required by the upcoming Qualcomm Maili SoC.
This series is dependent on Maili GCC clock series:
https://lore.kernel.org/all/20260713-maili_initial_clock-v2-0-79548f0bb58f@oss.qualcomm.com/
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
Changes in v3:
- Fixed the spaces indendation for VIDEO_CC_MVS0C_FREERUN_CLK_ARES
in maili videocc header file [Sashiko AI review].
- Used GENMASK to define .mem_enable_ack_mask field in videocc maili
driver
- Link to v2: https://lore.kernel.org/r/20260716-maili_videocc-v2-0-7ed5ab140770@oss.qualcomm.com
Changes in v2:
- Rebased on latest linux-next
- Dropped the explicit compatible check for required-opps in bindings,
as it is already handled by default in the latest linux-next. [Krzysztof]
- Added R-By tag received on v1
- Link to v1: https://lore.kernel.org/r/20260707-maili_videocc-v1-0-ef0828c0bf6e@oss.qualcomm.com
---
Jagadeesh Kona (2):
dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
.../bindings/clock/qcom,sm8450-videocc.yaml | 2 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-maili.c | 660 +++++++++++++++++++++
include/dt-bindings/clock/qcom,maili-videocc.h | 50 ++
5 files changed, 723 insertions(+)
---
base-commit: 1a1757b76427f6201bfe0bf1bea9f7574f332a93
change-id: 20260707-maili_videocc-db0d6ee94cb7
prerequisite-change-id: 20260617-maili_initial_clock-c7e2b4530d80:v2
prerequisite-patch-id: cb2499a822715bf6d411ea000e525e5feab52e7f
prerequisite-patch-id: 4280283ee9f782a5ba46e4419ab0b7186add0211
prerequisite-patch-id: 3e9a75794efb1633818ffe387d1f4e5048c361a4
prerequisite-patch-id: 9a218f161a75924b8cc3fbae44007d0da7739d60
prerequisite-patch-id: 7e5ac7db1fba3258b45b689b11d0ca93d65aa38a
Best regards,
--
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
From: Jagadeesh Kona @ 2026-07-17 4:14 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Taniya Das,
Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona
In-Reply-To: <20260717-maili_videocc-v3-0-6656694b06a7@oss.qualcomm.com>
Add device tree bindings for the video clock controller on Qualcomm
Maili SoC.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
.../bindings/clock/qcom,sm8450-videocc.yaml | 2 +
include/dt-bindings/clock/qcom,maili-videocc.h | 50 ++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index 1e1fec1cd7ce96f103348baf85341e775fac690a..910c6d5672b8657f161058c4ceba98637c299b73 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -18,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,hawi-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
+ include/dt-bindings/clock/qcom,maili-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@@ -29,6 +30,7 @@ properties:
- qcom,glymur-videocc
- qcom,hawi-videocc
- qcom,kaanapali-videocc
+ - qcom,maili-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
diff --git a/include/dt-bindings/clock/qcom,maili-videocc.h b/include/dt-bindings/clock/qcom,maili-videocc.h
new file mode 100644
index 0000000000000000000000000000000000000000..f8461048b04d43cc39606b415273c17eb5106dcf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,maili-videocc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK 0
+#define VIDEO_CC_AHB_CLK_SRC 1
+#define VIDEO_CC_MVS0_CLK 2
+#define VIDEO_CC_MVS0_CLK_SRC 3
+#define VIDEO_CC_MVS0_FREERUN_CLK 4
+#define VIDEO_CC_MVS0_SHIFT_CLK 5
+#define VIDEO_CC_MVS0_VPP0_CLK 6
+#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7
+#define VIDEO_CC_MVS0B_CLK 8
+#define VIDEO_CC_MVS0B_CLK_SRC 9
+#define VIDEO_CC_MVS0B_FREERUN_CLK 10
+#define VIDEO_CC_MVS0C_CLK 11
+#define VIDEO_CC_MVS0C_CLK_SRC 12
+#define VIDEO_CC_MVS0C_DEBUG_CLK 13
+#define VIDEO_CC_MVS0C_FREERUN_CLK 14
+#define VIDEO_CC_MVS0C_SHIFT_CLK 15
+#define VIDEO_CC_PLL0 16
+#define VIDEO_CC_PLL1 17
+#define VIDEO_CC_PLL2 18
+#define VIDEO_CC_SLEEP_CLK 19
+#define VIDEO_CC_TS_XO_CLK 20
+#define VIDEO_CC_XO_CLK 21
+#define VIDEO_CC_XO_CLK_SRC 22
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC 0
+#define VIDEO_CC_MVS0_VPP0_GDSC 1
+#define VIDEO_CC_MVS0C_GDSC 2
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR 0
+#define VIDEO_CC_MVS0_BCR 1
+#define VIDEO_CC_MVS0_CLK_ARES 2
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 3
+#define VIDEO_CC_MVS0_VPP0_BCR 4
+#define VIDEO_CC_MVS0C_BCR 5
+#define VIDEO_CC_MVS0C_CLK_ARES 6
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 7
+#define VIDEO_CC_XO_CLK_ARES 8
+
+#endif
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 2/2] media: i2c: Add Samsung S5KJN5 image sensor driver
From: sashiko-bot @ 2026-07-17 4:19 UTC (permalink / raw)
To: Wenmeng Liu; +Cc: devicetree, conor+dt, robh, media-ci
In-Reply-To: <20260717-sk5jn5-v1-2-da610d7fd494@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect hardware power-on/off sequence: reset is de-asserted without a running clock.
--
--- Patch [2]: [PATCH 2/2] media: i2c: Add Samsung S5KJN5 image sensor driver ---
commit 05e0426a4b9d13689d0f80d9c414692c4736124c
Author: Wenmeng Liu <wenmeng.liu@oss.qualcomm.com>
media: i2c: Add Samsung S5KJN5 image sensor driver
This commit adds a V4L2 sub-device driver for the Samsung S5KJN5 image
sensor. It supports the 4096x3072 mode and exposes standard controls for
exposure, gain, blanking, and test patterns.
> diff --git a/drivers/media/i2c/s5kjn5.c b/drivers/media/i2c/s5kjn5.c
> new file mode 100644
> index 0000000000000..294a4c3c5d2c5
> --- /dev/null
> +++ b/drivers/media/i2c/s5kjn5.c
[ ... ]
> +static int s5kjn5_power_on(struct device *dev)
> +{
> + struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
> + int ret;
> +
> + ret = regulator_bulk_enable(S5KJN5_NUM_SUPPLIES, s5kjn5->supplies);
> + if (ret) {
> + dev_err(dev, "failed to enable regulators: %d\n", ret);
> + return ret;
> + }
> +
> + gpiod_set_value_cansleep(s5kjn5->reset_gpio, 0);
> + usleep_range(8000, 10000);
> +
> + ret = clk_prepare_enable(s5kjn5->inclk);
[Severity: High]
Does this sequence de-assert the reset line before the master clock is
running? Releasing reset without an active master clock can sometimes cause
the sensor's internal state machines to enter an undefined or locked-up
state, which might lead to I2C communication failures or unreliable
initialization.
[ ... ]
> +static int s5kjn5_power_off(struct device *dev)
> +{
> + struct v4l2_subdev *sd = dev_get_drvdata(dev);
> + struct s5kjn5 *s5kjn5 = sd_to_s5kjn5(sd);
> +
> + clk_disable_unprepare(s5kjn5->inclk);
> + gpiod_set_value_cansleep(s5kjn5->reset_gpio, 1);
[Severity: High]
Similarly, does this stop the clock before placing the sensor back into
reset? Typically, the sensor should be placed into reset while the clock is
still running to ensure a clean shutdown state.
> + regulator_bulk_disable(S5KJN5_NUM_SUPPLIES, s5kjn5->supplies);
> +
> + return 0;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-sk5jn5-v1-0-da610d7fd494@oss.qualcomm.com?part=2
^ permalink raw reply
* [PATCH v3 2/2] clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
From: Jagadeesh Kona @ 2026-07-17 4:14 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Taniya Das,
Jagadeesh Kona
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel,
Jagadeesh Kona, Konrad Dybcio
In-Reply-To: <20260717-maili_videocc-v3-0-6656694b06a7@oss.qualcomm.com>
Add support for Qualcomm Maili video clock controller driver for
video clients to be able to request for videocc clocks.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-maili.c | 660 +++++++++++++++++++++++++++++++++++++++
3 files changed, 671 insertions(+)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 63f271aff1771bea0885fb753dd28d02fd7d4ab6..690f0b6fe227ca449274d3606f7ca6a9da23a5ab 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -181,6 +181,16 @@ config CLK_KAANAPALI_VIDEOCC
Say Y if you want to support video devices and functionality such as
video encode/decode.
+config CLK_MAILI_VIDEOCC
+ tristate "Maili Video Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ select CLK_HAWI_GCC
+ default m if ARCH_QCOM
+ help
+ Support for the video clock controller on Maili devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode/decode.
+
config CLK_NORD_GCC
tristate "Nord Global Clock Controller"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index db7689ee5dc63bc8b7d12b8222188bc1e1ff78ba..bb5e3dc7073340f895d3e1108f243c8d66b84b4f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
+obj-$(CONFIG_CLK_MAILI_VIDEOCC) += videocc-maili.o
obj-$(CONFIG_CLK_NORD_GCC) += gcc-nord.o negcc-nord.o nwgcc-nord.o segcc-nord.o
obj-$(CONFIG_CLK_NORD_TCSRCC) += tcsrcc-nord.o
obj-$(CONFIG_CLK_SHIKRA_GCC) += gcc-shikra.o
diff --git a/drivers/clk/qcom/videocc-maili.c b/drivers/clk/qcom/videocc-maili.c
new file mode 100644
index 0000000000000000000000000000000000000000..a7044009f078a9a36c8cf6914443415ed8a31118
--- /dev/null
+++ b/drivers/clk/qcom/videocc-maili.c
@@ -0,0 +1,660 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,maili-videocc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+#define ACCU_CFG_MASK GENMASK(25, 21)
+
+enum {
+ DT_BI_TCXO,
+ DT_AHB_CLK,
+};
+
+enum {
+ P_BI_TCXO,
+ P_VIDEO_CC_PLL0_OUT_MAIN,
+ P_VIDEO_CC_PLL1_OUT_MAIN,
+ P_VIDEO_CC_PLL2_OUT_MAIN,
+};
+
+static const struct pll_vco taycan_eha_t_vco[] = {
+ { 249600000, 2500000000, 0 },
+};
+
+/* 360.0 MHz Configuration */
+static const struct alpha_pll_config video_cc_pll0_config = {
+ .l = 0x12,
+ .cal_l = 0x42,
+ .alpha = 0xc000,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000002,
+};
+
+static struct clk_alpha_pll video_cc_pll0 = {
+ .offset = 0x0,
+ .config = &video_cc_pll0_config,
+ .vco_table = taycan_eha_t_vco,
+ .num_vco = ARRAY_SIZE(taycan_eha_t_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_pll0",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_taycan_eha_t_ops,
+ },
+ },
+};
+
+/* 480.0 MHz Configuration */
+static const struct alpha_pll_config video_cc_pll1_config = {
+ .l = 0x19,
+ .cal_l = 0x42,
+ .alpha = 0x0,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000002,
+};
+
+static struct clk_alpha_pll video_cc_pll1 = {
+ .offset = 0x1000,
+ .config = &video_cc_pll1_config,
+ .vco_table = taycan_eha_t_vco,
+ .num_vco = ARRAY_SIZE(taycan_eha_t_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_pll1",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_taycan_eha_t_ops,
+ },
+ },
+};
+
+/* 480.0 MHz Configuration */
+static const struct alpha_pll_config video_cc_pll2_config = {
+ .l = 0x19,
+ .cal_l = 0x42,
+ .alpha = 0x0,
+ .config_ctl_val = 0xa5c400e7,
+ .config_ctl_hi_val = 0x0a806160,
+ .config_ctl_hi1_val = 0xf51dea20,
+ .user_ctl_val = 0x00000000,
+ .user_ctl_hi_val = 0x00000002,
+};
+
+static struct clk_alpha_pll video_cc_pll2 = {
+ .offset = 0x2000,
+ .config = &video_cc_pll2_config,
+ .vco_table = taycan_eha_t_vco,
+ .num_vco = ARRAY_SIZE(taycan_eha_t_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T],
+ .clkr = {
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_pll2",
+ .parent_data = &(const struct clk_parent_data) {
+ .index = DT_BI_TCXO,
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_taycan_eha_t_ops,
+ },
+ },
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_0[] = {
+ { .index = DT_BI_TCXO },
+};
+
+static const struct parent_map video_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_CC_PLL1_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_1[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &video_cc_pll1.clkr.hw },
+};
+
+static const struct parent_map video_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_CC_PLL2_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_2[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &video_cc_pll2.clkr.hw },
+};
+
+static const struct parent_map video_cc_parent_map_3[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_3[] = {
+ { .index = DT_BI_TCXO },
+ { .hw = &video_cc_pll0.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
+ F(19200000, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_ahb_clk_src = {
+ .cmd_rcgr = 0x8060,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_0,
+ .freq_tbl = ftbl_video_cc_ahb_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_ahb_clk_src",
+ .parent_data = video_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
+ F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(600000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_mvs0_clk_src = {
+ .cmd_rcgr = 0x8030,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_1,
+ .freq_tbl = ftbl_video_cc_mvs0_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_clk_src",
+ .parent_data = video_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] = {
+ F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ F(800000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_mvs0b_clk_src = {
+ .cmd_rcgr = 0x8018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_2,
+ .freq_tbl = ftbl_video_cc_mvs0b_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0b_clk_src",
+ .parent_data = video_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] = {
+ F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_mvs0c_clk_src = {
+ .cmd_rcgr = 0x8048,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_3,
+ .freq_tbl = ftbl_video_cc_mvs0c_clk_src,
+ .hw_clk_ctrl = true,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_clk_src",
+ .parent_data = video_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 video_cc_xo_clk_src = {
+ .cmd_rcgr = 0x8194,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_0,
+ .freq_tbl = ftbl_video_cc_ahb_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_xo_clk_src",
+ .parent_data = video_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch video_cc_mvs0_clk = {
+ .halt_reg = 0x80d0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x80d0,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x80d0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_mem_branch video_cc_mvs0_freerun_clk = {
+ .mem_enable_reg = 0x80e4,
+ .mem_ack_reg = 0x80e4,
+ .mem_enable_mask = BIT(3),
+ .mem_enable_ack_mask = GENMASK(11, 10),
+ .mem_enable_invert = true,
+ .branch = {
+ .halt_reg = 0x80e0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x80e0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_freerun_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_mem_ops,
+ },
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0_shift_clk = {
+ .halt_reg = 0x81b4,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x81b4,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x81b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0_vpp0_clk = {
+ .halt_reg = 0x8134,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8134,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8134,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_vpp0_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0_vpp0_freerun_clk = {
+ .halt_reg = 0x8144,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8144,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0_vpp0_freerun_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0b_clk = {
+ .halt_reg = 0x80bc,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x80bc,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x80bc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0b_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0b_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0b_freerun_clk = {
+ .halt_reg = 0x80cc,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x80cc,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0b_freerun_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0b_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0c_clk = {
+ .halt_reg = 0x8164,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x8164,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x8164,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0c_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0c_debug_clk = {
+ .halt_reg = 0x81c0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x81c0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_debug_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0c_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0c_freerun_clk = {
+ .halt_reg = 0x8174,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8174,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_freerun_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_mvs0c_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0c_shift_clk = {
+ .halt_reg = 0x81b8,
+ .halt_check = BRANCH_HALT_VOTED,
+ .hwcg_reg = 0x81b8,
+ .hwcg_bit = 1,
+ .clkr = {
+ .enable_reg = 0x81b8,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "video_cc_mvs0c_shift_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &video_cc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc video_cc_mvs0c_gdsc = {
+ .gdscr = 0x814c,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x6,
+ .pd = {
+ .name = "video_cc_mvs0c_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc video_cc_mvs0_gdsc = {
+ .gdscr = 0x80a8,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0x6,
+ .pd = {
+ .name = "video_cc_mvs0_gdsc",
+ },
+ .parent = &video_cc_mvs0c_gdsc.pd,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc video_cc_mvs0_vpp0_gdsc = {
+ .gdscr = 0x8120,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
+ .pd = {
+ .name = "video_cc_mvs0_vpp0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *video_cc_maili_clocks[] = {
+ [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
+ [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
+ [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
+ [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.branch.clkr,
+ [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
+ [VIDEO_CC_MVS0_VPP0_CLK] = &video_cc_mvs0_vpp0_clk.clkr,
+ [VIDEO_CC_MVS0_VPP0_FREERUN_CLK] = &video_cc_mvs0_vpp0_freerun_clk.clkr,
+ [VIDEO_CC_MVS0B_CLK] = &video_cc_mvs0b_clk.clkr,
+ [VIDEO_CC_MVS0B_CLK_SRC] = &video_cc_mvs0b_clk_src.clkr,
+ [VIDEO_CC_MVS0B_FREERUN_CLK] = &video_cc_mvs0b_freerun_clk.clkr,
+ [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
+ [VIDEO_CC_MVS0C_CLK_SRC] = &video_cc_mvs0c_clk_src.clkr,
+ [VIDEO_CC_MVS0C_DEBUG_CLK] = &video_cc_mvs0c_debug_clk.clkr,
+ [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
+ [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
+ [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
+ [VIDEO_CC_PLL1] = &video_cc_pll1.clkr,
+ [VIDEO_CC_PLL2] = &video_cc_pll2.clkr,
+ [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
+};
+
+static struct gdsc *video_cc_maili_gdscs[] = {
+ [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
+ [VIDEO_CC_MVS0_VPP0_GDSC] = &video_cc_mvs0_vpp0_gdsc,
+ [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
+};
+
+static const struct qcom_reset_map video_cc_maili_resets[] = {
+ [VIDEO_CC_INTERFACE_BCR] = { 0x8178 },
+ [VIDEO_CC_MVS0_BCR] = { 0x80a4 },
+ [VIDEO_CC_MVS0_CLK_ARES] = { 0x80d0, 2 },
+ [VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x80e0, 2 },
+ [VIDEO_CC_MVS0_VPP0_BCR] = { 0x811c },
+ [VIDEO_CC_MVS0C_BCR] = { 0x8148 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8164, 2 },
+ [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x8174, 2 },
+ [VIDEO_CC_XO_CLK_ARES] = { 0x81ac, 2 },
+};
+
+static struct clk_alpha_pll *video_cc_maili_plls[] = {
+ &video_cc_pll0,
+ &video_cc_pll1,
+ &video_cc_pll2,
+};
+
+static const u32 video_cc_maili_critical_cbcrs[] = {
+ 0x817c, /* VIDEO_CC_AHB_CLK */
+ 0x81bc, /* VIDEO_CC_SLEEP_CLK */
+ 0x81b0, /* VIDEO_CC_TS_XO_CLK */
+ 0x81ac, /* VIDEO_CC_XO_CLK */
+};
+
+static const struct regmap_config video_cc_maili_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0xa010,
+ .fast_io = true,
+};
+
+static void clk_maili_regs_configure(struct device *dev, struct regmap *regmap)
+{
+ /*
+ * Enable clk_on sync for MVS0 and VPP clocks as per the
+ * hardware recommendation.
+ */
+ regmap_set_bits(regmap, 0x9f24, BIT(0));
+
+ /*
+ * Update ACCU configuration for MVS0 CFG3, MVS0 VPP0 CFG3,
+ * MVS0C CFG3 GDSCRs as per the hardware recommendation.
+ */
+ regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK);
+ regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK);
+ regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK);
+}
+
+static const struct qcom_cc_driver_data video_cc_maili_driver_data = {
+ .alpha_plls = video_cc_maili_plls,
+ .num_alpha_plls = ARRAY_SIZE(video_cc_maili_plls),
+ .clk_cbcrs = video_cc_maili_critical_cbcrs,
+ .num_clk_cbcrs = ARRAY_SIZE(video_cc_maili_critical_cbcrs),
+ .clk_regs_configure = clk_maili_regs_configure,
+};
+
+static const struct qcom_cc_desc video_cc_maili_desc = {
+ .config = &video_cc_maili_regmap_config,
+ .clks = video_cc_maili_clocks,
+ .num_clks = ARRAY_SIZE(video_cc_maili_clocks),
+ .resets = video_cc_maili_resets,
+ .num_resets = ARRAY_SIZE(video_cc_maili_resets),
+ .gdscs = video_cc_maili_gdscs,
+ .num_gdscs = ARRAY_SIZE(video_cc_maili_gdscs),
+ .use_rpm = true,
+ .driver_data = &video_cc_maili_driver_data,
+};
+
+static const struct of_device_id video_cc_maili_match_table[] = {
+ { .compatible = "qcom,maili-videocc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, video_cc_maili_match_table);
+
+static int video_cc_maili_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &video_cc_maili_desc);
+}
+
+static struct platform_driver video_cc_maili_driver = {
+ .probe = video_cc_maili_probe,
+ .driver = {
+ .name = "videocc-maili",
+ .of_match_table = video_cc_maili_match_table,
+ },
+};
+
+module_platform_driver(video_cc_maili_driver);
+
+MODULE_DESCRIPTION("QTI VIDEOCC Maili Driver");
+MODULE_LICENSE("GPL");
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v3 2/2] clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
From: sashiko-bot @ 2026-07-17 4:28 UTC (permalink / raw)
To: Jagadeesh Kona; +Cc: conor+dt, devicetree, robh
In-Reply-To: <20260717-maili_videocc-v3-2-6656694b06a7@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] CLK_MAILI_VIDEOCC incorrectly selects CLK_HAWI_GCC instead of a Maili-specific Global Clock Controller.
--
--- Patch [2]: [PATCH v3 2/2] clk: qcom: Add support for videocc driver on Qualcomm Maili SoC ---
commit 3279b9315bb8b961f7460eb907c8f81979b2b267
Author: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
This commit adds support for the Qualcomm Maili video clock controller
driver. It introduces the new videocc-maili module and its Kconfig entry
for devices requiring video encode/decode clock functionalities.
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 63f271aff1771..690f0b6fe227c 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -181,6 +181,16 @@ config CLK_KAANAPALI_VIDEOCC
> Say Y if you want to support video devices and functionality such as
> video encode/decode.
>
> +config CLK_MAILI_VIDEOCC
> + tristate "Maili Video Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + select CLK_HAWI_GCC
[Severity: Low]
Is this select statement accurate? The CLK_MAILI_VIDEOCC config appears to
select CLK_HAWI_GCC, which seems to be a Global Clock Controller for the Hawi
platform rather than Maili.
Could this be a copy-paste error that should instead select a Maili-specific
GCC?
> + default m if ARCH_QCOM
> + help
> + Support for the video clock controller on Maili devices.
> + Say Y if you want to support video devices and functionality such as
> + video encode/decode.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-maili_videocc-v3-0-6656694b06a7@oss.qualcomm.com?part=2
^ permalink raw reply
* Re: [PATCH v7 11/18] media: iris: Add framework support for AR50_LITE video core
From: Vishnu Reddy @ 2026-07-17 4:30 UTC (permalink / raw)
To: Dmitry Baryshkov, Vikash Garodia, Abhinav Kumar,
Bryan O'Donoghue, Mauro Carvalho Chehab, Bjorn Andersson,
Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-arm-msm, linux-kernel, devicetree,
Dikshita Agarwal
In-Reply-To: <20260709-iris-ar50lt-v7-11-76af9dd4d1f6@oss.qualcomm.com>
On 7/9/2026 7:12 PM, Dmitry Baryshkov wrote:
> From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
>
> Add power sequence for ar5lt core.
> Add register handling for ar50lt by hooking up vpu op with ar50lt
> specific implemtation or resue from earlier generation wherever
> feasible.
>
> Signed-off-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/Makefile | 1 +
> .../platform/qcom/iris/iris_platform_common.h | 2 +
> drivers/media/platform/qcom/iris/iris_vpu2.c | 28 +----
> drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 130 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 29 ++++-
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 +
> 6 files changed, 164 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
> index 48e415cbc439..f1b204b95694 100644
> --- a/drivers/media/platform/qcom/iris/Makefile
> +++ b/drivers/media/platform/qcom/iris/Makefile
> @@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \
> iris_vpu2.o \
> iris_vpu3x.o \
> iris_vpu4x.o \
> + iris_vpu_ar50lt.o \
> iris_vpu_buffer.o \
> iris_vpu_common.o \
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index accc1627defd..6a189489369f 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -74,6 +74,7 @@ enum platform_clk_type {
> IRIS_VPP0_HW_CLK,
> IRIS_VPP1_HW_CLK,
> IRIS_APV_HW_CLK,
> + IRIS_THROTTLE_CLK,
> };
>
> struct platform_clk_data {
> @@ -315,6 +316,7 @@ struct iris_platform_data {
> u32 tz_cp_config_data_size;
> u32 num_vpp_pipe;
> bool no_aon;
> + bool no_rpmh;
> u32 wd_intr_mask;
> u32 icc_ib_multiplier;
> u32 max_session_count;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/platform/qcom/iris/iris_vpu2.c
> index dd2eeae0d9eb..5419a5096b00 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu2.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c
> @@ -12,38 +12,12 @@
>
> #include "iris_vpu_register_defines.h"
>
> -static u64 iris_vpu2_calc_freq(struct iris_inst *inst, size_t data_size)
> -{
> - struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> - struct v4l2_format *inp_f = inst->fmt_src;
> - u32 mbs_per_second, mbpf, height, width;
> - unsigned long vpp_freq, vsp_freq;
> - u32 fps = inst->frame_rate;
> -
> - width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
> - height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
> -
> - mbpf = NUM_MBS_PER_FRAME(height, width);
> - mbs_per_second = mbpf * fps;
> -
> - vpp_freq = mbs_per_second * caps->mb_cycles_vpp;
> -
> - /* 21 / 20 is overhead factor */
> - vpp_freq += vpp_freq / 20;
> - vsp_freq = mbs_per_second * caps->mb_cycles_vsp;
> -
> - /* 10 / 7 is overhead factor */
> - vsp_freq += ((fps * data_size * 8) * 10) / 7;
> -
> - return max(vpp_freq, vsp_freq);
> -}
> -
> const struct vpu_ops iris_vpu2_ops = {
> .power_off_hw = iris_vpu_power_off_hw,
> .power_on_hw = iris_vpu_power_on_hw,
> .power_off_controller = iris_vpu_power_off_controller,
> .power_on_controller = iris_vpu_power_on_controller,
> - .calc_freq = iris_vpu2_calc_freq,
> + .calc_freq = iris_vpu2_calculate_frequency,
> .set_hwmode = iris_vpu_set_hwmode,
> .set_preset_registers = iris_vpu_set_preset_registers,
> .interrupt_init = iris_vpu_interrupt_init,
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
> new file mode 100644
> index 000000000000..e084a5b49f2e
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/iopoll.h>
> +#include <linux/reset.h>
> +
> +#include "iris_instance.h"
> +#include "iris_vpu_common.h"
> +
> +#include "iris_vpu_register_defines.h"
> +
> +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3)
> +
> +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080
> +
> +#define CPU_CS_VCICMD 0xa0020
> +#define CPU_CS_VCICMD_ARP_OFF 0x1
> +
> +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core)
> +{
> + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT);
> +}
> +
> +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core)
> +{
> + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK);
> +}
> +
> +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core)
> +{
> + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD);
> +}
> +
> +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core)
> +{
> + iris_disable_unprepare_clock(core, IRIS_AHB_CLK);
> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return 0;
> +}
> +
> +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core)
> +{
> + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false);
> + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK);
> + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> + iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> +}
> +
> +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core)
> +{
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);
> + if (ret && ret != -ENOENT)
> + goto err_disable_ctrl_clock;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK);
> + if (ret)
> + goto err_disable_axi_clock;
> +
> + return 0;
> +
> +err_disable_axi_clock:
> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> +err_disable_ctrl_clock:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
> +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core)
> +{
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK);
> + if (ret)
> + goto err_disable_hw_clock;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK);
> + if (ret)
> + goto err_disable_hw_ahb_clock;
> +
> + return 0;
> +
> +err_disable_hw_ahb_clock:
> + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK);
> +err_disable_hw_clock:
> + iris_disable_unprepare_clock(core, IRIS_HW_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
> +const struct vpu_ops iris_vpu_ar50lt_ops = {
> + .power_off_hw = iris_vpu_ar50lt_power_off_hw,
> + .power_on_hw = iris_vpu_ar50lt_power_on_hw,
> + .power_off_controller = iris_vpu_ar50lt_power_off_controller,
> + .power_on_controller = iris_vpu_ar50lt_power_on_controller,
> + .calc_freq = iris_vpu2_calculate_frequency,
> + .set_hwmode = iris_vpu_set_hwmode,
> + .set_preset_registers = iris_vpu_ar50lt_set_preset_registers,
> + .interrupt_init = iris_vpu_ar50lt_interrupt_init,
> + .disable_arp = iris_vpu_ar50lt_disable_arp,
> +};
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index 41498f94480e..d64e7745a63d 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core)
> }
>
> writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN);
> - writel(0x0, core->reg_base + CPU_CS_X2RPMH);
> + if (!core->iris_platform_data->no_rpmh)
> + writel(0x0, core->reg_base + CPU_CS_X2RPMH);
>
> return 0;
> }
> @@ -422,6 +423,32 @@ void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core)
> writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);
> }
>
> +u64 iris_vpu2_calculate_frequency(struct iris_inst *inst, size_t data_size)
> +{
> + struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> + struct v4l2_format *inp_f = inst->fmt_src;
> + u32 mbs_per_second, mbpf, height, width;
> + unsigned long vpp_freq, vsp_freq;
> + u32 fps = inst->frame_rate;
> +
> + width = max(inp_f->fmt.pix_mp.width, inst->crop.width);
> + height = max(inp_f->fmt.pix_mp.height, inst->crop.height);
> +
> + mbpf = NUM_MBS_PER_FRAME(height, width);
> + mbs_per_second = mbpf * fps;
> +
> + vpp_freq = mbs_per_second * caps->mb_cycles_vpp;
> +
> + /* 21 / 20 is overhead factor */
> + vpp_freq += vpp_freq / 20;
> + vsp_freq = mbs_per_second * caps->mb_cycles_vsp;
> +
> + /* 10 / 7 is overhead factor */
> + vsp_freq += ((fps * data_size * 8) * 10) / 7;
> +
> + return max(vpp_freq, vsp_freq);
> +}
> +
> u64 iris_vpu3x_vpu4x_calculate_frequency(struct iris_inst *inst, size_t data_size)
> {
> struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> index 71d96921ed37..a62b6184bde7 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h
> @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops;
> extern const struct vpu_ops iris_vpu33_ops;
> extern const struct vpu_ops iris_vpu35_ops;
> extern const struct vpu_ops iris_vpu4x_ops;
> +extern const struct vpu_ops iris_vpu_ar50lt_ops;
>
> struct vpu_ops {
> void (*power_off_hw)(struct iris_core *core);
> @@ -40,6 +41,7 @@ int iris_vpu_power_on(struct iris_core *core);
> int iris_vpu_power_off_controller(struct iris_core *core);
> void iris_vpu_power_off_hw(struct iris_core *core);
> void iris_vpu_power_off(struct iris_core *core);
> +u64 iris_vpu2_calculate_frequency(struct iris_inst *inst, size_t data_size);
> int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core);
> int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core);
> void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core);
Reviewed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: qcom: smb2370: Disable SMB2370_2 by default
From: Gopikrishna Garmidi @ 2026-07-17 4:50 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Konrad Dybcio
In-Reply-To: <20260716-topic-smb2370_port2-v1-1-83d02b2ba4b0@oss.qualcomm.com>
On 7/16/2026 11:03 PM, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> It's absent on laptops that only have 2 type-C ports (the majority so
> far, including the CRD). Keep it disabled by default, following
> established practice from the previous generation.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/smb2370.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi
> index 80f3fdae5705..1e02578e4ee3 100644
> --- a/arch/arm64/boot/dts/qcom/smb2370.dtsi
> +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi
> @@ -36,6 +36,8 @@ smb2370_l_e2: pmic@b {
> #address-cells = <1>;
> #size-cells = <0>;
>
> + status = "disabled";
> +
> smb2370_l_e2_eusb2_repeater: phy@fd00 {
> compatible = "qcom,smb2370-eusb2-repeater";
> reg = <0xfd00>;
>
Reviewed-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
^ permalink raw reply
* [PATCH 0/3] Add i.MX93 Wireless FRDM board support
From: Joseph Guo @ 2026-07-17 5:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Joseph Guo
i.MX93 Wireless FRDM board(FRDM-IMX93W) is a low-cost and compact board featuring
the i.MX93W applications processor
FRDM-IMX93W board basically reuse the FRDM-IMX93 board, with some minor functional
and pin connection differences. Factor common parts of FRDM-IMX93 and FRDM-IMX93W
into imx93-11x11-frdm-common.dtsi and add the board-specific changes.
Signed-off-by: Joseph Guo <qijian.guo@nxp.com>
---
Joseph Guo (3):
arm64: dts: imx93-11x11-frdm: factor out common parts into dtsi
dt-bindings: arm: fsl: Add i.MX93 Wireless FRDM board
arm64: dts: imx93: Add i.MX93 Wireless FRDM board support
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-11x11-frdm-common.dtsi | 692 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts | 686 +-------------------
arch/arm64/boot/dts/freescale/imx93w-frdm.dts | 23 +
5 files changed, 719 insertions(+), 684 deletions(-)
---
base-commit: b8809969e1d7a591e0f49dd464a5d04b3cf02ab1
change-id: 20260716-imx93w_frdm-2528ada72343
Best regards,
--
Joseph Guo <qijian.guo@nxp.com>
^ permalink raw reply
* [PATCH 1/3] arm64: dts: imx93-11x11-frdm: factor out common parts into dtsi
From: Joseph Guo @ 2026-07-17 5:11 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Joseph Guo
In-Reply-To: <20260717-imx93w_frdm-v1-0-0cca6c0ba2f5@nxp.com>
The i.MX93 Wireless FRDM board reuses most of the i.MX93 FRDM board.
To avoid duplication and DTS-to-DTS includes, extract common hardware
definitions from imx93-11x11-frdm.dts into imx93-11x11-frdm-common.dtsi
to allow the common description shared by both boards.
The FRDM-IMX93 board-specific .dts now includes the common dtsi and only
contains board-specific overrides.
Signed-off-by: Joseph Guo <qijian.guo@nxp.com>
---
.../dts/freescale/imx93-11x11-frdm-common.dtsi | 692 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts | 686 +-------------------
2 files changed, 694 insertions(+), 684 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-common.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..69e23570f71f40a3f3517d31e16a9ca1d3dfb1f2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm-common.dtsi
@@ -0,0 +1,692 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/usb/pd.h>
+
+/ {
+
+ aliases {
+ can0 = &flexcan2;
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ mmc0 = &usdhc1; /* EMMC */
+ mmc1 = &usdhc2; /* uSD */
+ rtc0 = &pcf2131;
+ serial0 = &lpuart1;
+ serial4 = &lpuart5;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ flexcan2_phy: can-phy {
+ compatible = "nxp,tja1051";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-k2 {
+ label = "Button K2";
+ linux,code = <BTN_1>;
+ gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ };
+
+ button-k3 {
+ label = "Button K3";
+ linux,code = <BTN_2>;
+ gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "VSD_3V3";
+ vin-supply = <&buck4>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x80000000 0 0x30000000>;
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021e000 {
+ reg = <0 0x2021e000 0 0x1000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4010000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+ };
+};
+
+&adc1 {
+ vref-supply = <&buck5>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&cm33 {
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-1 = <&pinctrl_eqos_sleep>;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec>;
+ pinctrl-1 = <&pinctrl_fec_sleep>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&flexcan2 {
+ phys = <&flexcan2_phy>;
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6408: gpio@20 {
+ compatible = "nxp,pcal6408";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ /* does not boot with supplier set, because it is the bucks interrupt parent */
+ /* vcc-supply = <&buck4>; */
+ };
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+
+ buck1: BUCK1 {
+ regulator-name = "VDD_SOC_0V8";
+ regulator-min-microvolt = <610000>;
+ regulator-max-microvolt = <950000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "LPD4_x_VDDQ_0V6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <670000>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "VDD_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "LPD4_x_VDD2_1V1";
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1140000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "NVCC_BBSM_1V8";
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "VDD_ANA_0V8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <840000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "NVCC_SD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ pagesize = <64>;
+ vcc-supply = <&buck4>;
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lpuart5 {
+ pinctrl-0 = <&pinctrl_uart5>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_usdhc3_vmmc>;
+ };
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ disable-over-current;
+ dr_mode = "host";
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&buck4>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_eqos_sleep: eqossleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
+ MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
+ MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
+ MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
+ MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
+ MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
+ MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
+ MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
+ MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
+ MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
+ MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
+ MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
+ MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
+ MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_fec_sleep: fecsleepgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
+ MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
+ MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
+ MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
+ MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
+ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
+ MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
+ MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
+ MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
+ MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
+ MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
+ MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
+ MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
+ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2_sleep: flexcan2sleepgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
+ MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
+ MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
+ MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ /* need to config the SION for data and cmd pad, refer to ERR052021 */
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
+ MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
+ MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
+ MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
+ MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
+ MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
+ MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
index bd14ba28690c081817111aaabef12fb56a7c56a4..f2a31a0eacabff07532aee989eebd75a0c3e22e0 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts
@@ -1,71 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
/dts-v1/;
-#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"
+#include "imx93-11x11-frdm-common.dtsi"
/ {
compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
model = "NXP i.MX93 11X11 FRDM board";
- aliases {
- can0 = &flexcan2;
- ethernet0 = &fec;
- ethernet1 = &eqos;
- i2c0 = &lpi2c1;
- i2c1 = &lpi2c2;
- i2c2 = &lpi2c3;
- mmc0 = &usdhc1; /* EMMC */
- mmc1 = &usdhc2; /* uSD */
- rtc0 = &pcf2131;
- serial0 = &lpuart1;
- serial4 = &lpuart5;
- };
-
- chosen {
- stdout-path = &lpuart1;
- };
-
- flexcan2_phy: can-phy {
- compatible = "nxp,tja1051";
- #phy-cells = <0>;
- max-bitrate = <5000000>;
- silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- button-k2 {
- label = "Button K2";
- linux,code = <BTN_1>;
- gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- interrupt-parent = <&pcal6524>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- };
-
- button-k3 {
- label = "Button K3";
- linux,code = <BTN_2>;
- gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
- interrupt-parent = <&pcal6524>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
- };
- };
-
- reg_usdhc2_vmmc: regulator-usdhc2 {
- compatible = "regulator-fixed";
- off-on-delay-us = <12000>;
- pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
- pinctrl-names = "default";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-name = "VSD_3V3";
- vin-supply = <&buck4>;
- gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
reg_usdhc3_vmmc: regulator-usdhc3 {
compatible = "regulator-fixed";
regulator-name = "VPCIe_3V3";
@@ -76,51 +19,6 @@ reg_usdhc3_vmmc: regulator-usdhc3 {
enable-active-high;
};
- reserved-memory {
- ranges;
- #address-cells = <2>;
- #size-cells = <2>;
-
- linux,cma {
- compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x30000000>;
- reusable;
- size = <0 0x10000000>;
- linux,cma-default;
- };
-
- rsc_table: rsc-table@2021e000 {
- reg = <0 0x2021e000 0 0x1000>;
- no-map;
- };
-
- vdev0vring0: vdev0vring0@a4000000 {
- reg = <0 0xa4000000 0 0x8000>;
- no-map;
- };
-
- vdev0vring1: vdev0vring1@a4008000 {
- reg = <0 0xa4008000 0 0x8000>;
- no-map;
- };
-
- vdev1vring0: vdev1vring0@a4010000 {
- reg = <0 0xa4010000 0 0x8000>;
- no-map;
- };
-
- vdev1vring1: vdev1vring1@a4018000 {
- reg = <0 0xa4018000 0 0x8000>;
- no-map;
- };
-
- vdevbuffer: vdevbuffer@a4020000 {
- compatible = "shared-dma-pool";
- reg = <0 0xa4020000 0 0x100000>;
- no-map;
- };
- };
-
sound-mqs {
compatible = "fsl,imx-audio-mqs";
model = "mqs-audio";
@@ -134,269 +32,6 @@ usdhc3_pwrseq: mmc-pwrseq {
};
};
-&adc1 {
- vref-supply = <&buck5>;
- status = "okay";
-};
-
-&mu1 {
- status = "okay";
-};
-
-&cm33 {
- mboxes = <&mu1 0 1>,
- <&mu1 1 1>,
- <&mu1 3 1>;
- mbox-names = "tx", "rx", "rxdb";
- memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
- <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
- status = "okay";
-};
-
-&eqos {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_eqos>;
- pinctrl-1 = <&pinctrl_eqos_sleep>;
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-id";
- status = "okay";
-
- mdio {
- compatible = "snps,dwmac-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy1: ethernet-phy@1 {
- reg = <1>;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
- realtek,clkout-disable;
- };
- };
-};
-
-&fec {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec>;
- pinctrl-1 = <&pinctrl_fec_sleep>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy2>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <5000000>;
-
- ethphy2: ethernet-phy@2 {
- reg = <2>;
- reset-assert-us = <10000>;
- reset-deassert-us = <80000>;
- reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
- realtek,clkout-disable;
- };
- };
-};
-
-&flexcan2 {
- phys = <&flexcan2_phy>;
- pinctrl-0 = <&pinctrl_flexcan2>;
- pinctrl-1 = <&pinctrl_flexcan2_sleep>;
- pinctrl-names = "default", "sleep";
- status = "okay";
-};
-
-&lpi2c1 {
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c1>;
- pinctrl-names = "default";
- status = "okay";
-
- pcal6408: gpio@20 {
- compatible = "nxp,pcal6408";
- reg = <0x20>;
- #gpio-cells = <2>;
- gpio-controller;
- reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
- };
-};
-
-&lpi2c2 {
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c2>;
- pinctrl-names = "default";
- status = "okay";
-
- pcal6524: gpio@22 {
- compatible = "nxp,pcal6524";
- reg = <0x22>;
- #interrupt-cells = <2>;
- interrupt-controller;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
- #gpio-cells = <2>;
- gpio-controller;
- pinctrl-0 = <&pinctrl_pcal6524>;
- pinctrl-names = "default";
- /* does not boot with supplier set, because it is the bucks interrupt parent */
- /* vcc-supply = <&buck4>; */
- };
-
- pmic@25 {
- compatible = "nxp,pca9451a";
- reg = <0x25>;
- interrupt-parent = <&pcal6524>;
- interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
-
- regulators {
-
- buck1: BUCK1 {
- regulator-name = "VDD_SOC_0V8";
- regulator-min-microvolt = <610000>;
- regulator-max-microvolt = <950000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck2: BUCK2 {
- regulator-name = "LPD4_x_VDDQ_0V6";
- regulator-min-microvolt = <600000>;
- regulator-max-microvolt = <670000>;
- regulator-always-on;
- regulator-boot-on;
- regulator-ramp-delay = <3125>;
- };
-
- buck4: BUCK4 {
- regulator-name = "VDD_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck5: BUCK5 {
- regulator-name = "VDD_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck6: BUCK6 {
- regulator-name = "LPD4_x_VDD2_1V1";
- regulator-min-microvolt = <1060000>;
- regulator-max-microvolt = <1140000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo1: LDO1 {
- regulator-name = "NVCC_BBSM_1V8";
- regulator-min-microvolt = <1620000>;
- regulator-max-microvolt = <1980000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo4: LDO4 {
- regulator-name = "VDD_ANA_0V8";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <840000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo5: LDO5 {
- regulator-name = "NVCC_SD";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-
- eeprom: eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- pagesize = <64>;
- vcc-supply = <&buck4>;
- };
-};
-
-&lpi2c3 {
- clock-frequency = <400000>;
- pinctrl-0 = <&pinctrl_lpi2c3>;
- pinctrl-names = "default";
- status = "okay";
-
- ptn5110: tcpc@50 {
- compatible = "nxp,ptn5110", "tcpci";
- reg = <0x50>;
- interrupt-parent = <&gpio3>;
- interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
- typec1_con: connector {
- compatible = "usb-c-connector";
- data-role = "dual";
- label = "USB-C";
- op-sink-microwatt = <15000000>;
- power-role = "dual";
- self-powered;
- sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
- PDO_VAR(5000, 20000, 3000)>;
- source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
- try-power-role = "sink";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- typec1_dr_sw: endpoint {
- remote-endpoint = <&usb1_drd_sw>;
- };
- };
- };
- };
- };
-
- pcf2131: rtc@53 {
- compatible = "nxp,pcf2131";
- reg = <0x53>;
- interrupt-parent = <&pcal6524>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- };
-};
-
-&lpuart1 { /* console */
- pinctrl-0 = <&pinctrl_uart1>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&lpuart5 {
- pinctrl-0 = <&pinctrl_uart5>;
- pinctrl-names = "default";
- status = "okay";
-
- uart-has-rtscts;
-
- bluetooth {
- compatible = "nxp,88w8987-bt";
- device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>;
- reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>;
- vcc-supply = <®_usdhc3_vmmc>;
- };
-};
-
&mqs1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mqs1>;
@@ -418,57 +53,6 @@ &sai1 {
status = "okay";
};
-&usbotg1 {
- adp-disable;
- disable-over-current;
- dr_mode = "otg";
- hnp-disable;
- srp-disable;
- usb-role-switch;
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-
- port {
- usb1_drd_sw: endpoint {
- remote-endpoint = <&typec1_dr_sw>;
- };
- };
-};
-
-&usbotg2 {
- disable-over-current;
- dr_mode = "host";
- samsung,picophy-dc-vol-level-adjust = <7>;
- samsung,picophy-pre-emp-curr-control = <3>;
- status = "okay";
-};
-
-&usdhc1 {
- bus-width = <8>;
- non-removable;
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- vmmc-supply = <&buck4>;
- status = "okay";
-};
-
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
- no-mmc;
- no-sdio;
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- vmmc-supply = <®_usdhc2_vmmc>;
- status = "okay";
-};
-
&usdhc3 {
bus-width = <4>;
keep-power-in-suspend;
@@ -483,126 +67,8 @@ &usdhc3 {
status = "okay";
};
-&wdog3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wdog>;
- fsl,ext-reset-output;
- status = "okay";
-};
&iomuxc {
-
- pinctrl_eqos: eqosgrp {
- fsl,pins = <
- MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
- MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
- MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
- MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
- MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
- MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
- MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
- MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
- MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
- MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
- MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
- MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
- MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_eqos_sleep: eqossleepgrp {
- fsl,pins = <
- MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
- MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
- MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
- MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
- MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
- MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
- MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
- MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
- MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
- MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
- MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
- MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
- MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
- MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
- MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
- MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
- MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
- MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
- MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
- MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
- MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
- MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
- MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
- MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
- MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
- MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
- MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
- >;
- };
-
- pinctrl_fec_sleep: fecsleepgrp {
- fsl,pins = <
- MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
- MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
- MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
- MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
- MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
- MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
- MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
- MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
- MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
- MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
- MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
- MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
- MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
- MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
- MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
- >;
- };
-
- pinctrl_flexcan2_sleep: flexcan2sleepgrp {
- fsl,pins = <
- MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e
- MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e
- >;
- };
-
- pinctrl_lpi2c1: lpi2c1grp {
- fsl,pins = <
- MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
- MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c2: lpi2c2grp {
- fsl,pins = <
- MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
- MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
- >;
- };
-
- pinctrl_lpi2c3: lpi2c3grp {
- fsl,pins = <
- MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
- MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
- >;
- };
-
pinctrl_mqs1: mqs1grp {
fsl,pins = <
MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e
@@ -610,149 +76,7 @@ MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e
>;
};
- pinctrl_pcal6524: pcal6524grp {
- fsl,pins = <
- MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
- >;
- };
-
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
- fsl,pins = <
- MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
- MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
- >;
- };
-
- pinctrl_uart5: uart5grp {
- fsl,pins = <
- MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
- MX93_PAD_DAP_TDI__LPUART5_RX 0x31e
- MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
- MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
- MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
- MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
- MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
- MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
- MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
- MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
- MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
- MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
- MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
- >;
- };
-
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
- >;
- };
-
- pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
- fsl,pins = <
- MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
/* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
- MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
- MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
- MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
- MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
- MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
- >;
- };
-
- pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
- fsl,pins = <
- MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
- MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
- MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
- MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
- MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
- MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
- MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
- >;
- };
-
- /* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
@@ -798,10 +122,4 @@ MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
-
- pinctrl_wdog: wdoggrp {
- fsl,pins = <
- MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
- >;
- };
};
--
2.34.1
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