[PATCH 0/6] Documentation/gpu/amdgpu: Add documentation about Pipes, Queues, MES, and others

[PATCH 0/6] Documentation/gpu/amdgpu: Add documentation about Pipes, Queues, MES, and others

[Rodrigo Siqueira]

Hi,

This patchset came from my endeavor to understand better how some of the
amdgpu components operate; in particular, I was focused on the ideas
behind Pipes, Hardware Queues, MES, and Ring Buffers. In some way, this
series is an attempt to put multiple pieces of information spread around
many different places in an organized way in the amdgpu kernel-doc. In
particular, the following links were crucial to create this series:

* https://lore.kernel.org/amd-gfx/CADnq5_Pcz2x4aJzKbVrN3jsZhD6sTydtDw=6PaN4O3m4t+Grtg@mail.gmail.com/T/#m9a670b55ab20e0f7c46c80f802a0a4be255a719d
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/11759
* https://www.x.org/docs/AMD/old/R5xx_Acceleration_v1.5.pdf
* https://gpuopen.com/videos/graphics-pipeline/

The first part of this series just updates the amdgpu-glossary with some
new acronyms (some of them useful for other patches). The next two
patches are just some basic organization to improve the documentation
flow. The last part describes pipes, hardware queues, ring buffers, and
MES.

Thanks
Siqueira

Rodrigo Siqueira (6):
  Documentation/gpu: Add new acronyms
  Documentation/gpu: Change index order to show driver core first
  Documentation/gpu: Create a documentation entry just for hardware info
  Documentation/gpu: Add explanation about AMD Pipes and Queues
  Documentation/gpu: Create a GC entry in the amdgpu documentation
  Documentation/gpu: Add an intro about MES

 .../gpu/amdgpu/amd-hardware-list-info.rst     |   23 +
 Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   36 +
 Documentation/gpu/amdgpu/driver-core.rst      |   77 +-
 Documentation/gpu/amdgpu/driver-misc.rst      |   17 -
 Documentation/gpu/amdgpu/gc/index.rst         |   53 +
 Documentation/gpu/amdgpu/gc/mes.rst           |   38 +
 Documentation/gpu/amdgpu/index.rst            |    4 +-
 .../gpu/amdgpu/pipe_and_queue_abstraction.svg | 1279 +++++++++++++++++
 8 files changed, 1485 insertions(+), 42 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/amd-hardware-list-info.rst
 create mode 100644 Documentation/gpu/amdgpu/gc/index.rst
 create mode 100644 Documentation/gpu/amdgpu/gc/mes.rst
 create mode 100644 Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg

-- 
2.49.0

[PATCH 1/6] Documentation/gpu: Add new acronyms

[Rodrigo Siqueira]

This commit introduces some new acronyms extracted from the source code
and found on some web pages around the internet (most of them came from
ArchLinux, Gentoo, and Wikipedia links).

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/amdgpu-glossary.rst | 36 ++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 1e9283e076ba..080c3f2250d1 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -12,15 +12,27 @@ we have a dedicated glossary for Display Core at
       The number of CUs that are active on the system.  The number of active
       CUs may be less than SE * SH * CU depending on the board configuration.
 
+    BACO
+      Bus Alive, Chip Off
+
+    BOCO
+      Bus Off, Chip Off
+
     CE
       Constant Engine
 
+    CIK
+      Sea Islands
+
     CP
       Command Processor
 
     CPLIB
       Content Protection Library
 
+    CS
+      Command Submission
+
     CU
       Compute Unit
 
@@ -33,6 +45,9 @@ we have a dedicated glossary for Display Core at
     EOP
       End Of Pipe/Pipeline
 
+    FLR
+      Function Level Reset
+
     GART
       Graphics Address Remapping Table.  This is the name we use for the GPUVM
       page table used by the GPU kernel driver.  It remaps system resources
@@ -80,6 +95,9 @@ we have a dedicated glossary for Display Core at
     KCQ
       Kernel Compute Queue
 
+    KFD
+      Kernel Fusion Driver
+
     KGQ
       Kernel Graphics Queue
 
@@ -89,6 +107,9 @@ we have a dedicated glossary for Display Core at
     MC
       Memory Controller
 
+    MCBP
+      Mid Command Buffer Preemption
+
     ME
       MicroEngine (Graphics)
 
@@ -125,9 +146,15 @@ we have a dedicated glossary for Display Core at
     SE
       Shader Engine
 
+    SGPR
+      Scalar General-Purpose Registers
+
     SH
       SHader array
 
+    SI
+      Southern Islands
+
     SMU/SMC
       System Management Unit / System Management Controller
 
@@ -146,6 +173,9 @@ we have a dedicated glossary for Display Core at
     TA
       Trusted Application
 
+    TC
+      Texture Cache
+
     TOC
       Table of Contents
 
@@ -158,5 +188,11 @@ we have a dedicated glossary for Display Core at
     VCN
       Video Codec Next
 
+    VGPR
+      Vector General-Purpose Registers
+
+    VMID
+      Virtual Memory ID
+
     VPE
       Video Processing Engine
-- 
2.49.0

Re: [PATCH 1/6] Documentation/gpu: Add new acronyms

[Christian König]

Am 25.03.25 um 18:18 schrieb Rodrigo Siqueira:
> This commit introduces some new acronyms extracted from the source code
> and found on some web pages around the internet (most of them came from
> ArchLinux, Gentoo, and Wikipedia links).
>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 36 ++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 1e9283e076ba..080c3f2250d1 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -12,15 +12,27 @@ we have a dedicated glossary for Display Core at
>        The number of CUs that are active on the system.  The number of active
>        CUs may be less than SE * SH * CU depending on the board configuration.
>  
> +    BACO
> +      Bus Alive, Chip Off
> +
> +    BOCO
> +      Bus Off, Chip Off
> +
>      CE
>        Constant Engine
>  
> +    CIK
> +      Sea Islands
> +
>      CP
>        Command Processor
>  
>      CPLIB
>        Content Protection Library
>  
> +    CS
> +      Command Submission
> +
>      CU
>        Compute Unit
>  
> @@ -33,6 +45,9 @@ we have a dedicated glossary for Display Core at
>      EOP
>        End Of Pipe/Pipeline
>  
> +    FLR
> +      Function Level Reset
> +
>      GART
>        Graphics Address Remapping Table.  This is the name we use for the GPUVM
>        page table used by the GPU kernel driver.  It remaps system resources
> @@ -80,6 +95,9 @@ we have a dedicated glossary for Display Core at
>      KCQ
>        Kernel Compute Queue
>  
> +    KFD
> +      Kernel Fusion Driver
> +
>      KGQ
>        Kernel Graphics Queue
>  
> @@ -89,6 +107,9 @@ we have a dedicated glossary for Display Core at
>      MC
>        Memory Controller
>  
> +    MCBP
> +      Mid Command Buffer Preemption
> +
>      ME
>        MicroEngine (Graphics)
>  
> @@ -125,9 +146,15 @@ we have a dedicated glossary for Display Core at
>      SE
>        Shader Engine
>  
> +    SGPR
> +      Scalar General-Purpose Registers
> +
>      SH
>        SHader array
>  
> +    SI
> +      Southern Islands
> +
>      SMU/SMC
>        System Management Unit / System Management Controller
>  
> @@ -146,6 +173,9 @@ we have a dedicated glossary for Display Core at
>      TA
>        Trusted Application
>  
> +    TC
> +      Texture Cache
> +
>      TOC
>        Table of Contents
>  
> @@ -158,5 +188,11 @@ we have a dedicated glossary for Display Core at
>      VCN
>        Video Codec Next
>  
> +    VGPR
> +      Vector General-Purpose Registers
> +
> +    VMID
> +      Virtual Memory ID
> +
>      VPE
>        Video Processing Engine

[PATCH 2/6] Documentation/gpu: Change index order to show driver core first

[Rodrigo Siqueira]

Since driver-core has an overview of the AMD GPU hardware structure, it
makes more sense to keep it first. This commit move driver-core up in
the index list.

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/index.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 302d039928ee..3832aa764c72 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -7,8 +7,8 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
 
 .. toctree::
 
-   module-parameters
    driver-core
+   module-parameters
    display/index
    flashing
    xgmi
-- 
2.49.0

[PATCH 3/6] Documentation/gpu: Create a documentation entry just for hardware info

[Rodrigo Siqueira]

The APU and dGPU tables are hidden in the driver misc info, which makes
it hard to find specific hardware info when users need it. This commit
creates a single page for this information and adds it to the top of the
amdgpu list to improve searchability.

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 .../gpu/amdgpu/amd-hardware-list-info.rst     | 23 +++++++++++++++++++
 Documentation/gpu/amdgpu/driver-misc.rst      | 17 --------------
 Documentation/gpu/amdgpu/index.rst            |  1 +
 3 files changed, 24 insertions(+), 17 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/amd-hardware-list-info.rst

diff --git a/Documentation/gpu/amdgpu/amd-hardware-list-info.rst b/Documentation/gpu/amdgpu/amd-hardware-list-info.rst
new file mode 100644
index 000000000000..1786544fe7c1
--- /dev/null
+++ b/Documentation/gpu/amdgpu/amd-hardware-list-info.rst
@@ -0,0 +1,23 @@
+=================================================
+ AMD Hardware Components Information per Product
+=================================================
+
+On this page, you can find the AMD product name and which component version is
+part of it.
+
+Accelerated Processing Units (APU) Info
+---------------------------------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1, 1
+   :file: ./apu-asic-info-table.csv
+
+Discrete GPU Info
+-----------------
+
+.. csv-table::
+   :header-rows: 1
+   :widths: 3, 2, 2, 1, 1, 1
+   :file: ./dgpu-asic-info-table.csv
+
diff --git a/Documentation/gpu/amdgpu/driver-misc.rst b/Documentation/gpu/amdgpu/driver-misc.rst
index e40e15f89fd3..25b0c857816e 100644
--- a/Documentation/gpu/amdgpu/driver-misc.rst
+++ b/Documentation/gpu/amdgpu/driver-misc.rst
@@ -50,23 +50,6 @@ board_info
 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
    :doc: board_info
 
-Accelerated Processing Units (APU) Info
----------------------------------------
-
-.. csv-table::
-   :header-rows: 1
-   :widths: 3, 2, 2, 1, 1, 1, 1
-   :file: ./apu-asic-info-table.csv
-
-Discrete GPU Info
------------------
-
-.. csv-table::
-   :header-rows: 1
-   :widths: 3, 2, 2, 1, 1, 1
-   :file: ./dgpu-asic-info-table.csv
-
-
 GPU Memory Usage Information
 ============================
 
diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 3832aa764c72..7e9d60754287 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
 .. toctree::
 
    driver-core
+   amd-hardware-list-info
    module-parameters
    display/index
    flashing
-- 
2.49.0

[PATCH 4/6] Documentation/gpu: Add explanation about AMD Pipes and Queues

[Rodrigo Siqueira]

Pipes and Queues are two common vocabulary that pervades discussions
around amdgpu core features. The definition and explanation of those
components are spread around multiple places in the code, mailing list,
and Gitlab, which sometimes leads to the wrong interpretation of these
concepts. This commit attempts to centralize the definition and
explanation of Pipe and Queue from amdgpu perspective in a kernel doc.
Most of the information in this doc was derived from:

- https://lore.kernel.org/amd-gfx/CADnq5_Pcz2x4aJzKbVrN3jsZhD6sTydtDw=6PaN4O3m4t+Grtg@mail.gmail.com/T/#m9a670b55ab20e0f7c46c80f802a0a4be255a719d
- https://gitlab.freedesktop.org/mesa/mesa/-/issues/11759

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/driver-core.rst      |   49 +
 .../gpu/amdgpu/pipe_and_queue_abstraction.svg | 1279 +++++++++++++++++
 2 files changed, 1328 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg

diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 32723a925377..746fd081876f 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -98,6 +98,55 @@ RLC (RunList Controller)
     The name is a vestige of old hardware where it was originally added
     and doesn't really have much relation to what the engine does now.
 
+
+GFX, Compute, and SDMA Overall Behavior
+=======================================
+
+.. note:: For simplicity, whenever the term block is used in this section, it
+   means GFX, Compute, and SDMA.
+
+GFX, Compute and SDMA share a similar form of operation that can be abstracted
+to facilitate understanding of the behavior of these blocks. See the figure
+below illustrating the common components of these blocks:
+
+.. kernel-figure:: pipe_and_queue_abstraction.svg
+
+In the central part of this figure, you can see two elements, one called
+**Pipe** and another named **Queues**; it is important to highlight that Queues
+must be associated with a Pipe and vice-versa. Every specific hardware may have
+a different number of Pipes and, in turn, a different number of Queues; for
+example, GFX 11 has two Pipes and two Queues per Pipe.
+
+Pipe is the hardware that processes the instructions available in the Queues;
+in other words, it is a thread executing the operations inserted in the Queue.
+One crucial characteristic of Pipes is that they can only execute one Queue at
+a time; no matter if the hardware has multiple Queues in the Pipe, it only runs
+one Queue per Pipe. When a queue is running in the Pipe, it is said that the
+Queue is **Active**.
+
+Pipes have the mechanics of swapping between queues at the hardware level.
+Nonetheless, they only make use of Queues that are considered mapped. Pipes can
+switch between queues based on any of the following inputs:
+
+1. Command Stream;
+2. Packet by Packet;
+3. Other hardware requests the change (e.g., MES).
+
+Queues within Pipes are defined by the Hardware Queue Descriptors (HQD).
+Associated with the HQD concept, we have the Memory Queue Descriptor (MQD),
+which is responsible for storing information about the state of each of the
+available Queues in the memory. The state of a Queue contains information such
+as the GPU virtual address of the queue itself, save areas, doorbell, etc. The
+MQD also stores the HQD registers, which are vital for activating or
+deactivating a given Queue.
+
+The Queue-switching process can also happen with the firmware requesting the
+preemption or unmapping of a Queue. The firmware waits for the HQD_ACTIVE bit
+to change to low before saving the state into the MQD. To make a different
+Queue become active, the firmware copies the MQD state into the HQD registers
+and loads any additional state. Finally, it sets the HQD_ACTIVE bit to high to
+indicate that the queue is active.
+
 Driver Structure
 ================
 
diff --git a/Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg b/Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg
new file mode 100644
index 000000000000..0df3c6b3000b
--- /dev/null
+++ b/Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg
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-- 
2.49.0

Re: [PATCH 4/6] Documentation/gpu: Add explanation about AMD Pipes and Queues

[Bagas Sanjaya]

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On Tue, Mar 25, 2025 at 11:18:45AM -0600, Rodrigo Siqueira wrote:
> +.. kernel-figure:: pipe_and_queue_abstraction.svg
> +
> +In the central part of this figure, you can see two elements, one called
Did you mean hardware block?
> +**Pipe** and another named **Queues**; it is important to highlight that Queues
> +must be associated with a Pipe and vice-versa. Every specific hardware may have
> +a different number of Pipes and, in turn, a different number of Queues; for
> +example, GFX 11 has two Pipes and two Queues per Pipe.
> +
> +Pipe is the hardware that processes the instructions available in the Queues;
> +in other words, it is a thread executing the operations inserted in the Queue.
> +One crucial characteristic of Pipes is that they can only execute one Queue at
> +a time; no matter if the hardware has multiple Queues in the Pipe, it only runs
> +one Queue per Pipe. When a queue is running in the Pipe, it is said that the
> +Queue is **Active**.
> +
> +Pipes have the mechanics of swapping between queues at the hardware level.
> +Nonetheless, they only make use of Queues that are considered mapped. Pipes can
> +switch between queues based on any of the following inputs:
> +
> +1. Command Stream;
> +2. Packet by Packet;
> +3. Other hardware requests the change (e.g., MES).
> +
> +Queues within Pipes are defined by the Hardware Queue Descriptors (HQD).
> +Associated with the HQD concept, we have the Memory Queue Descriptor (MQD),
Related to HQD, we have MQD?
> +which is responsible for storing information about the state of each of the
> +available Queues in the memory. The state of a Queue contains information such
> +as the GPU virtual address of the queue itself, save areas, doorbell, etc. The
> +MQD also stores the HQD registers, which are vital for activating or
> +deactivating a given Queue.
> +

Thanks.

-- 
An old man doll... just what I always wanted! - Clara

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Re: [PATCH 4/6] Documentation/gpu: Add explanation about AMD Pipes and Queues

[Christian König]

Am 25.03.25 um 18:18 schrieb Rodrigo Siqueira:
> Pipes and Queues are two common vocabulary that pervades discussions
> around amdgpu core features. The definition and explanation of those
> components are spread around multiple places in the code, mailing list,
> and Gitlab, which sometimes leads to the wrong interpretation of these
> concepts. This commit attempts to centralize the definition and
> explanation of Pipe and Queue from amdgpu perspective in a kernel doc.
> Most of the information in this doc was derived from:
>
> - https://lore.kernel.org/amd-gfx/CADnq5_Pcz2x4aJzKbVrN3jsZhD6sTydtDw=6PaN4O3m4t+Grtg@mail.gmail.com/T/#m9a670b55ab20e0f7c46c80f802a0a4be255a719d
> - https://gitlab.freedesktop.org/mesa/mesa/-/issues/11759
>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>

Oh that's really nice to have, especially since I'm constantly mixing up the terms queue and pipe as well :)

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>  Documentation/gpu/amdgpu/driver-core.rst      |   49 +
>  .../gpu/amdgpu/pipe_and_queue_abstraction.svg | 1279 +++++++++++++++++
>  2 files changed, 1328 insertions(+)
>  create mode 100644 Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg
>
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 32723a925377..746fd081876f 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -98,6 +98,55 @@ RLC (RunList Controller)
>      The name is a vestige of old hardware where it was originally added
>      and doesn't really have much relation to what the engine does now.
>  
> +
> +GFX, Compute, and SDMA Overall Behavior
> +=======================================
> +
> +.. note:: For simplicity, whenever the term block is used in this section, it
> +   means GFX, Compute, and SDMA.
> +
> +GFX, Compute and SDMA share a similar form of operation that can be abstracted
> +to facilitate understanding of the behavior of these blocks. See the figure
> +below illustrating the common components of these blocks:
> +
> +.. kernel-figure:: pipe_and_queue_abstraction.svg
> +
> +In the central part of this figure, you can see two elements, one called
> +**Pipe** and another named **Queues**; it is important to highlight that Queues
> +must be associated with a Pipe and vice-versa. Every specific hardware may have
> +a different number of Pipes and, in turn, a different number of Queues; for
> +example, GFX 11 has two Pipes and two Queues per Pipe.
> +
> +Pipe is the hardware that processes the instructions available in the Queues;
> +in other words, it is a thread executing the operations inserted in the Queue.
> +One crucial characteristic of Pipes is that they can only execute one Queue at
> +a time; no matter if the hardware has multiple Queues in the Pipe, it only runs
> +one Queue per Pipe. When a queue is running in the Pipe, it is said that the
> +Queue is **Active**.
> +
> +Pipes have the mechanics of swapping between queues at the hardware level.
> +Nonetheless, they only make use of Queues that are considered mapped. Pipes can
> +switch between queues based on any of the following inputs:
> +
> +1. Command Stream;
> +2. Packet by Packet;
> +3. Other hardware requests the change (e.g., MES).
> +
> +Queues within Pipes are defined by the Hardware Queue Descriptors (HQD).
> +Associated with the HQD concept, we have the Memory Queue Descriptor (MQD),
> +which is responsible for storing information about the state of each of the
> +available Queues in the memory. The state of a Queue contains information such
> +as the GPU virtual address of the queue itself, save areas, doorbell, etc. The
> +MQD also stores the HQD registers, which are vital for activating or
> +deactivating a given Queue.
> +
> +The Queue-switching process can also happen with the firmware requesting the
> +preemption or unmapping of a Queue. The firmware waits for the HQD_ACTIVE bit
> +to change to low before saving the state into the MQD. To make a different
> +Queue become active, the firmware copies the MQD state into the HQD registers
> +and loads any additional state. Finally, it sets the HQD_ACTIVE bit to high to
> +indicate that the queue is active.
> +
>  Driver Structure
>  ================
>  
> diff --git a/Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg b/Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg
> new file mode 100644
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> +    <path
> +       style="fill:#800000;fill-opacity:0;stroke:#1a1a1a;stroke-width:1;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#ArrowWide)"
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> +         id="tspan87">MQD</tspan></text>
> +    <text
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> +       style="font-style:normal;font-weight:normal;font-size:7.05556px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
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> +         id="tspan89">MQD</tspan></text>
> +    <text
> +       xml:space="preserve"
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> +         id="tspan90">MQD</tspan></text>
> +    <text
> +       xml:space="preserve"
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> +         id="tspan91">MQD</tspan></text>
> +    <text
> +       xml:space="preserve"
> +       style="font-style:normal;font-weight:normal;font-size:10.5833px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="-74.441521"
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> +       id="text92"><tspan
> +         sodipodi:role="line"
> +         x="-74.441521"
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> +         id="tspan92">...</tspan></text>
> +    <g
> +       id="g97"
> +       transform="translate(-5.8208336)">
> +      <rect
> +         style="fill:#aaffcc;fill-opacity:1;stroke:#1a1a1a;stroke-width:0.5;stroke-dasharray:none;stroke-dashoffset:0"
> +         id="rect96"
> +         width="58.726093"
> +         height="27.598055"
> +         x="-142.96434"
> +         y="46.852512" />
> +      <text
> +         xml:space="preserve"
> +         style="font-style:normal;font-weight:normal;font-size:4.23333px;line-height:1.25;font-family:sans-serif;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +         x="-139.74622"
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> +           sodipodi:role="line"
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> +           id="tspan93">HQD Registers</tspan><tspan
> +           sodipodi:role="line"
> +           x="-139.74622"
> +           y="57.91922"
> +           style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +           id="tspan95">Queue Address in the GPU</tspan><tspan
> +           sodipodi:role="line"
> +           x="-139.74622"
> +           y="63.210884"
> +           style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +           id="tspan96">Doorbell</tspan><tspan
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> +           x="-139.74622"
> +           y="68.502548"
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> +           id="tspan97">...</tspan><tspan
> +           sodipodi:role="line"
> +           x="-139.74622"
> +           y="73.794212"
> +           style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +           id="tspan94" /></text>
> +    </g>
> +    <text
> +       xml:space="preserve"
> +       style="font-style:normal;font-weight:normal;font-size:4.23333px;line-height:1.25;font-family:sans-serif;text-align:start;letter-spacing:0px;word-spacing:0px;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="-61.293022"
> +       y="-19.380915"
> +       id="text93-1"><tspan
> +         sodipodi:role="line"
> +         x="-61.293022"
> +         y="-19.380915"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;stroke-width:0.0690111"
> +         id="tspan104">SWITCH QUEUE:</tspan><tspan
> +         sodipodi:role="line"
> +         x="-61.293022"
> +         y="-14.089252"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +         id="tspan101">WAIT FOR HQD_ACTIVE = 0</tspan><tspan
> +         sodipodi:role="line"
> +         x="-61.293022"
> +         y="-8.7975903"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +         id="tspan105">SAVE QUEUE STATE TO THE MQD</tspan><tspan
> +         sodipodi:role="line"
> +         x="-61.293022"
> +         y="-3.505928"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +         id="tspan102">COPY NEW MQD STATE</tspan><tspan
> +         sodipodi:role="line"
> +         x="-61.293022"
> +         y="1.7857342"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:4.23333px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:start;text-anchor:start;stroke-width:0.0690111"
> +         id="tspan103">SET HQD_ACTIVE = 1</tspan></text>
> +    <circle
> +       style="fill:#ffeeaa;fill-opacity:1;stroke:#1a1a1a;stroke-width:1.88976;stroke-dasharray:none;stroke-dashoffset:0"
> +       id="path97"
> +       cx="0"
> +       cy="0"
> +       r="0"
> +       transform="matrix(0.26458333,0,0,0.26458333,-149.03517,37.347779)" />
> +    <text
> +       xml:space="preserve"
> +       style="font-style:normal;font-weight:normal;font-size:5.64444px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
> +       x="-36.659206"
> +       y="-44.828983"
> +       id="text106"><tspan
> +         sodipodi:role="line"
> +         x="-36.659206"
> +         y="-44.828983"
> +         style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:5.64444px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;stroke-width:0.0690111"
> +         id="tspan106">Firmware</tspan></text>
> +    <path
> +       style="fill:none;fill-opacity:1;stroke:#1a1a1a;stroke-width:1;stroke-dasharray:none;stroke-dashoffset:0;marker-start:url(#marker109);marker-end:url(#ArrowTriangleStylized)"
> +       d="M -84.242601,-9.1838245 H -98.041629 V 33.17598"
> +       id="path106" />
> +    <path
> +       style="fill:none;fill-opacity:1;stroke:#1a1a1a;stroke-width:1;stroke-dasharray:none;stroke-dashoffset:0;marker-end:url(#Dot)"
> +       d="M 9.9745536,-9.3442784 H 29.549918 V 37.170287"
> +       id="path107"
> +       sodipodi:nodetypes="ccc" />
> +  </g>
> +</svg>

[PATCH 5/6] Documentation/gpu: Create a GC entry in the amdgpu documentation

[Rodrigo Siqueira]

GC is a large block that plays a vital role for amdgpu; for this reason,
this commit creates one specific page for GC and adds extra information
about the CP component.

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/driver-core.rst | 30 ++-------------
 Documentation/gpu/amdgpu/gc/index.rst    | 48 ++++++++++++++++++++++++
 Documentation/gpu/amdgpu/index.rst       |  1 +
 3 files changed, 53 insertions(+), 26 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/gc/index.rst

diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 746fd081876f..2af1e919d76a 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -67,38 +67,16 @@ GC (Graphics and Compute)
     This is the graphics and compute engine, i.e., the block that
     encompasses the 3D pipeline and and shader blocks.  This is by far the
     largest block on the GPU.  The 3D pipeline has tons of sub-blocks.  In
-    addition to that, it also contains the CP microcontrollers (ME, PFP,
-    CE, MEC) and the RLC microcontroller.  It's exposed to userspace for
-    user mode drivers (OpenGL, Vulkan, OpenCL, etc.)
+    addition to that, it also contains the CP microcontrollers (ME, PFP, CE,
+    MEC) and the RLC microcontroller.  It's exposed to userspace for user mode
+    drivers (OpenGL, Vulkan, OpenCL, etc.). More details in :ref:`Graphics (GFX)
+    and Compute <amdgpu-gc>`.
 
 VCN (Video Core Next)
     This is the multi-media engine.  It handles video and image encode and
     decode.  It's exposed to userspace for user mode drivers (VA-API,
     OpenMAX, etc.)
 
-Graphics and Compute Microcontrollers
--------------------------------------
-
-CP (Command Processor)
-    The name for the hardware block that encompasses the front end of the
-    GFX/Compute pipeline.  Consists mainly of a bunch of microcontrollers
-    (PFP, ME, CE, MEC).  The firmware that runs on these microcontrollers
-    provides the driver interface to interact with the GFX/Compute engine.
-
-    MEC (MicroEngine Compute)
-        This is the microcontroller that controls the compute queues on the
-        GFX/compute engine.
-
-    MES (MicroEngine Scheduler)
-        This is a new engine for managing queues.  This is currently unused.
-
-RLC (RunList Controller)
-    This is another microcontroller in the GFX/Compute engine.  It handles
-    power management related functionality within the GFX/Compute engine.
-    The name is a vestige of old hardware where it was originally added
-    and doesn't really have much relation to what the engine does now.
-
-
 GFX, Compute, and SDMA Overall Behavior
 =======================================
 
diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
new file mode 100644
index 000000000000..f8128cca7028
--- /dev/null
+++ b/Documentation/gpu/amdgpu/gc/index.rst
@@ -0,0 +1,48 @@
+.. _amdgpu-gc:
+
+========================================
+ drm/amdgpu - Graphics and Compute (GC)
+========================================
+
+The relationship between the CPU and GPU can be described as the
+producer-consumer problem, where the CPU fills out a buffer with operations
+(producer) to be executed by the GPU (consumer). The requested operations in
+the buffer are called Command Packets, which can be summarized as a compressed
+way of transmitting command information to the graphics controller.
+
+The component that acts as the front end between the CPU and the GPU is called
+the Command Processor (CP). This component is responsible for providing greater
+flexibility to the GC since CP makes it possible to program various aspects of
+the GPU pipeline. CP also coordinates the communication between the CPU and GPU
+via a mechanism named **Ring Buffers**, where the CPU appends information to
+the buffer while the GPU removes operations. It is relevant to highlight that a
+CPU can add a pointer to the Ring Buffer that points to another region of
+memory outside the Ring Buffer, and CP can handle it; this mechanism is called
+**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
+according to the parser result, the CP writes the request for operations in the
+correct block.
+
+Graphics (GFX) and Compute Microcontrollers
+-------------------------------------------
+
+GC is a large block, and as a result, it has multiple firmware associated with
+it. Some of them are:
+
+CP (Command Processor)
+    The name for the hardware block that encompasses the front end of the
+    GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
+    (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
+    provides the driver interface to interact with the GFX/Compute engine.
+
+    MEC (MicroEngine Compute)
+        This is the microcontroller that controls the compute queues on the
+        GFX/compute engine.
+
+    MES (MicroEngine Scheduler)
+        This is the engine for managing queues.
+
+RLC (RunList Controller)
+    This is another microcontroller in the GFX/Compute engine. It handles
+    power management related functionality within the GFX/Compute engine.
+    The name is a vestige of old hardware where it was originally added
+    and doesn't really have much relation to what the engine does now.
diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index 7e9d60754287..1624f4b588c5 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -10,6 +10,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
    driver-core
    amd-hardware-list-info
    module-parameters
+   gc/index
    display/index
    flashing
    xgmi
-- 
2.49.0

Re: [PATCH 5/6] Documentation/gpu: Create a GC entry in the amdgpu documentation

[Bagas Sanjaya]

[-- Attachment #1: Type: text/plain, Size: 1025 bytes --]

On Tue, Mar 25, 2025 at 11:18:46AM -0600, Rodrigo Siqueira wrote:
> +The component that acts as the front end between the CPU and the GPU is called
> +the Command Processor (CP). This component is responsible for providing greater
> +flexibility to the GC since CP makes it possible to program various aspects of
> +the GPU pipeline. CP also coordinates the communication between the CPU and GPU
> +via a mechanism named **Ring Buffers**, where the CPU appends information to
> +the buffer while the GPU removes operations. It is relevant to highlight that a
> +CPU can add a pointer to the Ring Buffer that points to another region of
> +memory outside the Ring Buffer, and CP can handle it; this mechanism is called
> +**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
> +according to the parser result, the CP writes the request for operations in the
"depending on the parser result, ..."
> +correct block.

Thanks.

-- 
An old man doll... just what I always wanted! - Clara

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 5/6] Documentation/gpu: Create a GC entry in the amdgpu documentation

[Christian König]

Am 25.03.25 um 18:18 schrieb Rodrigo Siqueira:
> GC is a large block that plays a vital role for amdgpu; for this reason,
> this commit creates one specific page for GC and adds extra information
> about the CP component.
>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>

Acked-by: <christian.koenig@amd.com>

> ---
>  Documentation/gpu/amdgpu/driver-core.rst | 30 ++-------------
>  Documentation/gpu/amdgpu/gc/index.rst    | 48 ++++++++++++++++++++++++
>  Documentation/gpu/amdgpu/index.rst       |  1 +
>  3 files changed, 53 insertions(+), 26 deletions(-)
>  create mode 100644 Documentation/gpu/amdgpu/gc/index.rst
>
> diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
> index 746fd081876f..2af1e919d76a 100644
> --- a/Documentation/gpu/amdgpu/driver-core.rst
> +++ b/Documentation/gpu/amdgpu/driver-core.rst
> @@ -67,38 +67,16 @@ GC (Graphics and Compute)
>      This is the graphics and compute engine, i.e., the block that
>      encompasses the 3D pipeline and and shader blocks.  This is by far the
>      largest block on the GPU.  The 3D pipeline has tons of sub-blocks.  In
> -    addition to that, it also contains the CP microcontrollers (ME, PFP,
> -    CE, MEC) and the RLC microcontroller.  It's exposed to userspace for
> -    user mode drivers (OpenGL, Vulkan, OpenCL, etc.)
> +    addition to that, it also contains the CP microcontrollers (ME, PFP, CE,
> +    MEC) and the RLC microcontroller.  It's exposed to userspace for user mode
> +    drivers (OpenGL, Vulkan, OpenCL, etc.). More details in :ref:`Graphics (GFX)
> +    and Compute <amdgpu-gc>`.
>  
>  VCN (Video Core Next)
>      This is the multi-media engine.  It handles video and image encode and
>      decode.  It's exposed to userspace for user mode drivers (VA-API,
>      OpenMAX, etc.)
>  
> -Graphics and Compute Microcontrollers
> --------------------------------------
> -
> -CP (Command Processor)
> -    The name for the hardware block that encompasses the front end of the
> -    GFX/Compute pipeline.  Consists mainly of a bunch of microcontrollers
> -    (PFP, ME, CE, MEC).  The firmware that runs on these microcontrollers
> -    provides the driver interface to interact with the GFX/Compute engine.
> -
> -    MEC (MicroEngine Compute)
> -        This is the microcontroller that controls the compute queues on the
> -        GFX/compute engine.
> -
> -    MES (MicroEngine Scheduler)
> -        This is a new engine for managing queues.  This is currently unused.
> -
> -RLC (RunList Controller)
> -    This is another microcontroller in the GFX/Compute engine.  It handles
> -    power management related functionality within the GFX/Compute engine.
> -    The name is a vestige of old hardware where it was originally added
> -    and doesn't really have much relation to what the engine does now.
> -
> -
>  GFX, Compute, and SDMA Overall Behavior
>  =======================================
>  
> diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
> new file mode 100644
> index 000000000000..f8128cca7028
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/gc/index.rst
> @@ -0,0 +1,48 @@
> +.. _amdgpu-gc:
> +
> +========================================
> + drm/amdgpu - Graphics and Compute (GC)
> +========================================
> +
> +The relationship between the CPU and GPU can be described as the
> +producer-consumer problem, where the CPU fills out a buffer with operations
> +(producer) to be executed by the GPU (consumer). The requested operations in
> +the buffer are called Command Packets, which can be summarized as a compressed
> +way of transmitting command information to the graphics controller.
> +
> +The component that acts as the front end between the CPU and the GPU is called
> +the Command Processor (CP). This component is responsible for providing greater
> +flexibility to the GC since CP makes it possible to program various aspects of
> +the GPU pipeline. CP also coordinates the communication between the CPU and GPU
> +via a mechanism named **Ring Buffers**, where the CPU appends information to
> +the buffer while the GPU removes operations. It is relevant to highlight that a
> +CPU can add a pointer to the Ring Buffer that points to another region of
> +memory outside the Ring Buffer, and CP can handle it; this mechanism is called
> +**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
> +according to the parser result, the CP writes the request for operations in the
> +correct block.
> +
> +Graphics (GFX) and Compute Microcontrollers
> +-------------------------------------------
> +
> +GC is a large block, and as a result, it has multiple firmware associated with
> +it. Some of them are:
> +
> +CP (Command Processor)
> +    The name for the hardware block that encompasses the front end of the
> +    GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers
> +    (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers
> +    provides the driver interface to interact with the GFX/Compute engine.
> +
> +    MEC (MicroEngine Compute)
> +        This is the microcontroller that controls the compute queues on the
> +        GFX/compute engine.
> +
> +    MES (MicroEngine Scheduler)
> +        This is the engine for managing queues.
> +
> +RLC (RunList Controller)
> +    This is another microcontroller in the GFX/Compute engine. It handles
> +    power management related functionality within the GFX/Compute engine.
> +    The name is a vestige of old hardware where it was originally added
> +    and doesn't really have much relation to what the engine does now.
> diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> index 7e9d60754287..1624f4b588c5 100644
> --- a/Documentation/gpu/amdgpu/index.rst
> +++ b/Documentation/gpu/amdgpu/index.rst
> @@ -10,6 +10,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
>     driver-core
>     amd-hardware-list-info
>     module-parameters
> +   gc/index
>     display/index
>     flashing
>     xgmi

[PATCH 6/6] Documentation/gpu: Add an intro about MES

[Rodrigo Siqueira]

MES is an important firmware that lacks some essential documentation.
This commit introduces an overview of it and how it works.

Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
 Documentation/gpu/amdgpu/driver-core.rst |  2 ++
 Documentation/gpu/amdgpu/gc/index.rst    |  7 ++++-
 Documentation/gpu/amdgpu/gc/mes.rst      | 38 ++++++++++++++++++++++++
 3 files changed, 46 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/gpu/amdgpu/gc/mes.rst

diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 2af1e919d76a..f39077c44799 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -77,6 +77,8 @@ VCN (Video Core Next)
     decode.  It's exposed to userspace for user mode drivers (VA-API,
     OpenMAX, etc.)
 
+.. _pipes-and-queues-description:
+
 GFX, Compute, and SDMA Overall Behavior
 =======================================
 
diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
index f8128cca7028..b115d5883959 100644
--- a/Documentation/gpu/amdgpu/gc/index.rst
+++ b/Documentation/gpu/amdgpu/gc/index.rst
@@ -39,10 +39,15 @@ CP (Command Processor)
         GFX/compute engine.
 
     MES (MicroEngine Scheduler)
-        This is the engine for managing queues.
+        This is the engine for managing queues. For more details check
+        :ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`.
 
 RLC (RunList Controller)
     This is another microcontroller in the GFX/Compute engine. It handles
     power management related functionality within the GFX/Compute engine.
     The name is a vestige of old hardware where it was originally added
     and doesn't really have much relation to what the engine does now.
+
+.. toctree::
+
+   mes.rst
diff --git a/Documentation/gpu/amdgpu/gc/mes.rst b/Documentation/gpu/amdgpu/gc/mes.rst
new file mode 100644
index 000000000000..b99eb211b179
--- /dev/null
+++ b/Documentation/gpu/amdgpu/gc/mes.rst
@@ -0,0 +1,38 @@
+.. _amdgpu-mes:
+
+=============================
+ MicroEngine Scheduler (MES)
+=============================
+
+.. note::
+   Queue and ring buffer are used as a synonymous.
+
+.. note::
+   This section assumes that you are familiar with the concept of Pipes, Queues, and GC.
+   If not, check :ref:`GFX, Compute, and SDMA Overall Behavior<pipes-and-queues-description>`
+   and :ref:`drm/amdgpu - Graphics and Compute (GC) <amdgpu-gc>`.
+
+Every GFX has a pipe component with one or more hardware queues. Pipes can
+switch between queues depending on certain conditions, and one of the
+components that can request a queue switch to a pipe is the MicroEngine
+Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
+hardware queue, and then the MQDs are handed to the MES firmware for mapping
+to:
+
+1. Kernel Queues (legacy): This queue is statically mapped to HQDs and never
+   preempted. Even though this is a legacy feature, it is the current default, and
+   most existing hardware supports it. When an application submits work to the
+   kernel driver, it submits all of the application command buffers to the kernel
+   queues. The CS IOCTL takes the command buffer from the applications and
+   schedules them on the kernel queue.
+
+2. User Queues: These queues are dynamically mapped to the HQDs. Regarding the
+   utilization of User Queues, the userspace application will create its user
+   queues and submit work directly to its user queues with no need to IOCTL for
+   each submission and no need to share a single kernel queue.
+
+In terms of User Queues, MES can dynamically map them to the HQD. If there are
+more MQDs than HQDs, the MES firmware will preempt other user queues to make
+sure each queues get a time slice; in other words, MES is a microcontroller
+that handles the mapping and unmapping of MQDs into HQDs, as well as the
+priorities and oversubscription of MQDs.
-- 
2.49.0

Re: [PATCH 6/6] Documentation/gpu: Add an intro about MES

[Bagas Sanjaya]

[-- Attachment #1: Type: text/plain, Size: 2478 bytes --]

On Tue, Mar 25, 2025 at 11:18:47AM -0600, Rodrigo Siqueira wrote:
> diff --git a/Documentation/gpu/amdgpu/gc/mes.rst b/Documentation/gpu/amdgpu/gc/mes.rst
> new file mode 100644
> index 000000000000..b99eb211b179
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/gc/mes.rst
> @@ -0,0 +1,38 @@
> +.. _amdgpu-mes:
> +
> +=============================
> + MicroEngine Scheduler (MES)
> +=============================
> +
> +.. note::
> +   Queue and ring buffer are used as a synonymous.
> +
> +.. note::
> +   This section assumes that you are familiar with the concept of Pipes, Queues, and GC.
> +   If not, check :ref:`GFX, Compute, and SDMA Overall Behavior<pipes-and-queues-description>`
> +   and :ref:`drm/amdgpu - Graphics and Compute (GC) <amdgpu-gc>`.
> +
> +Every GFX has a pipe component with one or more hardware queues. Pipes can
> +switch between queues depending on certain conditions, and one of the
> +components that can request a queue switch to a pipe is the MicroEngine
> +Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
> +hardware queue, and then the MQDs are handed to the MES firmware for mapping
> +to:
> +
> +1. Kernel Queues (legacy): This queue is statically mapped to HQDs and never
> +   preempted. Even though this is a legacy feature, it is the current default, and
> +   most existing hardware supports it. When an application submits work to the
> +   kernel driver, it submits all of the application command buffers to the kernel
> +   queues. The CS IOCTL takes the command buffer from the applications and
> +   schedules them on the kernel queue.
> +
> +2. User Queues: These queues are dynamically mapped to the HQDs. Regarding the
> +   utilization of User Queues, the userspace application will create its user
> +   queues and submit work directly to its user queues with no need to IOCTL for
> +   each submission and no need to share a single kernel queue.
> +
> +In terms of User Queues, MES can dynamically map them to the HQD. If there are
> +more MQDs than HQDs, the MES firmware will preempt other user queues to make
> +sure each queues get a time slice; in other words, MES is a microcontroller
> +that handles the mapping and unmapping of MQDs into HQDs, as well as the
> +priorities and oversubscription of MQDs.

The doc LGTM, thanks!

Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com>

-- 
An old man doll... just what I always wanted! - Clara

[-- Attachment #2: signature.asc --]
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Re: [PATCH 0/6] Documentation/gpu/amdgpu: Add documentation about Pipes, Queues, MES, and others

[Alex Deucher]

Applied the series with some minor clarifications per the comments and
my proof reading.

Thanks!

Alex

On Tue, Mar 25, 2025 at 1:27 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> Hi,
>
> This patchset came from my endeavor to understand better how some of the
> amdgpu components operate; in particular, I was focused on the ideas
> behind Pipes, Hardware Queues, MES, and Ring Buffers. In some way, this
> series is an attempt to put multiple pieces of information spread around
> many different places in an organized way in the amdgpu kernel-doc. In
> particular, the following links were crucial to create this series:
>
> * https://lore.kernel.org/amd-gfx/CADnq5_Pcz2x4aJzKbVrN3jsZhD6sTydtDw=6PaN4O3m4t+Grtg@mail.gmail.com/T/#m9a670b55ab20e0f7c46c80f802a0a4be255a719d
> * https://gitlab.freedesktop.org/mesa/mesa/-/issues/11759
> * https://www.x.org/docs/AMD/old/R5xx_Acceleration_v1.5.pdf
> * https://gpuopen.com/videos/graphics-pipeline/
>
> The first part of this series just updates the amdgpu-glossary with some
> new acronyms (some of them useful for other patches). The next two
> patches are just some basic organization to improve the documentation
> flow. The last part describes pipes, hardware queues, ring buffers, and
> MES.
>
> Thanks
> Siqueira
>
> Rodrigo Siqueira (6):
>   Documentation/gpu: Add new acronyms
>   Documentation/gpu: Change index order to show driver core first
>   Documentation/gpu: Create a documentation entry just for hardware info
>   Documentation/gpu: Add explanation about AMD Pipes and Queues
>   Documentation/gpu: Create a GC entry in the amdgpu documentation
>   Documentation/gpu: Add an intro about MES
>
>  .../gpu/amdgpu/amd-hardware-list-info.rst     |   23 +
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   36 +
>  Documentation/gpu/amdgpu/driver-core.rst      |   77 +-
>  Documentation/gpu/amdgpu/driver-misc.rst      |   17 -
>  Documentation/gpu/amdgpu/gc/index.rst         |   53 +
>  Documentation/gpu/amdgpu/gc/mes.rst           |   38 +
>  Documentation/gpu/amdgpu/index.rst            |    4 +-
>  .../gpu/amdgpu/pipe_and_queue_abstraction.svg | 1279 +++++++++++++++++
>  8 files changed, 1485 insertions(+), 42 deletions(-)
>  create mode 100644 Documentation/gpu/amdgpu/amd-hardware-list-info.rst
>  create mode 100644 Documentation/gpu/amdgpu/gc/index.rst
>  create mode 100644 Documentation/gpu/amdgpu/gc/mes.rst
>  create mode 100644 Documentation/gpu/amdgpu/pipe_and_queue_abstraction.svg
>
> --
> 2.49.0
>