* [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 7:50 ` Krzysztof Kozlowski
` (2 more replies)
2025-11-26 9:38 ` [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
` (5 subsequent siblings)
6 siblings, 3 replies; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add SM8750 compatible consistent with CAMSS CCI interfaces.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
index 33852a5ffca8..a3fe1eea6aec 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
@@ -38,6 +38,7 @@ properties:
- qcom,sm8450-cci
- qcom,sm8550-cci
- qcom,sm8650-cci
+ - qcom,sm8750-cci
- qcom,x1e80100-cci
- const: qcom,msm8996-cci # CCI v2
@@ -132,6 +133,7 @@ allOf:
enum:
- qcom,kaanapali-cci
- qcom,qcm2290-cci
+ - qcom,sm8750-cci
then:
properties:
clocks:
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible
2025-11-26 9:38 ` [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible Hangxiang Ma
@ 2025-11-27 7:50 ` Krzysztof Kozlowski
2025-11-27 9:44 ` Bryan O'Donoghue
2025-12-03 20:52 ` Andi Shyti
2 siblings, 0 replies; 29+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-27 7:50 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On Wed, Nov 26, 2025 at 01:38:34AM -0800, Hangxiang Ma wrote:
> Add SM8750 compatible consistent with CAMSS CCI interfaces.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible
2025-11-26 9:38 ` [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible Hangxiang Ma
2025-11-27 7:50 ` Krzysztof Kozlowski
@ 2025-11-27 9:44 ` Bryan O'Donoghue
2025-12-03 20:52 ` Andi Shyti
2 siblings, 0 replies; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 9:44 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add SM8750 compatible consistent with CAMSS CCI interfaces.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> index 33852a5ffca8..a3fe1eea6aec 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
> @@ -38,6 +38,7 @@ properties:
> - qcom,sm8450-cci
> - qcom,sm8550-cci
> - qcom,sm8650-cci
> + - qcom,sm8750-cci
> - qcom,x1e80100-cci
> - const: qcom,msm8996-cci # CCI v2
>
> @@ -132,6 +133,7 @@ allOf:
> enum:
> - qcom,kaanapali-cci
> - qcom,qcm2290-cci
> + - qcom,sm8750-cci
> then:
> properties:
> clocks:
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible
2025-11-26 9:38 ` [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible Hangxiang Ma
2025-11-27 7:50 ` Krzysztof Kozlowski
2025-11-27 9:44 ` Bryan O'Donoghue
@ 2025-12-03 20:52 ` Andi Shyti
2 siblings, 0 replies; 29+ messages in thread
From: Andi Shyti @ 2025-12-03 20:52 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Todor Tomov, Vladimir Zapolskiy,
Mauro Carvalho Chehab, Bryan O'Donoghue, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
Hi Hangxiang,
On Wed, Nov 26, 2025 at 01:38:34AM -0800, Hangxiang Ma wrote:
> Add SM8750 compatible consistent with CAMSS CCI interfaces.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
Just this patch merged to i2c/i2c-host.
Thanks,
Andi
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
2025-11-26 9:38 ` [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 8:10 ` Krzysztof Kozlowski
2025-11-27 9:46 ` Bryan O'Donoghue
2025-11-26 9:38 ` [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver Hangxiang Ma
` (4 subsequent siblings)
6 siblings, 2 replies; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add the compatible string "qcom,sm8750-camss" to support the Camera
Subsystem (CAMSS) on the Qualcomm SM8750 platform.
The SM8750 platform provides:
- 3 x VFE, 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE Lite
- 3 x CSID
- 2 x CSID Lite
- 6 x CSIPHY
- 2 x ICP
- 1 x IPE
- 2 x JPEG DMA & Downscaler
- 2 x JPEG Encoder
- 1 x OFE
- 5 x RT CDM
- 3 x TPG
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++++++
1 file changed, 664 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
new file mode 100644
index 000000000000..6b2b0b5a7e19
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
@@ -0,0 +1,664 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8750 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
+
+description:
+ This binding describes the camera subsystem hardware found on SM8750 Qualcomm
+ SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID
+ (CSI Decoder), which comply with the MIPI CSI2 protocol.
+
+ The subsystem also integrates a set of real-time image processing engines and
+ their associated configuration modules, as well as non-real-time engines.
+
+ Additionally, it encompasses a test pattern generator (TPG) submodule.
+
+properties:
+ compatible:
+ const: qcom,sm8750-camss
+
+ reg:
+ items:
+ - description: Registers for CSID 0
+ - description: Registers for CSID 1
+ - description: Registers for CSID 2
+ - description: Registers for CSID Lite 0
+ - description: Registers for CSID Lite 1
+ - description: Registers for CSIPHY 0
+ - description: Registers for CSIPHY 1
+ - description: Registers for CSIPHY 2
+ - description: Registers for CSIPHY 3
+ - description: Registers for CSIPHY 4
+ - description: Registers for CSIPHY 5
+ - description: Registers for VFE (Video Front End) 0
+ - description: Registers for VFE 1
+ - description: Registers for VFE 2
+ - description: Registers for VFE Lite 0
+ - description: Registers for VFE Lite 1
+ - description: Registers for ICP (Imaging Control Processor) 0
+ - description: Registers for ICP SYS 0
+ - description: Registers for ICP 1
+ - description: Registers for ICP SYS 1
+ - description: Registers for IPE (Image Processing Engine)
+ - description: Registers for JPEG DMA & Downscaler 0
+ - description: Registers for JPEG Encoder 0
+ - description: Registers for JPEG DMA & Downscaler 1
+ - description: Registers for JPEG Encoder 1
+ - description: Registers for OFE (Offline Front End)
+ - description: Registers for RT CDM (Camera Data Mover) 0
+ - description: Registers for RT CDM 1
+ - description: Registers for RT CDM 2
+ - description: Registers for RT CDM 3
+ - description: Registers for RT CDM 4
+ - description: Registers for TPG 0
+ - description: Registers for TPG 1
+ - description: Registers for TPG 2
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: icp0
+ - const: icp0_sys
+ - const: icp1
+ - const: icp1_sys
+ - const: ipe
+ - const: jpeg_dma0
+ - const: jpeg_enc0
+ - const: jpeg_dma1
+ - const: jpeg_enc1
+ - const: ofe
+ - const: rt_cdm0
+ - const: rt_cdm1
+ - const: rt_cdm2
+ - const: rt_cdm3
+ - const: rt_cdm4
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+
+ clocks:
+ maxItems: 61
+
+ clock-names:
+ items:
+ - const: camnoc_nrt_axi
+ - const: camnoc_rt_axi
+ - const: camnoc_rt_vfe0
+ - const: camnoc_rt_vfe1
+ - const: camnoc_rt_vfe2
+ - const: camnoc_rt_vfe_lite
+ - const: cam_top_ahb
+ - const: cam_top_fast_ahb
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: csiphy5
+ - const: csiphy5_timer
+ - const: gcc_hf_axi
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe2
+ - const: vfe2_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: qdss_debug_xo
+ - const: camnoc_ipe_nps
+ - const: camnoc_ofe
+ - const: gcc_sf_axi
+ - const: icp0
+ - const: icp0_ahb
+ - const: icp1
+ - const: icp1_ahb
+ - const: ipe_nps
+ - const: ipe_nps_ahb
+ - const: ipe_nps_fast_ahb
+ - const: ipe_pps
+ - const: ipe_pps_fast_ahb
+ - const: jpeg0
+ - const: jpeg1
+ - const: ofe_ahb
+ - const: ofe_anchor
+ - const: ofe_anchor_fast_ahb
+ - const: ofe_hdr
+ - const: ofe_hdr_fast_ahb
+ - const: ofe_main
+ - const: ofe_main_fast_ahb
+ - const: vfe0_bayer
+ - const: vfe0_bayer_fast_ahb
+ - const: vfe1_bayer
+ - const: vfe1_bayer_fast_ahb
+ - const: vfe2_bayer
+ - const: vfe2_bayer_fast_ahb
+
+ interrupts:
+ maxItems: 32
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: csiphy4
+ - const: csiphy5
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: camnoc_nrt
+ - const: camnoc_rt
+ - const: icp0
+ - const: icp1
+ - const: jpeg_dma0
+ - const: jpeg_enc0
+ - const: jpeg_dma1
+ - const: jpeg_enc1
+ - const: rt_cdm0
+ - const: rt_cdm1
+ - const: rt_cdm2
+ - const: rt_cdm3
+ - const: rt_cdm4
+ - const: tpg0
+ - const: tpg1
+ - const: tpg2
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_icp_mnoc
+ - const: sf_mnoc
+
+ iommus:
+ items:
+ - description: VFE non-protected stream
+ - description: ICP0 shared stream
+ - description: ICP1 shared stream
+ - description: IPE CDM non-protected stream
+ - description: IPE non-protected stream
+ - description: JPEG non-protected stream
+ - description: OFE CDM non-protected stream
+ - description: OFE non-protected stream
+ - description: VFE / VFE Lite CDM non-protected stream
+
+ power-domains:
+ items:
+ - description:
+ VFE0 GDSC - Global Distributed Switch Controller for VFE0.
+ - description:
+ VFE1 GDSC - Global Distributed Switch Controller for VFE1.
+ - description:
+ VFE2 GDSC - Global Distributed Switch Controller for VFE2.
+ - description:
+ Titan GDSC - Global Distributed Switch Controller for the entire camss.
+ - description:
+ IPE GDSC - Global Distributed Switch Controller for IPE.
+ - description:
+ OFE GDSC - Block Global Distributed Switch Controller for OFE.
+
+ power-domain-names:
+ items:
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: top
+ - const: ipe
+ - const: ofe
+
+ vdd-csiphy0-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY0 core block.
+
+ vdd-csiphy0-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
+
+ vdd-csiphy1-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY1 core block.
+
+ vdd-csiphy1-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY1 pll block.
+
+ vdd-csiphy2-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY2 core block.
+
+ vdd-csiphy2-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY2 pll block.
+
+ vdd-csiphy3-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY3 core block.
+
+ vdd-csiphy3-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY3 pll block.
+
+ vdd-csiphy4-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY4 core block.
+
+ vdd-csiphy4-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY4 pll block.
+
+ vdd-csiphy5-0p88-supply:
+ description:
+ Phandle to a 0.88V regulator supply to CSIPHY5 core block.
+
+ vdd-csiphy5-1p2-supply:
+ description:
+ Phandle to a 1.2V regulator supply to CSIPHY5 pll block.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-5]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Input ports for receiving CSI data on CSIPHY 0-5.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@ad27000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ada9000 0x0 0x2000>,
+ <0x0 0x0adab000 0x0 0x2000>,
+ <0x0 0x0adad000 0x0 0x2000>,
+ <0x0 0x0adaf000 0x0 0x2000>,
+ <0x0 0x0adb1000 0x0 0x2000>,
+ <0x0 0x0adb3000 0x0 0x2000>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x1800>,
+ <0x0 0x0ad73000 0x0 0x1800>,
+ <0x0 0x0ac06000 0x0 0x1000>,
+ <0x0 0x0ac05000 0x0 0x1000>,
+ <0x0 0x0ac16000 0x0 0x1000>,
+ <0x0 0x0ac15000 0x0 0x1000>,
+ <0x0 0x0ac42000 0x0 0x18000>,
+ <0x0 0x0ac26000 0x0 0x1000>,
+ <0x0 0x0ac25000 0x0 0x1000>,
+ <0x0 0x0ac28000 0x0 0x1000>,
+ <0x0 0x0ac27000 0x0 0x1000>,
+ <0x0 0x0ac2a000 0x0 0x18000>,
+ <0x0 0x0ac7f000 0x0 0x580>,
+ <0x0 0x0ac80000 0x0 0x580>,
+ <0x0 0x0ac81000 0x0 0x580>,
+ <0x0 0x0ac82000 0x0 0x580>,
+ <0x0 0x0ac83000 0x0 0x580>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "icp0",
+ "icp0_sys",
+ "icp1",
+ "icp1_sys",
+ "ipe",
+ "jpeg_dma0",
+ "jpeg_enc0",
+ "jpeg_dma1",
+ "jpeg_enc1",
+ "ofe",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ clocks = <&camcc_cam_cc_camnoc_nrt_axi_clk>,
+ <&camcc_cam_cc_camnoc_rt_axi_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>,
+ <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>,
+ <&camcc_cam_cc_cam_top_ahb_clk>,
+ <&camcc_cam_cc_cam_top_fast_ahb_clk>,
+ <&camcc_cam_cc_csid_clk>,
+ <&camcc_cam_cc_csid_csiphy_rx_clk>,
+ <&camcc_cam_cc_csiphy0_clk>,
+ <&camcc_cam_cc_csi0phytimer_clk>,
+ <&camcc_cam_cc_csiphy1_clk>,
+ <&camcc_cam_cc_csi1phytimer_clk>,
+ <&camcc_cam_cc_csiphy2_clk>,
+ <&camcc_cam_cc_csi2phytimer_clk>,
+ <&camcc_cam_cc_csiphy3_clk>,
+ <&camcc_cam_cc_csi3phytimer_clk>,
+ <&camcc_cam_cc_csiphy4_clk>,
+ <&camcc_cam_cc_csi4phytimer_clk>,
+ <&camcc_cam_cc_csiphy5_clk>,
+ <&camcc_cam_cc_csi5phytimer_clk>,
+ <&gcc_gcc_camera_hf_axi_clk>,
+ <&camcc_cam_cc_vfe_0_main_clk>,
+ <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_1_main_clk>,
+ <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_2_main_clk>,
+ <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_lite_clk>,
+ <&camcc_cam_cc_vfe_lite_ahb_clk>,
+ <&camcc_cam_cc_vfe_lite_cphy_rx_clk>,
+ <&camcc_cam_cc_vfe_lite_csid_clk>,
+ <&camcc_cam_cc_qdss_debug_xo_clk>,
+ <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>,
+ <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>,
+ <&gcc_gcc_camera_sf_axi_clk>,
+ <&camcc_cam_cc_icp_0_clk>,
+ <&camcc_cam_cc_icp_0_ahb_clk>,
+ <&camcc_cam_cc_icp_1_clk>,
+ <&camcc_cam_cc_icp_1_ahb_clk>,
+ <&camcc_cam_cc_ipe_nps_clk>,
+ <&camcc_cam_cc_ipe_nps_ahb_clk>,
+ <&camcc_cam_cc_ipe_nps_fast_ahb_clk>,
+ <&camcc_cam_cc_ipe_pps_clk>,
+ <&camcc_cam_cc_ipe_pps_fast_ahb_clk>,
+ <&camcc_cam_cc_jpeg_0_clk>,
+ <&camcc_cam_cc_jpeg_1_clk>,
+ <&camcc_cam_cc_ofe_ahb_clk>,
+ <&camcc_cam_cc_ofe_anchor_clk>,
+ <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>,
+ <&camcc_cam_cc_ofe_hdr_clk>,
+ <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>,
+ <&camcc_cam_cc_ofe_main_clk>,
+ <&camcc_cam_cc_ofe_main_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_0_bayer_clk>,
+ <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_1_bayer_clk>,
+ <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>,
+ <&camcc_cam_cc_vfe_2_bayer_clk>,
+ <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_rt_vfe0",
+ "camnoc_rt_vfe1",
+ "camnoc_rt_vfe2",
+ "camnoc_rt_vfe_lite",
+ "cam_top_ahb",
+ "cam_top_fast_ahb",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "gcc_hf_axi",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo",
+ "camnoc_ipe_nps",
+ "camnoc_ofe",
+ "gcc_sf_axi",
+ "icp0",
+ "icp0_ahb",
+ "icp1",
+ "icp1_ahb",
+ "ipe_nps",
+ "ipe_nps_ahb",
+ "ipe_nps_fast_ahb",
+ "ipe_pps",
+ "ipe_pps_fast_ahb",
+ "jpeg0",
+ "jpeg1",
+ "ofe_ahb",
+ "ofe_anchor",
+ "ofe_anchor_fast_ahb",
+ "ofe_hdr",
+ "ofe_hdr_fast_ahb",
+ "ofe_main",
+ "ofe_main_fast_ahb",
+ "vfe0_bayer",
+ "vfe0_bayer_fast_ahb",
+ "vfe1_bayer",
+ "vfe1_bayer_fast_ahb",
+ "vfe2_bayer",
+ "vfe2_bayer_fast_ahb";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "camnoc_nrt",
+ "camnoc_rt",
+ "icp0",
+ "icp1",
+ "jpeg_dma0",
+ "jpeg_enc0",
+ "jpeg_dma1",
+ "jpeg_enc1",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ interconnects = <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc_master_camnoc_nrt_icp_sf QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS
+ &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_icp_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>,
+ <&apps_smmu 0x18c0 0x00>,
+ <&apps_smmu 0x1980 0x00>,
+ <&apps_smmu 0x1840 0x00>,
+ <&apps_smmu 0x1800 0x00>,
+ <&apps_smmu 0x18a0 0x00>,
+ <&apps_smmu 0x1880 0x00>,
+ <&apps_smmu 0x1820 0x00>,
+ <&apps_smmu 0x1860 0x00>;
+
+ power-domains = <&camcc_cam_cc_vfe_0_gdsc>,
+ <&camcc_cam_cc_vfe_1_gdsc>,
+ <&camcc_cam_cc_vfe_2_gdsc>,
+ <&camcc_cam_cc_titan_top_gdsc>,
+ <&camcc_cam_cc_ipe_0_gdsc>,
+ <&camcc_cam_cc_ofe_gdsc>;
+ power-domain-names = "vfe0",
+ "vfe1",
+ "vfe2",
+ "top",
+ "ipe",
+ "ofe";
+
+ vdd-csiphy0-0p88-supply = <&vreg_0p88_supply>;
+ vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy_ep0: endpoint {
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-11-26 9:38 ` [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
@ 2025-11-27 8:10 ` Krzysztof Kozlowski
2025-12-04 1:31 ` Vladimir Zapolskiy
2026-01-06 18:02 ` Vijay Kumar Tumati
2025-11-27 9:46 ` Bryan O'Donoghue
1 sibling, 2 replies; 29+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-27 8:10 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On Wed, Nov 26, 2025 at 01:38:35AM -0800, Hangxiang Ma wrote:
> Add the compatible string "qcom,sm8750-camss" to support the Camera
s/to support the/for the/
Bindings do not support hardware.
> Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>
> The SM8750 platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSIPHY
> - 2 x ICP
> - 1 x IPE
> - 2 x JPEG DMA & Downscaler
> - 2 x JPEG Encoder
> - 1 x OFE
> - 5 x RT CDM
> - 3 x TPG
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++++++
> 1 file changed, 664 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> new file mode 100644
> index 000000000000..6b2b0b5a7e19
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> @@ -0,0 +1,664 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8750 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> +
> +description:
> + This binding describes the camera subsystem hardware found on SM8750 Qualcomm
s/This binding ..../SM8750 CAMSS (Camera Subsystem) is foo bar..../
or any other form which will describe the hardware. There is no point to
say that binding describes hardware. It cannot describe anything else.
> + SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID
> + (CSI Decoder), which comply with the MIPI CSI2 protocol.
> +
> + The subsystem also integrates a set of real-time image processing engines and
> + their associated configuration modules, as well as non-real-time engines.
> +
> + Additionally, it encompasses a test pattern generator (TPG) submodule.
> +
> +properties:
> + compatible:
> + const: qcom,sm8750-camss
> +
> + reg:
> + items:
> + - description: Registers for CSID 0
> + - description: Registers for CSID 1
> + - description: Registers for CSID 2
> + - description: Registers for CSID Lite 0
> + - description: Registers for CSID Lite 1
> + - description: Registers for CSIPHY 0
> + - description: Registers for CSIPHY 1
> + - description: Registers for CSIPHY 2
> + - description: Registers for CSIPHY 3
> + - description: Registers for CSIPHY 4
> + - description: Registers for CSIPHY 5
> + - description: Registers for VFE (Video Front End) 0
> + - description: Registers for VFE 1
> + - description: Registers for VFE 2
> + - description: Registers for VFE Lite 0
> + - description: Registers for VFE Lite 1
> + - description: Registers for ICP (Imaging Control Processor) 0
> + - description: Registers for ICP SYS 0
> + - description: Registers for ICP 1
> + - description: Registers for ICP SYS 1
> + - description: Registers for IPE (Image Processing Engine)
> + - description: Registers for JPEG DMA & Downscaler 0
> + - description: Registers for JPEG Encoder 0
> + - description: Registers for JPEG DMA & Downscaler 1
> + - description: Registers for JPEG Encoder 1
> + - description: Registers for OFE (Offline Front End)
> + - description: Registers for RT CDM (Camera Data Mover) 0
> + - description: Registers for RT CDM 1
> + - description: Registers for RT CDM 2
> + - description: Registers for RT CDM 3
> + - description: Registers for RT CDM 4
> + - description: Registers for TPG 0
> + - description: Registers for TPG 1
> + - description: Registers for TPG 2
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
I had impression there were talks and plans to split CSI PHY out of
camss. Some other patches got blocked by this, so unfortunately this as
well. Your cover letter does not answer on this, so unfortuntaly this
concludes the review.
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: icp0
> + - const: icp0_sys
> + - const: icp1
> + - const: icp1_sys
> + - const: ipe
> + - const: jpeg_dma0
> + - const: jpeg_enc0
> + - const: jpeg_dma1
> + - const: jpeg_enc1
> + - const: ofe
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + clocks:
> + maxItems: 61
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: camnoc_rt_vfe0
> + - const: camnoc_rt_vfe1
> + - const: camnoc_rt_vfe2
> + - const: camnoc_rt_vfe_lite
> + - const: cam_top_ahb
cpas_ahb?
> + - const: cam_top_fast_ahb
Isn't this cpas_fast_ahb? Why every schema comes with its own naming...
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: csiphy5
> + - const: csiphy5_timer
> + - const: gcc_hf_axi
Look at previous generation how this is called: gcc_axi_hf. Use that
name.
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe2
> + - const: vfe2_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> + - const: qdss_debug_xo
> + - const: camnoc_ipe_nps
> + - const: camnoc_ofe
> + - const: gcc_sf_axi
> + - const: icp0
> + - const: icp0_ahb
> + - const: icp1
> + - const: icp1_ahb
> + - const: ipe_nps
> + - const: ipe_nps_ahb
> + - const: ipe_nps_fast_ahb
> + - const: ipe_pps
> + - const: ipe_pps_fast_ahb
> + - const: jpeg0
> + - const: jpeg1
> + - const: ofe_ahb
> + - const: ofe_anchor
> + - const: ofe_anchor_fast_ahb
> + - const: ofe_hdr
> + - const: ofe_hdr_fast_ahb
> + - const: ofe_main
> + - const: ofe_main_fast_ahb
> + - const: vfe0_bayer
> + - const: vfe0_bayer_fast_ahb
> + - const: vfe1_bayer
> + - const: vfe1_bayer_fast_ahb
> + - const: vfe2_bayer
> + - const: vfe2_bayer_fast_ahb
> +
> + interrupts:
> + maxItems: 32
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: camnoc_nrt
> + - const: camnoc_rt
> + - const: icp0
> + - const: icp1
> + - const: jpeg_dma0
> + - const: jpeg_enc0
> + - const: jpeg_dma1
> + - const: jpeg_enc1
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_icp_mnoc
> + - const: sf_mnoc
Which previous generation you used as ordering style? X1E has it
different.
> +
> + iommus:
> + items:
> + - description: VFE non-protected stream
> + - description: ICP0 shared stream
> + - description: ICP1 shared stream
> + - description: IPE CDM non-protected stream
> + - description: IPE non-protected stream
> + - description: JPEG non-protected stream
> + - description: OFE CDM non-protected stream
> + - description: OFE non-protected stream
> + - description: VFE / VFE Lite CDM non-protected stream
> +
> + power-domains:
> + items:
> + - description:
> + VFE0 GDSC - Global Distributed Switch Controller for VFE0.
> + - description:
> + VFE1 GDSC - Global Distributed Switch Controller for VFE1.
> + - description:
> + VFE2 GDSC - Global Distributed Switch Controller for VFE2.
> + - description:
> + Titan GDSC - Global Distributed Switch Controller for the entire camss.
> + - description:
> + IPE GDSC - Global Distributed Switch Controller for IPE.
> + - description:
> + OFE GDSC - Block Global Distributed Switch Controller for OFE.
> +
> + power-domain-names:
> + items:
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
Previous generations call these IFE, I already raised this and you
changed to ife in Kaanapali. So are all future devices going to use
rather VFE name?
> + - const: top
> + - const: ipe
> + - const: ofe
> +
> + vdd-csiphy0-0p88-supply:
88->8, so: vdd-csiphy0-0p8-supply:
Same in other places. This is how it is called for every binding.
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY0 core block.
> +
> + vdd-csiphy0-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
> +
> + vdd-csiphy1-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY1 core block.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-11-27 8:10 ` Krzysztof Kozlowski
@ 2025-12-04 1:31 ` Vladimir Zapolskiy
2026-01-06 18:04 ` Vijay Kumar Tumati
2026-01-06 18:02 ` Vijay Kumar Tumati
1 sibling, 1 reply; 29+ messages in thread
From: Vladimir Zapolskiy @ 2025-12-04 1:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bryan O'Donoghue, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 11/27/25 10:10, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 01:38:35AM -0800, Hangxiang Ma wrote:
>> Add the compatible string "qcom,sm8750-camss" to support the Camera
>
> s/to support the/for the/
>
> Bindings do not support hardware.
>
>> Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>>
>> The SM8750 platform provides:
>> - 3 x VFE, 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>> - 3 x CSID
>> - 2 x CSID Lite
>> - 6 x CSIPHY
>> - 2 x ICP
>> - 1 x IPE
>> - 2 x JPEG DMA & Downscaler
>> - 2 x JPEG Encoder
>> - 1 x OFE
>> - 5 x RT CDM
>> - 3 x TPG
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++++++
>> 1 file changed, 664 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
<snip>
>> +
>> + vdd-csiphy0-0p88-supply:
>
> 88->8, so: vdd-csiphy0-0p8-supply:
I would make a minor correction here, it'd be rather 0p9.
> Same in other places. This is how it is called for every binding.
>
>> + description:
>> + Phandle to a 0.88V regulator supply to CSIPHY0 core block.
>> +
>> + vdd-csiphy0-1p2-supply:
>> + description:
>> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
>> +
>> + vdd-csiphy1-0p88-supply:
>> + description:
>> + Phandle to a 0.88V regulator supply to CSIPHY1 core block.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-12-04 1:31 ` Vladimir Zapolskiy
@ 2026-01-06 18:04 ` Vijay Kumar Tumati
0 siblings, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:04 UTC (permalink / raw)
To: Vladimir Zapolskiy, Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bryan O'Donoghue, linux-i2c,
linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 12/3/2025 5:31 PM, Vladimir Zapolskiy wrote:
> On 11/27/25 10:10, Krzysztof Kozlowski wrote:
>> On Wed, Nov 26, 2025 at 01:38:35AM -0800, Hangxiang Ma wrote:
>>> Add the compatible string "qcom,sm8750-camss" to support the Camera
>>
>> s/to support the/for the/
>>
>> Bindings do not support hardware.
>>
>>> Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>>>
>>> The SM8750 platform provides:
>>> - 3 x VFE, 5 RDI per VFE
>>> - 2 x VFE Lite, 4 RDI per VFE Lite
>>> - 3 x CSID
>>> - 2 x CSID Lite
>>> - 6 x CSIPHY
>>> - 2 x ICP
>>> - 1 x IPE
>>> - 2 x JPEG DMA & Downscaler
>>> - 2 x JPEG Encoder
>>> - 1 x OFE
>>> - 5 x RT CDM
>>> - 3 x TPG
>>>
>>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>>> ---
>>> .../bindings/media/qcom,sm8750-camss.yaml | 664
>>> +++++++++++++++++++++
>>> 1 file changed, 664 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
>>> b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
>
> <snip>
>
>>> +
>>> + vdd-csiphy0-0p88-supply:
>>
>> 88->8, so: vdd-csiphy0-0p8-supply:
>
> I would make a minor correction here, it'd be rather 0p9.
Sure, thanks.
>
>> Same in other places. This is how it is called for every binding.
>>
>>> + description:
>>> + Phandle to a 0.88V regulator supply to CSIPHY0 core block.
>>> +
>>> + vdd-csiphy0-1p2-supply:
>>> + description:
>>> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
>>> +
>>> + vdd-csiphy1-0p88-supply:
>>> + description:
>>> + Phandle to a 0.88V regulator supply to CSIPHY1 core block.
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-11-27 8:10 ` Krzysztof Kozlowski
2025-12-04 1:31 ` Vladimir Zapolskiy
@ 2026-01-06 18:02 ` Vijay Kumar Tumati
1 sibling, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:02 UTC (permalink / raw)
To: Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 11/27/2025 12:10 AM, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 01:38:35AM -0800, Hangxiang Ma wrote:
>> Add the compatible string "qcom,sm8750-camss" to support the Camera
> s/to support the/for the/
>
> Bindings do not support hardware.
Ack
>
>> Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>>
>> The SM8750 platform provides:
>> - 3 x VFE, 5 RDI per VFE
>> - 2 x VFE Lite, 4 RDI per VFE Lite
>> - 3 x CSID
>> - 2 x CSID Lite
>> - 6 x CSIPHY
>> - 2 x ICP
>> - 1 x IPE
>> - 2 x JPEG DMA & Downscaler
>> - 2 x JPEG Encoder
>> - 1 x OFE
>> - 5 x RT CDM
>> - 3 x TPG
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++++++
>> 1 file changed, 664 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
>> new file mode 100644
>> index 000000000000..6b2b0b5a7e19
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
>> @@ -0,0 +1,664 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SM8750 Camera Subsystem (CAMSS)
>> +
>> +maintainers:
>> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> +
>> +description:
>> + This binding describes the camera subsystem hardware found on SM8750 Qualcomm
> s/This binding ..../SM8750 CAMSS (Camera Subsystem) is foo bar..../
>
> or any other form which will describe the hardware. There is no point to
> say that binding describes hardware. It cannot describe anything else.
Ack
>
>> + SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID
>> + (CSI Decoder), which comply with the MIPI CSI2 protocol.
>> +
>> + The subsystem also integrates a set of real-time image processing engines and
>> + their associated configuration modules, as well as non-real-time engines.
>> +
>> + Additionally, it encompasses a test pattern generator (TPG) submodule.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sm8750-camss
>> +
>> + reg:
>> + items:
>> + - description: Registers for CSID 0
>> + - description: Registers for CSID 1
>> + - description: Registers for CSID 2
>> + - description: Registers for CSID Lite 0
>> + - description: Registers for CSID Lite 1
>> + - description: Registers for CSIPHY 0
>> + - description: Registers for CSIPHY 1
>> + - description: Registers for CSIPHY 2
>> + - description: Registers for CSIPHY 3
>> + - description: Registers for CSIPHY 4
>> + - description: Registers for CSIPHY 5
>> + - description: Registers for VFE (Video Front End) 0
>> + - description: Registers for VFE 1
>> + - description: Registers for VFE 2
>> + - description: Registers for VFE Lite 0
>> + - description: Registers for VFE Lite 1
>> + - description: Registers for ICP (Imaging Control Processor) 0
>> + - description: Registers for ICP SYS 0
>> + - description: Registers for ICP 1
>> + - description: Registers for ICP SYS 1
>> + - description: Registers for IPE (Image Processing Engine)
>> + - description: Registers for JPEG DMA & Downscaler 0
>> + - description: Registers for JPEG Encoder 0
>> + - description: Registers for JPEG DMA & Downscaler 1
>> + - description: Registers for JPEG Encoder 1
>> + - description: Registers for OFE (Offline Front End)
>> + - description: Registers for RT CDM (Camera Data Mover) 0
>> + - description: Registers for RT CDM 1
>> + - description: Registers for RT CDM 2
>> + - description: Registers for RT CDM 3
>> + - description: Registers for RT CDM 4
>> + - description: Registers for TPG 0
>> + - description: Registers for TPG 1
>> + - description: Registers for TPG 2
>> +
>> + reg-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: csiphy3
>> + - const: csiphy4
>> + - const: csiphy5
> I had impression there were talks and plans to split CSI PHY out of
> camss. Some other patches got blocked by this, so unfortunately this as
> well. Your cover letter does not answer on this, so unfortuntaly this
> concludes the review.
I believe we are not blocking the ongoing patches for this. I will let
Bryan confirm this.
>
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> + - const: icp0
>> + - const: icp0_sys
>> + - const: icp1
>> + - const: icp1_sys
>> + - const: ipe
>> + - const: jpeg_dma0
>> + - const: jpeg_enc0
>> + - const: jpeg_dma1
>> + - const: jpeg_enc1
>> + - const: ofe
>> + - const: rt_cdm0
>> + - const: rt_cdm1
>> + - const: rt_cdm2
>> + - const: rt_cdm3
>> + - const: rt_cdm4
>> + - const: tpg0
>> + - const: tpg1
>> + - const: tpg2
>> +
>> + clocks:
>> + maxItems: 61
>> +
>> + clock-names:
>> + items:
>> + - const: camnoc_nrt_axi
>> + - const: camnoc_rt_axi
>> + - const: camnoc_rt_vfe0
>> + - const: camnoc_rt_vfe1
>> + - const: camnoc_rt_vfe2
>> + - const: camnoc_rt_vfe_lite
>> + - const: cam_top_ahb
> cpas_ahb?
Ack
>
>> + - const: cam_top_fast_ahb
> Isn't this cpas_fast_ahb? Why every schema comes with its own naming...
Ack. These were based on Kaanapali patches but we updated these there
too. Will do the same here.
>> + - const: csid
>> + - const: csid_csiphy_rx
>> + - const: csiphy0
>> + - const: csiphy0_timer
>> + - const: csiphy1
>> + - const: csiphy1_timer
>> + - const: csiphy2
>> + - const: csiphy2_timer
>> + - const: csiphy3
>> + - const: csiphy3_timer
>> + - const: csiphy4
>> + - const: csiphy4_timer
>> + - const: csiphy5
>> + - const: csiphy5_timer
>> + - const: gcc_hf_axi
> Look at previous generation how this is called: gcc_axi_hf. Use that
> name.
Ack
>
>> + - const: vfe0
>> + - const: vfe0_fast_ahb
>> + - const: vfe1
>> + - const: vfe1_fast_ahb
>> + - const: vfe2
>> + - const: vfe2_fast_ahb
>> + - const: vfe_lite
>> + - const: vfe_lite_ahb
>> + - const: vfe_lite_cphy_rx
>> + - const: vfe_lite_csid
>> + - const: qdss_debug_xo
>> + - const: camnoc_ipe_nps
>> + - const: camnoc_ofe
>> + - const: gcc_sf_axi
>> + - const: icp0
>> + - const: icp0_ahb
>> + - const: icp1
>> + - const: icp1_ahb
>> + - const: ipe_nps
>> + - const: ipe_nps_ahb
>> + - const: ipe_nps_fast_ahb
>> + - const: ipe_pps
>> + - const: ipe_pps_fast_ahb
>> + - const: jpeg0
>> + - const: jpeg1
>> + - const: ofe_ahb
>> + - const: ofe_anchor
>> + - const: ofe_anchor_fast_ahb
>> + - const: ofe_hdr
>> + - const: ofe_hdr_fast_ahb
>> + - const: ofe_main
>> + - const: ofe_main_fast_ahb
>> + - const: vfe0_bayer
>> + - const: vfe0_bayer_fast_ahb
>> + - const: vfe1_bayer
>> + - const: vfe1_bayer_fast_ahb
>> + - const: vfe2_bayer
>> + - const: vfe2_bayer_fast_ahb
>> +
>> + interrupts:
>> + maxItems: 32
>> +
>> + interrupt-names:
>> + items:
>> + - const: csid0
>> + - const: csid1
>> + - const: csid2
>> + - const: csid_lite0
>> + - const: csid_lite1
>> + - const: csiphy0
>> + - const: csiphy1
>> + - const: csiphy2
>> + - const: csiphy3
>> + - const: csiphy4
>> + - const: csiphy5
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
>> + - const: vfe_lite0
>> + - const: vfe_lite1
>> + - const: camnoc_nrt
>> + - const: camnoc_rt
>> + - const: icp0
>> + - const: icp1
>> + - const: jpeg_dma0
>> + - const: jpeg_enc0
>> + - const: jpeg_dma1
>> + - const: jpeg_enc1
>> + - const: rt_cdm0
>> + - const: rt_cdm1
>> + - const: rt_cdm2
>> + - const: rt_cdm3
>> + - const: rt_cdm4
>> + - const: tpg0
>> + - const: tpg1
>> + - const: tpg2
>> +
>> + interconnects:
>> + maxItems: 4
>> +
>> + interconnect-names:
>> + items:
>> + - const: ahb
>> + - const: hf_mnoc
>> + - const: sf_icp_mnoc
>> + - const: sf_mnoc
> Which previous generation you used as ordering style? X1E has it
> different.
The ordering is based on Kaanapali patches. Some names have been updated
on the latest Kaanapali patches to be consistent with previous
generations. and will update those here too.
>> +
>> + iommus:
>> + items:
>> + - description: VFE non-protected stream
>> + - description: ICP0 shared stream
>> + - description: ICP1 shared stream
>> + - description: IPE CDM non-protected stream
>> + - description: IPE non-protected stream
>> + - description: JPEG non-protected stream
>> + - description: OFE CDM non-protected stream
>> + - description: OFE non-protected stream
>> + - description: VFE / VFE Lite CDM non-protected stream
>> +
>> + power-domains:
>> + items:
>> + - description:
>> + VFE0 GDSC - Global Distributed Switch Controller for VFE0.
>> + - description:
>> + VFE1 GDSC - Global Distributed Switch Controller for VFE1.
>> + - description:
>> + VFE2 GDSC - Global Distributed Switch Controller for VFE2.
>> + - description:
>> + Titan GDSC - Global Distributed Switch Controller for the entire camss.
>> + - description:
>> + IPE GDSC - Global Distributed Switch Controller for IPE.
>> + - description:
>> + OFE GDSC - Block Global Distributed Switch Controller for OFE.
>> +
>> + power-domain-names:
>> + items:
>> + - const: vfe0
>> + - const: vfe1
>> + - const: vfe2
> Previous generations call these IFE, I already raised this and you
> changed to ife in Kaanapali. So are all future devices going to use
> rather VFE name?
Will change to 'ife'.
>
>> + - const: top
>> + - const: ipe
>> + - const: ofe
>> +
>> + vdd-csiphy0-0p88-supply:
> 88->8, so: vdd-csiphy0-0p8-supply:
>
> Same in other places. This is how it is called for every binding.
Ack
>> + description:
>> + Phandle to a 0.88V regulator supply to CSIPHY0 core block.
>> +
>> + vdd-csiphy0-1p2-supply:
>> + description:
>> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
>> +
>> + vdd-csiphy1-0p88-supply:
>> + description:
>> + Phandle to a 0.88V regulator supply to CSIPHY1 core block.
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750
2025-11-26 9:38 ` [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
2025-11-27 8:10 ` Krzysztof Kozlowski
@ 2025-11-27 9:46 ` Bryan O'Donoghue
1 sibling, 0 replies; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 9:46 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add the compatible string "qcom,sm8750-camss" to support the Camera
> Subsystem (CAMSS) on the Qualcomm SM8750 platform.
>
> The SM8750 platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE Lite
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSIPHY
> - 2 x ICP
> - 1 x IPE
> - 2 x JPEG DMA & Downscaler
> - 2 x JPEG Encoder
> - 1 x OFE
> - 5 x RT CDM
> - 3 x TPG
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../bindings/media/qcom,sm8750-camss.yaml | 664 +++++++++++++++++++++
> 1 file changed, 664 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> new file mode 100644
> index 000000000000..6b2b0b5a7e19
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-camss.yaml
> @@ -0,0 +1,664 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,sm8750-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8750 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> +
> +description:
> + This binding describes the camera subsystem hardware found on SM8750 Qualcomm
> + SoCs. It includes submodules such as CSIPHY (CSI Physical layer) and CSID
> + (CSI Decoder), which comply with the MIPI CSI2 protocol.
> +
> + The subsystem also integrates a set of real-time image processing engines and
> + their associated configuration modules, as well as non-real-time engines.
> +
> + Additionally, it encompasses a test pattern generator (TPG) submodule.
> +
> +properties:
> + compatible:
> + const: qcom,sm8750-camss
> +
> + reg:
> + items:
> + - description: Registers for CSID 0
> + - description: Registers for CSID 1
> + - description: Registers for CSID 2
> + - description: Registers for CSID Lite 0
> + - description: Registers for CSID Lite 1
> + - description: Registers for CSIPHY 0
> + - description: Registers for CSIPHY 1
> + - description: Registers for CSIPHY 2
> + - description: Registers for CSIPHY 3
> + - description: Registers for CSIPHY 4
> + - description: Registers for CSIPHY 5
> + - description: Registers for VFE (Video Front End) 0
> + - description: Registers for VFE 1
> + - description: Registers for VFE 2
> + - description: Registers for VFE Lite 0
> + - description: Registers for VFE Lite 1
> + - description: Registers for ICP (Imaging Control Processor) 0
> + - description: Registers for ICP SYS 0
> + - description: Registers for ICP 1
> + - description: Registers for ICP SYS 1
> + - description: Registers for IPE (Image Processing Engine)
> + - description: Registers for JPEG DMA & Downscaler 0
> + - description: Registers for JPEG Encoder 0
> + - description: Registers for JPEG DMA & Downscaler 1
> + - description: Registers for JPEG Encoder 1
> + - description: Registers for OFE (Offline Front End)
> + - description: Registers for RT CDM (Camera Data Mover) 0
> + - description: Registers for RT CDM 1
> + - description: Registers for RT CDM 2
> + - description: Registers for RT CDM 3
> + - description: Registers for RT CDM 4
> + - description: Registers for TPG 0
> + - description: Registers for TPG 1
> + - description: Registers for TPG 2
> +
> + reg-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: icp0
> + - const: icp0_sys
> + - const: icp1
> + - const: icp1_sys
> + - const: ipe
> + - const: jpeg_dma0
> + - const: jpeg_enc0
> + - const: jpeg_dma1
> + - const: jpeg_enc1
> + - const: ofe
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + clocks:
> + maxItems: 61
> +
> + clock-names:
> + items:
> + - const: camnoc_nrt_axi
> + - const: camnoc_rt_axi
> + - const: camnoc_rt_vfe0
> + - const: camnoc_rt_vfe1
> + - const: camnoc_rt_vfe2
> + - const: camnoc_rt_vfe_lite
> + - const: cam_top_ahb
> + - const: cam_top_fast_ahb
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy3
> + - const: csiphy3_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: csiphy5
> + - const: csiphy5_timer
> + - const: gcc_hf_axi
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe2
> + - const: vfe2_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> + - const: qdss_debug_xo
> + - const: camnoc_ipe_nps
> + - const: camnoc_ofe
> + - const: gcc_sf_axi
> + - const: icp0
> + - const: icp0_ahb
> + - const: icp1
> + - const: icp1_ahb
> + - const: ipe_nps
> + - const: ipe_nps_ahb
> + - const: ipe_nps_fast_ahb
> + - const: ipe_pps
> + - const: ipe_pps_fast_ahb
> + - const: jpeg0
> + - const: jpeg1
> + - const: ofe_ahb
> + - const: ofe_anchor
> + - const: ofe_anchor_fast_ahb
> + - const: ofe_hdr
> + - const: ofe_hdr_fast_ahb
> + - const: ofe_main
> + - const: ofe_main_fast_ahb
> + - const: vfe0_bayer
> + - const: vfe0_bayer_fast_ahb
> + - const: vfe1_bayer
> + - const: vfe1_bayer_fast_ahb
> + - const: vfe2_bayer
> + - const: vfe2_bayer_fast_ahb
> +
> + interrupts:
> + maxItems: 32
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy3
> + - const: csiphy4
> + - const: csiphy5
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: camnoc_nrt
> + - const: camnoc_rt
> + - const: icp0
> + - const: icp1
> + - const: jpeg_dma0
> + - const: jpeg_enc0
> + - const: jpeg_dma1
> + - const: jpeg_enc1
> + - const: rt_cdm0
> + - const: rt_cdm1
> + - const: rt_cdm2
> + - const: rt_cdm3
> + - const: rt_cdm4
> + - const: tpg0
> + - const: tpg1
> + - const: tpg2
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: ahb
> + - const: hf_mnoc
> + - const: sf_icp_mnoc
> + - const: sf_mnoc
> +
> + iommus:
> + items:
> + - description: VFE non-protected stream
> + - description: ICP0 shared stream
> + - description: ICP1 shared stream
> + - description: IPE CDM non-protected stream
> + - description: IPE non-protected stream
> + - description: JPEG non-protected stream
> + - description: OFE CDM non-protected stream
> + - description: OFE non-protected stream
> + - description: VFE / VFE Lite CDM non-protected stream
> +
> + power-domains:
> + items:
> + - description:
> + VFE0 GDSC - Global Distributed Switch Controller for VFE0.
> + - description:
> + VFE1 GDSC - Global Distributed Switch Controller for VFE1.
> + - description:
> + VFE2 GDSC - Global Distributed Switch Controller for VFE2.
> + - description:
> + Titan GDSC - Global Distributed Switch Controller for the entire camss.
> + - description:
> + IPE GDSC - Global Distributed Switch Controller for IPE.
> + - description:
> + OFE GDSC - Block Global Distributed Switch Controller for OFE.
> +
> + power-domain-names:
> + items:
> + - const: vfe0
> + - const: vfe1
> + - const: vfe2
> + - const: top
> + - const: ipe
> + - const: ofe
> +
> + vdd-csiphy0-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY0 core block.
> +
> + vdd-csiphy0-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY0 pll block.
> +
> + vdd-csiphy1-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY1 core block.
> +
> + vdd-csiphy1-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY1 pll block.
> +
> + vdd-csiphy2-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY2 core block.
> +
> + vdd-csiphy2-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY2 pll block.
> +
> + vdd-csiphy3-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY3 core block.
> +
> + vdd-csiphy3-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY3 pll block.
> +
> + vdd-csiphy4-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY4 core block.
> +
> + vdd-csiphy4-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY4 pll block.
> +
> + vdd-csiphy5-0p88-supply:
> + description:
> + Phandle to a 0.88V regulator supply to CSIPHY5 core block.
> +
> + vdd-csiphy5-1p2-supply:
> + description:
> + Phandle to a 1.2V regulator supply to CSIPHY5 pll block.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-5]$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description:
> + Input ports for receiving CSI data on CSIPHY 0-5.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - interrupts
> + - interrupt-names
> + - interconnects
> + - interconnect-names
> + - iommus
> + - power-domains
> + - power-domain-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interconnect/qcom,icc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + isp@ad27000 {
> + compatible = "qcom,sm8750-camss";
> +
> + reg = <0x0 0x0ad27000 0x0 0x2b00>,
> + <0x0 0x0ad2a000 0x0 0x2b00>,
> + <0x0 0x0ad2d000 0x0 0x2b00>,
> + <0x0 0x0ad6d000 0x0 0xa00>,
> + <0x0 0x0ad72000 0x0 0xa00>,
> + <0x0 0x0ada9000 0x0 0x2000>,
> + <0x0 0x0adab000 0x0 0x2000>,
> + <0x0 0x0adad000 0x0 0x2000>,
> + <0x0 0x0adaf000 0x0 0x2000>,
> + <0x0 0x0adb1000 0x0 0x2000>,
> + <0x0 0x0adb3000 0x0 0x2000>,
> + <0x0 0x0ac86000 0x0 0x10000>,
> + <0x0 0x0ac96000 0x0 0x10000>,
> + <0x0 0x0aca6000 0x0 0x10000>,
> + <0x0 0x0ad6e000 0x0 0x1800>,
> + <0x0 0x0ad73000 0x0 0x1800>,
> + <0x0 0x0ac06000 0x0 0x1000>,
> + <0x0 0x0ac05000 0x0 0x1000>,
> + <0x0 0x0ac16000 0x0 0x1000>,
> + <0x0 0x0ac15000 0x0 0x1000>,
> + <0x0 0x0ac42000 0x0 0x18000>,
> + <0x0 0x0ac26000 0x0 0x1000>,
> + <0x0 0x0ac25000 0x0 0x1000>,
> + <0x0 0x0ac28000 0x0 0x1000>,
> + <0x0 0x0ac27000 0x0 0x1000>,
> + <0x0 0x0ac2a000 0x0 0x18000>,
> + <0x0 0x0ac7f000 0x0 0x580>,
> + <0x0 0x0ac80000 0x0 0x580>,
> + <0x0 0x0ac81000 0x0 0x580>,
> + <0x0 0x0ac82000 0x0 0x580>,
> + <0x0 0x0ac83000 0x0 0x580>,
> + <0x0 0x0ad8b000 0x0 0x400>,
> + <0x0 0x0ad8c000 0x0 0x400>,
> + <0x0 0x0ad8d000 0x0 0x400>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "icp0",
> + "icp0_sys",
> + "icp1",
> + "icp1_sys",
> + "ipe",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "ofe",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + clocks = <&camcc_cam_cc_camnoc_nrt_axi_clk>,
> + <&camcc_cam_cc_camnoc_rt_axi_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_0_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_1_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_2_main_clk>,
> + <&camcc_cam_cc_camnoc_rt_vfe_lite_clk>,
> + <&camcc_cam_cc_cam_top_ahb_clk>,
> + <&camcc_cam_cc_cam_top_fast_ahb_clk>,
> + <&camcc_cam_cc_csid_clk>,
> + <&camcc_cam_cc_csid_csiphy_rx_clk>,
> + <&camcc_cam_cc_csiphy0_clk>,
> + <&camcc_cam_cc_csi0phytimer_clk>,
> + <&camcc_cam_cc_csiphy1_clk>,
> + <&camcc_cam_cc_csi1phytimer_clk>,
> + <&camcc_cam_cc_csiphy2_clk>,
> + <&camcc_cam_cc_csi2phytimer_clk>,
> + <&camcc_cam_cc_csiphy3_clk>,
> + <&camcc_cam_cc_csi3phytimer_clk>,
> + <&camcc_cam_cc_csiphy4_clk>,
> + <&camcc_cam_cc_csi4phytimer_clk>,
> + <&camcc_cam_cc_csiphy5_clk>,
> + <&camcc_cam_cc_csi5phytimer_clk>,
> + <&gcc_gcc_camera_hf_axi_clk>,
> + <&camcc_cam_cc_vfe_0_main_clk>,
> + <&camcc_cam_cc_vfe_0_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_1_main_clk>,
> + <&camcc_cam_cc_vfe_1_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_2_main_clk>,
> + <&camcc_cam_cc_vfe_2_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_lite_clk>,
> + <&camcc_cam_cc_vfe_lite_ahb_clk>,
> + <&camcc_cam_cc_vfe_lite_cphy_rx_clk>,
> + <&camcc_cam_cc_vfe_lite_csid_clk>,
> + <&camcc_cam_cc_qdss_debug_xo_clk>,
> + <&camcc_cam_cc_camnoc_nrt_ipe_nps_clk>,
> + <&camcc_cam_cc_camnoc_nrt_ofe_main_clk>,
> + <&gcc_gcc_camera_sf_axi_clk>,
> + <&camcc_cam_cc_icp_0_clk>,
> + <&camcc_cam_cc_icp_0_ahb_clk>,
> + <&camcc_cam_cc_icp_1_clk>,
> + <&camcc_cam_cc_icp_1_ahb_clk>,
> + <&camcc_cam_cc_ipe_nps_clk>,
> + <&camcc_cam_cc_ipe_nps_ahb_clk>,
> + <&camcc_cam_cc_ipe_nps_fast_ahb_clk>,
> + <&camcc_cam_cc_ipe_pps_clk>,
> + <&camcc_cam_cc_ipe_pps_fast_ahb_clk>,
> + <&camcc_cam_cc_jpeg_0_clk>,
> + <&camcc_cam_cc_jpeg_1_clk>,
> + <&camcc_cam_cc_ofe_ahb_clk>,
> + <&camcc_cam_cc_ofe_anchor_clk>,
> + <&camcc_cam_cc_ofe_anchor_fast_ahb_clk>,
> + <&camcc_cam_cc_ofe_hdr_clk>,
> + <&camcc_cam_cc_ofe_hdr_fast_ahb_clk>,
> + <&camcc_cam_cc_ofe_main_clk>,
> + <&camcc_cam_cc_ofe_main_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_0_bayer_clk>,
> + <&camcc_cam_cc_vfe_0_bayer_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_1_bayer_clk>,
> + <&camcc_cam_cc_vfe_1_bayer_fast_ahb_clk>,
> + <&camcc_cam_cc_vfe_2_bayer_clk>,
> + <&camcc_cam_cc_vfe_2_bayer_fast_ahb_clk>;
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "camnoc_rt_vfe0",
> + "camnoc_rt_vfe1",
> + "camnoc_rt_vfe2",
> + "camnoc_rt_vfe_lite",
> + "cam_top_ahb",
> + "cam_top_fast_ahb",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "gcc_hf_axi",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "qdss_debug_xo",
> + "camnoc_ipe_nps",
> + "camnoc_ofe",
> + "gcc_sf_axi",
> + "icp0",
> + "icp0_ahb",
> + "icp1",
> + "icp1_ahb",
> + "ipe_nps",
> + "ipe_nps_ahb",
> + "ipe_nps_fast_ahb",
> + "ipe_pps",
> + "ipe_pps_fast_ahb",
> + "jpeg0",
> + "jpeg1",
> + "ofe_ahb",
> + "ofe_anchor",
> + "ofe_anchor_fast_ahb",
> + "ofe_hdr",
> + "ofe_hdr_fast_ahb",
> + "ofe_main",
> + "ofe_main_fast_ahb",
> + "vfe0_bayer",
> + "vfe0_bayer_fast_ahb",
> + "vfe1_bayer",
> + "vfe1_bayer_fast_ahb",
> + "vfe2_bayer",
> + "vfe2_bayer_fast_ahb";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "camnoc_nrt",
> + "camnoc_rt",
> + "icp0",
> + "icp1",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + interconnects = <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc_slave_camera_cfg QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc_master_camnoc_hf QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc_master_camnoc_nrt_icp_sf QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc_master_camnoc_sf QCOM_ICC_TAG_ALWAYS
> + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_icp_mnoc",
> + "sf_mnoc";
> +
> + iommus = <&apps_smmu 0x1c00 0x00>,
> + <&apps_smmu 0x18c0 0x00>,
> + <&apps_smmu 0x1980 0x00>,
> + <&apps_smmu 0x1840 0x00>,
> + <&apps_smmu 0x1800 0x00>,
> + <&apps_smmu 0x18a0 0x00>,
> + <&apps_smmu 0x1880 0x00>,
> + <&apps_smmu 0x1820 0x00>,
> + <&apps_smmu 0x1860 0x00>;
> +
> + power-domains = <&camcc_cam_cc_vfe_0_gdsc>,
> + <&camcc_cam_cc_vfe_1_gdsc>,
> + <&camcc_cam_cc_vfe_2_gdsc>,
> + <&camcc_cam_cc_titan_top_gdsc>,
> + <&camcc_cam_cc_ipe_0_gdsc>,
> + <&camcc_cam_cc_ofe_gdsc>;
> + power-domain-names = "vfe0",
> + "vfe1",
> + "vfe2",
> + "top",
> + "ipe",
> + "ofe";
> +
> + vdd-csiphy0-0p88-supply = <&vreg_0p88_supply>;
> + vdd-csiphy0-1p2-supply = <&vreg_1p2_supply>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + csiphy_ep0: endpoint {
> + data-lanes = <0 1>;
> + remote-endpoint = <&sensor_ep>;
> + };
> + };
> + };
> + };
> + };
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
2025-11-26 9:38 ` [PATCH 1/7] dt-bindings: i2c: qcom-cci: Document SM8750 compatible Hangxiang Ma
2025-11-26 9:38 ` [PATCH 2/7] media: dt-bindings: Add CAMSS device for SM8750 Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 9:46 ` Bryan O'Donoghue
2025-11-26 9:38 ` [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Hangxiang Ma
` (3 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add support for SM8750 in the camss driver. Add high level resource
information along with the bus bandwidth votes. Module level detailed
resource information will be enumerated in the following patches of the
series.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 5ee43c8a9ae4..805e2fbd97dd 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -3870,6 +3870,20 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct resources_icc icc_res_sm8750[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 150000,
+ .icc_bw_tbl.peak = 300000,
+ },
+ /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 471860,
+ .icc_bw_tbl.peak = 925857,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
/* CSIPHY0 */
{
@@ -5283,6 +5297,13 @@ static const struct camss_resources sm8650_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm8650),
};
+static const struct camss_resources sm8750_resources = {
+ .version = CAMSS_8750,
+ .pd_name = "top",
+ .icc_res = icc_res_sm8750,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
+};
+
static const struct camss_resources x1e80100_resources = {
.version = CAMSS_X1E80100,
.pd_name = "top",
@@ -5314,6 +5335,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
+ { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources },
{ .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
{ }
};
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index b1cc4825f027..f87b615ad1a9 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -91,6 +91,7 @@ enum camss_version {
CAMSS_845,
CAMSS_8550,
CAMSS_8650,
+ CAMSS_8750,
CAMSS_8775P,
CAMSS_KAANAPALI,
CAMSS_X1E80100,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver
2025-11-26 9:38 ` [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver Hangxiang Ma
@ 2025-11-27 9:46 ` Bryan O'Donoghue
0 siblings, 0 replies; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 9:46 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add support for SM8750 in the camss driver. Add high level resource
> information along with the bus bandwidth votes. Module level detailed
> resource information will be enumerated in the following patches of the
> series.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/camss.c | 22 ++++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss.h | 1 +
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 5ee43c8a9ae4..805e2fbd97dd 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -3870,6 +3870,20 @@ static const struct resources_icc icc_res_sa8775p[] = {
> },
> };
>
> +static const struct resources_icc icc_res_sm8750[] = {
> + {
> + .name = "ahb",
> + .icc_bw_tbl.avg = 150000,
> + .icc_bw_tbl.peak = 300000,
> + },
> + /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */
> + {
> + .name = "hf_mnoc",
> + .icc_bw_tbl.avg = 471860,
> + .icc_bw_tbl.peak = 925857,
> + },
> +};
> +
> static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
> /* CSIPHY0 */
> {
> @@ -5283,6 +5297,13 @@ static const struct camss_resources sm8650_resources = {
> .vfe_num = ARRAY_SIZE(vfe_res_sm8650),
> };
>
> +static const struct camss_resources sm8750_resources = {
> + .version = CAMSS_8750,
> + .pd_name = "top",
> + .icc_res = icc_res_sm8750,
> + .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
> +};
> +
> static const struct camss_resources x1e80100_resources = {
> .version = CAMSS_X1E80100,
> .pd_name = "top",
> @@ -5314,6 +5335,7 @@ static const struct of_device_id camss_dt_match[] = {
> { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
> { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
> { .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
> + { .compatible = "qcom,sm8750-camss", .data = &sm8750_resources },
> { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
> { }
> };
> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
> index b1cc4825f027..f87b615ad1a9 100644
> --- a/drivers/media/platform/qcom/camss/camss.h
> +++ b/drivers/media/platform/qcom/camss/camss.h
> @@ -91,6 +91,7 @@ enum camss_version {
> CAMSS_845,
> CAMSS_8550,
> CAMSS_8650,
> + CAMSS_8750,
> CAMSS_8775P,
> CAMSS_KAANAPALI,
> CAMSS_X1E80100,
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (2 preceding siblings ...)
2025-11-26 9:38 ` [PATCH 3/7] media: qcom: camss: Add SM8750 compatible camss driver Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 8:14 ` Krzysztof Kozlowski
2025-11-26 9:38 ` [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980 Hangxiang Ma
` (2 subsequent siblings)
6 siblings, 1 reply; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add more detailed resource information for CSIPHY devices in the camss
driver along with the support for v2.3.0 in the 2 phase CSIPHY driver
that is responsible for the PHY lane register configuration, module
reset and interrupt handling.
Additionally, generalize the struct name for the lane configuration that
had been added for Kaanapali and use it for SM8750 as well as they share
the settings.
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 11 ++-
drivers/media/platform/qcom/camss/camss.c | 107 +++++++++++++++++++++
2 files changed, 114 insertions(+), 4 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index f9db7e195dfe..157e946f67db 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -684,9 +684,9 @@ csiphy_lane_regs lane_regs_sm8650[] = {
{0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
};
-/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
+/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */
static const struct
-csiphy_lane_regs lane_regs_kaanapali[] = {
+csiphy_lane_regs lane_regs_v_2_3[] = {
/* LN 0 */
{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -1134,6 +1134,7 @@ static bool csiphy_is_gen2(u32 version)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
@@ -1250,9 +1251,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_sa8775p[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
break;
+ case CAMSS_8750:
case CAMSS_KAANAPALI:
- regs->lane_regs = &lane_regs_kaanapali[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali);
+ /* CSPHY v2.4.0 is backward compatible with v2.3.0 settings */
+ regs->lane_regs = &lane_regs_v_2_3[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_v_2_3);
regs->offset = 0x1000;
regs->common_status_offset = 0x138;
break;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 805e2fbd97dd..bfc942635682 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -3870,6 +3870,111 @@ static const struct resources_icc icc_res_sa8775p[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_8750[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = { "vdd-csiphy0-0p88", "vdd-csiphy0-1p2" },
+ .clock = { "csiphy0", "csiphy0_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = { "vdd-csiphy1-0p88", "vdd-csiphy1-1p2" },
+ .clock = { "csiphy1", "csiphy1_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = { "vdd-csiphy2-0p88", "vdd-csiphy2-1p2" },
+ .clock = { "csiphy2", "csiphy2_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = { "vdd-csiphy3-0p88", "vdd-csiphy3-1p2" },
+ .clock = { "csiphy3", "csiphy3_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY4 */
+ {
+ .regulators = { "vdd-csiphy4-0p88", "vdd-csiphy4-1p2" },
+ .clock = { "csiphy4", "csiphy4_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy4" },
+ .interrupt = { "csiphy4" },
+ .csiphy = {
+ .id = 4,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY5 */
+ {
+ .regulators = { "vdd-csiphy5-0p88", "vdd-csiphy5-1p2" },
+ .clock = { "csiphy5", "csiphy5_timer",
+ "cam_top_ahb", "cam_top_fast_ahb" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "csiphy5" },
+ .interrupt = { "csiphy5" },
+ .csiphy = {
+ .id = 5,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -5300,7 +5405,9 @@ static const struct camss_resources sm8650_resources = {
static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
+ .csiphy_res = csiphy_res_8750,
.icc_res = icc_res_sm8750,
+ .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY
2025-11-26 9:38 ` [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Hangxiang Ma
@ 2025-11-27 8:14 ` Krzysztof Kozlowski
2026-01-06 18:05 ` Vijay Kumar Tumati
0 siblings, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-27 8:14 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On Wed, Nov 26, 2025 at 01:38:37AM -0800, Hangxiang Ma wrote:
> Add more detailed resource information for CSIPHY devices in the camss
> driver along with the support for v2.3.0 in the 2 phase CSIPHY driver
> that is responsible for the PHY lane register configuration, module
> reset and interrupt handling.
>
> Additionally, generalize the struct name for the lane configuration that
> had been added for Kaanapali and use it for SM8750 as well as they share
> the settings.
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 11 ++-
> drivers/media/platform/qcom/camss/camss.c | 107 +++++++++++++++++++++
> 2 files changed, 114 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index f9db7e195dfe..157e946f67db 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -684,9 +684,9 @@ csiphy_lane_regs lane_regs_sm8650[] = {
> {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
> };
>
> -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
> +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */
> static const struct
> -csiphy_lane_regs lane_regs_kaanapali[] = {
There is no such line in next. Your cover letter does not explain
dependencies.
> +csiphy_lane_regs lane_regs_v_2_3[] = {
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY
2025-11-27 8:14 ` Krzysztof Kozlowski
@ 2026-01-06 18:05 ` Vijay Kumar Tumati
0 siblings, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 11/27/2025 12:14 AM, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 01:38:37AM -0800, Hangxiang Ma wrote:
>> Add more detailed resource information for CSIPHY devices in the camss
>> driver along with the support for v2.3.0 in the 2 phase CSIPHY driver
>> that is responsible for the PHY lane register configuration, module
>> reset and interrupt handling.
>>
>> Additionally, generalize the struct name for the lane configuration that
>> had been added for Kaanapali and use it for SM8750 as well as they share
>> the settings.
>>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 11 ++-
>> drivers/media/platform/qcom/camss/camss.c | 107 +++++++++++++++++++++
>> 2 files changed, 114 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index f9db7e195dfe..157e946f67db 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -684,9 +684,9 @@ csiphy_lane_regs lane_regs_sm8650[] = {
>> {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>> };
>>
>> -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */
>> +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */
>> static const struct
>> -csiphy_lane_regs lane_regs_kaanapali[] = {
> There is no such line in next. Your cover letter does not explain
> dependencies.
Will do. Thanks.
>
>> +csiphy_lane_regs lane_regs_v_2_3[] = {
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (3 preceding siblings ...)
2025-11-26 9:38 ` [PATCH 4/7] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 10:01 ` Bryan O'Donoghue
2025-11-26 9:38 ` [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4 Hangxiang Ma
2025-11-26 9:38 ` [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss Hangxiang Ma
6 siblings, 1 reply; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma,
Atiya Kailany
Add more detailed resource information for CSID devices along with the
driver for CSID 980 that is responsible for CSID register
configuration, module reset and IRQ handling for BUF_DONE events.
In SM8750, RUP and AUP updates for the CSID Full modules are split into
two registers along with a SET register. However, CSID Lite modules
still use a single register to update RUP and AUP without the additional
SET register. Handled the difference in the driver.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 1 +
drivers/media/platform/qcom/camss/camss-csid-980.c | 428 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss.c | 80 ++++
4 files changed, 510 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index a0abbca2b83d..74e12ec65427 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -8,6 +8,7 @@ qcom-camss-objs += \
camss-csid-4-7.o \
camss-csid-340.o \
camss-csid-680.o \
+ camss-csid-980.o \
camss-csid-1080.o \
camss-csid-gen2.o \
camss-csid-gen3.o \
diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
new file mode 100644
index 000000000000..0656a912505a
--- /dev/null
+++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * camss-csid-980.c
+ *
+ * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include "camss.h"
+#include "camss-csid.h"
+#include "camss-csid-gen3.h"
+
+/* Reset and Command Registers */
+#define CSID_RST_CFG 0xC
+#define RST_MODE BIT(0)
+#define RST_LOCATION BIT(4)
+
+/* Reset and Command Registers */
+#define CSID_RST_CMD 0x10
+#define SELECT_HW_RST BIT(0)
+#define SELECT_IRQ_RST BIT(2)
+#define CSID_IRQ_CMD 0x14
+#define IRQ_CMD_CLEAR BIT(0)
+
+/* Register Update Commands, RUP/AUP */
+#define CSID_RUP_CMD 0x18
+#define CSID_AUP_CMD 0x1C
+#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
+#define CSID_RUP_AUP_CMD 0x20
+#define RUP_SET BIT(0)
+#define MUP BIT(4)
+
+#define CSID_LITE_RUP_AUP_CMD 0x18
+#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
+#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
+
+/* Top level interrupt registers */
+#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84)
+#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
+#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C)
+#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
+#define INFO_RST_DONE BIT(0)
+#define CSI2_RX_IRQ_STATUS BIT(2)
+#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
+
+/* Buffer done interrupt registers */
+#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4)
+#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16)
+#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8)
+#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC)
+#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0)
+
+/* CSI2 RX interrupt registers */
+#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4)
+#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8)
+#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC)
+#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0)
+
+/* CSI2 RX Configuration */
+#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400)
+#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
+#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
+#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
+#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
+#define CSI2_RX_CFG1_VC_MODE BIT(2)
+
+#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5)
+
+#define CSID_RDI_CFG0(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
+ 0xE00 + 0x200 * _rdi; \
+ })
+#define RDI_CFG0_RETIME_BS BIT(5)
+#define RDI_CFG0_TIMESTAMP_EN BIT(6)
+#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
+#define RDI_CFG0_DECODE_FORMAT 12
+#define RDI_CFG0_DT 16
+#define RDI_CFG0_VC 22
+#define RDI_CFG0_DT_ID 27
+#define RDI_CFG0_EN BIT(31)
+
+/* RDI Control and Configuration */
+#define CSID_RDI_CTRL(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
+ 0xE04 + 0x200 * _rdi; \
+ })
+#define RDI_CTRL_START_CMD BIT(0)
+
+#define CSID_RDI_CFG1(rdi) \
+ ({ \
+ __typeof__(rdi) _rdi = (rdi); \
+ csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
+ 0xE10 + 0x200 * _rdi; \
+ })
+#define RDI_CFG1_DROP_H_EN BIT(5)
+#define RDI_CFG1_DROP_V_EN BIT(6)
+#define RDI_CFG1_CROP_H_EN BIT(7)
+#define RDI_CFG1_CROP_V_EN BIT(8)
+#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
+
+/* RDI Pixel Store Configuration */
+#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
+#define RDI_PIX_STORE_CFG0_EN BIT(0)
+#define RDI_PIX_STORE_CFG0_MIN_HBI 1
+
+/* RDI IRQ Status in wrapper */
+#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
+ (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi))
+#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
+ (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi))
+#define INFO_RUP_DONE BIT(23)
+
+static void __csid_full_aup_rup_trigger(struct csid_device *csid)
+{
+ /* trigger SET in combined register */
+ writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
+}
+
+static void __csid_aup_update(struct csid_device *csid, int port_id)
+{
+ if (!csid_is_lite(csid)) {
+ csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->aup_update, csid->base + CSID_AUP_CMD);
+
+ __csid_full_aup_rup_trigger(csid);
+ } else {
+ csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ }
+}
+
+static void __csid_rup_update(struct csid_device *csid, int port_id)
+{
+ if (!csid_is_lite(csid)) {
+ csid->rup_update |= CSID_RUP_AUP_RDI(port_id);
+ writel(csid->rup_update, csid->base + CSID_RUP_CMD);
+
+ __csid_full_aup_rup_trigger(csid);
+ } else {
+ csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
+ writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
+ }
+}
+
+static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
+{
+ /* Hardware clears the registers upon consuming the settings */
+ if (csid_is_lite(csid)) {
+ csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
+ csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
+ } else {
+ csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
+ csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id);
+ }
+}
+
+static void __csid_configure_rx(struct csid_device *csid,
+ struct csid_phy_config *phy)
+{
+ int val;
+
+ val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
+ val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
+ << CSI2_RX_CFG0_PHY_NUM_SEL;
+ writel(val, csid->base + CSID_CSI2_RX_CFG0);
+
+ val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+}
+
+static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
+{
+ int val;
+
+ if (vc > 3) {
+ val = readl(csid->base + CSID_CSI2_RX_CFG1);
+ val |= CSI2_RX_CFG1_VC_MODE;
+ writel(val, csid->base + CSID_CSI2_RX_CFG1);
+ }
+}
+
+static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
+{
+ int val = 0;
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
+
+ if (enable)
+ val = RDI_CTRL_START_CMD;
+
+ writel(val, csid->base + rdi_ctrl_offset);
+}
+
+static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
+{
+ u32 val;
+
+ /* Configure pixel store to allow absorption of hblanking or idle time.
+ * This helps with horizontal crop and prevents line buffer conflicts.
+ * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
+ * and just enable the pixel store functionality.
+ */
+ val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
+ writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
+}
+
+static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
+{
+ u32 val;
+ u8 lane_cnt = csid->phy.lane_cnt;
+
+ /* Source pads matching RDI channels on hardware.
+ * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
+ */
+ struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
+ const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
+ csid->res->formats->nformats,
+ input_format->code);
+
+ if (!lane_cnt)
+ lane_cnt = 4;
+
+ /*
+ * DT_ID is a two bit bitfield that is concatenated with
+ * the four least significant bits of the five bit VC
+ * bitfield to generate an internal CID value.
+ *
+ * CSID_RDI_CFG0(vc)
+ * DT_ID : 28:27
+ * VC : 26:22
+ * DT : 21:16
+ *
+ * CID : VC 3:0 << 2 | DT_ID 1:0
+ */
+ u8 dt_id = vc & 0x03;
+ u32 rdi_cfg0_offset = CSID_RDI_CFG0(vc);
+ u32 rdi_cfg1_offset = CSID_RDI_CFG1(vc);
+ u32 rdi_ctrl_offset = CSID_RDI_CTRL(vc);
+
+ val = RDI_CFG0_TIMESTAMP_EN;
+ val |= RDI_CFG0_TIMESTAMP_STB_SEL;
+ val |= RDI_CFG0_RETIME_BS;
+
+ /* note: for non-RDI path, this should be format->decode_format */
+ val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
+ val |= vc << RDI_CFG0_VC;
+ val |= format->data_type << RDI_CFG0_DT;
+ val |= dt_id << RDI_CFG0_DT_ID;
+ writel(val, csid->base + rdi_cfg0_offset);
+
+ val = RDI_CFG1_PACKING_FORMAT_MIPI;
+ writel(val, csid->base + rdi_cfg1_offset);
+
+ /* Configure pixel store using dedicated register in 980 */
+ if (!csid_is_lite(csid))
+ __csid_configure_rdi_pix_store(csid, vc);
+
+ val = 0;
+ writel(val, csid->base + rdi_ctrl_offset);
+
+ val = readl(csid->base + rdi_cfg0_offset);
+
+ if (enable)
+ val |= RDI_CFG0_EN;
+
+ writel(val, csid->base + rdi_cfg0_offset);
+}
+
+static void csid_configure_stream_980(struct csid_device *csid, u8 enable)
+{
+ u8 vc, i;
+
+ __csid_configure_rx(csid, &csid->phy);
+
+ for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_980; vc++) {
+ if (csid->phy.en_vc & BIT(vc)) {
+ __csid_configure_rdi_stream(csid, enable, vc);
+ __csid_configure_rx_vc(csid, vc);
+
+ for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
+ __csid_aup_update(csid, vc);
+ __csid_rup_update(csid, vc);
+ }
+
+ __csid_ctrl_rdi(csid, enable, vc);
+ }
+ }
+}
+
+static int csid_configure_testgen_pattern_980(struct csid_device *csid,
+ s32 val)
+{
+ return 0;
+}
+
+static void csid_subdev_reg_update_980(struct csid_device *csid, int port_id,
+ bool clear)
+{
+ if (clear)
+ __csid_aup_rup_clear(csid, port_id);
+ else
+ __csid_aup_update(csid, port_id);
+}
+
+/**
+ * csid_isr - CSID module interrupt service routine
+ * @irq: Interrupt line
+ * @dev: CSID device
+ *
+ * Return IRQ_HANDLED on success
+ */
+static irqreturn_t csid_isr_980(int irq, void *dev)
+{
+ struct csid_device *csid = dev;
+ u32 val, buf_done_val;
+ u8 reset_done;
+ int i;
+
+ val = readl(csid->base + CSID_TOP_IRQ_STATUS);
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+
+ reset_done = val & INFO_RST_DONE;
+
+ buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
+ writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
+ writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
+
+ if (val & INFO_RUP_DONE)
+ csid_subdev_reg_update_980(csid, i, true);
+
+ if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
+ camss_buf_done(csid->camss, csid->id, i);
+ }
+ }
+
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ if (reset_done)
+ complete(&csid->reset_complete);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * csid_reset - Trigger reset on CSID module and wait to complete
+ * @csid: CSID device
+ *
+ * Return 0 on success or a negative error code otherwise
+ */
+static int csid_reset_980(struct csid_device *csid)
+{
+ unsigned long time;
+ u32 val;
+ int i;
+
+ reinit_completion(&csid->reset_complete);
+
+ val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
+ writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
+ writel(val, csid->base + CSID_TOP_IRQ_MASK);
+
+ val = 0;
+ for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
+ if (csid->phy.en_vc & BIT(i)) {
+ /*
+ * Only need to clear buf done IRQ status here,
+ * RUP done IRQ status will be cleared once isr
+ * strobe generated by CSID_RST_CMD
+ */
+ val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
+ }
+ }
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
+ writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
+
+ /* Clear all IRQ status with CLEAR bits set */
+ val = IRQ_CMD_CLEAR;
+ writel(val, csid->base + CSID_IRQ_CMD);
+
+ val = RST_LOCATION | RST_MODE;
+ writel(val, csid->base + CSID_RST_CFG);
+
+ val = SELECT_HW_RST | SELECT_IRQ_RST;
+ writel(val, csid->base + CSID_RST_CMD);
+
+ time = wait_for_completion_timeout(&csid->reset_complete,
+ msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
+
+ if (!time) {
+ dev_err(csid->camss->dev, "CSID reset timeout\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static void csid_subdev_init_980(struct csid_device *csid)
+{
+ csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
+}
+
+const struct csid_hw_ops csid_ops_980 = {
+ .configure_stream = csid_configure_stream_980,
+ .configure_testgen_pattern = csid_configure_testgen_pattern_980,
+ .hw_version = csid_hw_version,
+ .isr = csid_isr_980,
+ .reset = csid_reset_980,
+ .src_pad_code = csid_src_pad_code,
+ .subdev_init = csid_subdev_init_980,
+ .reg_update = csid_subdev_reg_update_980,
+};
+
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 6c214b487003..c77c61ab9c3a 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -223,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
extern const struct csid_hw_ops csid_ops_4_7;
extern const struct csid_hw_ops csid_ops_340;
extern const struct csid_hw_ops csid_ops_680;
+extern const struct csid_hw_ops csid_ops_980;
extern const struct csid_hw_ops csid_ops_1080;
extern const struct csid_hw_ops csid_ops_gen2;
extern const struct csid_hw_ops csid_ops_gen3;
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index bfc942635682..9dea343c1ac5 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -3975,6 +3975,84 @@ static const struct camss_subdev_resources csiphy_res_8750[] = {
},
};
+static const struct camss_subdev_resources csid_res_8750[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "csid", "csid_csiphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .is_lite = false,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite0" },
+ .interrupt = { "csid_lite0" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
+ .clock_rate = { { 400000000, 480000000 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite1" },
+ .interrupt = { "csid_lite1" },
+ .csid = {
+ .is_lite = true,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .hw_ops = &csid_ops_980,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -5406,8 +5484,10 @@ static const struct camss_resources sm8750_resources = {
.version = CAMSS_8750,
.pd_name = "top",
.csiphy_res = csiphy_res_8750,
+ .csid_res = csid_res_8750,
.icc_res = icc_res_sm8750,
.csiphy_num = ARRAY_SIZE(csiphy_res_8750),
+ .csid_num = ARRAY_SIZE(csid_res_8750),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980
2025-11-26 9:38 ` [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980 Hangxiang Ma
@ 2025-11-27 10:01 ` Bryan O'Donoghue
2026-01-06 18:07 ` Vijay Kumar Tumati
0 siblings, 1 reply; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 10:01 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Atiya Kailany
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add more detailed resource information for CSID devices along with the
> driver for CSID 980 that is responsible for CSID register
> configuration, module reset and IRQ handling for BUF_DONE events.
>
> In SM8750, RUP and AUP updates for the CSID Full modules are split into
> two registers along with a SET register. However, CSID Lite modules
> still use a single register to update RUP and AUP without the additional
> SET register. Handled the difference in the driver.
>
> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 1 +
> drivers/media/platform/qcom/camss/camss-csid-980.c | 428 +++++++++++++++++++++
> drivers/media/platform/qcom/camss/camss-csid.h | 1 +
> drivers/media/platform/qcom/camss/camss.c | 80 ++++
> 4 files changed, 510 insertions(+)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index a0abbca2b83d..74e12ec65427 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -8,6 +8,7 @@ qcom-camss-objs += \
> camss-csid-4-7.o \
> camss-csid-340.o \
> camss-csid-680.o \
> + camss-csid-980.o \
> camss-csid-1080.o \
> camss-csid-gen2.o \
> camss-csid-gen3.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/media/platform/qcom/camss/camss-csid-980.c
> new file mode 100644
> index 000000000000..0656a912505a
> --- /dev/null
> +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
> @@ -0,0 +1,428 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * camss-csid-980.c
> + *
> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include "camss.h"
> +#include "camss-csid.h"
> +#include "camss-csid-gen3.h"
> +
> +/* Reset and Command Registers */
> +#define CSID_RST_CFG 0xC
> +#define RST_MODE BIT(0)
> +#define RST_LOCATION BIT(4)
> +
> +/* Reset and Command Registers */
> +#define CSID_RST_CMD 0x10
> +#define SELECT_HW_RST BIT(0)
> +#define SELECT_IRQ_RST BIT(2)
> +#define CSID_IRQ_CMD 0x14
> +#define IRQ_CMD_CLEAR BIT(0)
> +
> +/* Register Update Commands, RUP/AUP */
> +#define CSID_RUP_CMD 0x18
> +#define CSID_AUP_CMD 0x1C
> +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
> +#define CSID_RUP_AUP_CMD 0x20
> +#define RUP_SET BIT(0)
> +#define MUP BIT(4)
> +
> +#define CSID_LITE_RUP_AUP_CMD 0x18
> +#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
> +#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
> +
> +/* Top level interrupt registers */
> +#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84)
> +#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
> +#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C)
> +#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
> +#define INFO_RST_DONE BIT(0)
> +#define CSI2_RX_IRQ_STATUS BIT(2)
> +#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
> +
> +/* Buffer done interrupt registers */
> +#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4)
> +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16)
> +#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8)
> +#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC)
> +#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0)
> +
> +/* CSI2 RX interrupt registers */
> +#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4)
> +#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8)
> +#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC)
> +#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0)
> +
> +/* CSI2 RX Configuration */
> +#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400)
> +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
> +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
> +#define CSI2_RX_CFG0_PHY_NUM_SEL 20
> +#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404)
> +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
> +#define CSI2_RX_CFG1_VC_MODE BIT(2)
> +
> +#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5)
> +
> +#define CSID_RDI_CFG0(rdi) \
> + ({ \
> + __typeof__(rdi) _rdi = (rdi); \
> + csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
> + 0xE00 + 0x200 * _rdi; \
> + })
> +#define RDI_CFG0_RETIME_BS BIT(5)
> +#define RDI_CFG0_TIMESTAMP_EN BIT(6)
> +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
> +#define RDI_CFG0_DECODE_FORMAT 12
> +#define RDI_CFG0_DT 16
> +#define RDI_CFG0_VC 22
> +#define RDI_CFG0_DT_ID 27
> +#define RDI_CFG0_EN BIT(31)
> +
> +/* RDI Control and Configuration */
> +#define CSID_RDI_CTRL(rdi) \
> + ({ \
> + __typeof__(rdi) _rdi = (rdi); \
> + csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
> + 0xE04 + 0x200 * _rdi; \
> + })
> +#define RDI_CTRL_START_CMD BIT(0)
> +
> +#define CSID_RDI_CFG1(rdi) \
> + ({ \
> + __typeof__(rdi) _rdi = (rdi); \
> + csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
> + 0xE10 + 0x200 * _rdi; \
> + })
> +#define RDI_CFG1_DROP_H_EN BIT(5)
> +#define RDI_CFG1_DROP_V_EN BIT(6)
> +#define RDI_CFG1_CROP_H_EN BIT(7)
> +#define RDI_CFG1_CROP_V_EN BIT(8)
> +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
> +
> +/* RDI Pixel Store Configuration */
> +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
> +#define RDI_PIX_STORE_CFG0_EN BIT(0)
> +#define RDI_PIX_STORE_CFG0_MIN_HBI 1
> +
> +/* RDI IRQ Status in wrapper */
> +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
> + (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi))
> +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
> + (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi))
> +#define INFO_RUP_DONE BIT(23)
> +
> +static void __csid_full_aup_rup_trigger(struct csid_device *csid)
> +{
> + /* trigger SET in combined register */
> + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
> +}
> +
> +static void __csid_aup_update(struct csid_device *csid, int port_id)
> +{
> + if (!csid_is_lite(csid)) {
> + csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
> + writel(csid->aup_update, csid->base + CSID_AUP_CMD);
> +
> + __csid_full_aup_rup_trigger(csid);
> + } else {
> + csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
> + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
> + }
This is backwards logic
if (csid_is_lite()) {
/* do stuff */
} else {
/* do other stuff */
}
Please add a comment to the code to explain why
__csid_full_aup_rup_trigger is omitted in one case.
> +}
> +
> +static void __csid_rup_update(struct csid_device *csid, int port_id)
> +{
> + if (!csid_is_lite(csid)) {
> + csid->rup_update |= CSID_RUP_AUP_RDI(port_id);
> + writel(csid->rup_update, csid->base + CSID_RUP_CMD);
> +
> + __csid_full_aup_rup_trigger(csid);
> + } else {
> + csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
> + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
> + }
> +}
> +
> +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
> +{
> + /* Hardware clears the registers upon consuming the settings */
> + if (csid_is_lite(csid)) {
> + csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
> + csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
> + } else {
> + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
> + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id);
> + }
> +}
Please be consistent with if (csid_is_lite())
> +
> +static void __csid_configure_rx(struct csid_device *csid,
> + struct csid_phy_config *phy)
> +{
> + int val;
> +
> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
> + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
> + << CSI2_RX_CFG0_PHY_NUM_SEL;
> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
> +
> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> +}
> +
> +static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
> +{
> + int val;
> +
> + if (vc > 3) {
> + val = readl(csid->base + CSID_CSI2_RX_CFG1);
> + val |= CSI2_RX_CFG1_VC_MODE;
> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
> + }
> +}
> +
> +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi)
> +{
> + int val = 0;
> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
> +
> + if (enable)
> + val = RDI_CTRL_START_CMD;
> +
> + writel(val, csid->base + rdi_ctrl_offset);
> +}
> +
> +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi)
> +{
> + u32 val;
> +
> + /* Configure pixel store to allow absorption of hblanking or idle time.
> + * This helps with horizontal crop and prevents line buffer conflicts.
> + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI
> + * and just enable the pixel store functionality.
> + */
> + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
> + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
> +}
> +
> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 vc)
> +{
> + u32 val;
> + u8 lane_cnt = csid->phy.lane_cnt;
> +
> + /* Source pads matching RDI channels on hardware.
> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
> + */
> + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
> + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats,
> + csid->res->formats->nformats,
> + input_format->code);
> +
> + if (!lane_cnt)
> + lane_cnt = 4;
> +
> + /*
> + * DT_ID is a two bit bitfield that is concatenated with
> + * the four least significant bits of the five bit VC
> + * bitfield to generate an internal CID value.
> + *
> + * CSID_RDI_CFG0(vc)
> + * DT_ID : 28:27
> + * VC : 26:22
> + * DT : 21:16
> + *
> + * CID : VC 3:0 << 2 | DT_ID 1:0
> + */
> + u8 dt_id = vc & 0x03;
> + u32 rdi_cfg0_offset = CSID_RDI_CFG0(vc);
> + u32 rdi_cfg1_offset = CSID_RDI_CFG1(vc);
> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(vc);
> +
> + val = RDI_CFG0_TIMESTAMP_EN;
> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
> + val |= RDI_CFG0_RETIME_BS;
> +
> + /* note: for non-RDI path, this should be format->decode_format */
> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
> + val |= vc << RDI_CFG0_VC;
> + val |= format->data_type << RDI_CFG0_DT;
> + val |= dt_id << RDI_CFG0_DT_ID;
> + writel(val, csid->base + rdi_cfg0_offset);
> +
> + val = RDI_CFG1_PACKING_FORMAT_MIPI;
> + writel(val, csid->base + rdi_cfg1_offset);
> +
> + /* Configure pixel store using dedicated register in 980 */
> + if (!csid_is_lite(csid))
> + __csid_configure_rdi_pix_store(csid, vc);
> +
> + val = 0;
> + writel(val, csid->base + rdi_ctrl_offset);
> +
> + val = readl(csid->base + rdi_cfg0_offset);
> +
> + if (enable)
> + val |= RDI_CFG0_EN;
> +
> + writel(val, csid->base + rdi_cfg0_offset);
> +}
> +
> +static void csid_configure_stream_980(struct csid_device *csid, u8 enable)
> +{
> + u8 vc, i;
> +
> + __csid_configure_rx(csid, &csid->phy);
> +
> + for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_980; vc++) {
> + if (csid->phy.en_vc & BIT(vc)) {
> + __csid_configure_rdi_stream(csid, enable, vc);
> + __csid_configure_rx_vc(csid, vc);
> +
> + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
> + __csid_aup_update(csid, vc);
> + __csid_rup_update(csid, vc);
> + }
> +
> + __csid_ctrl_rdi(csid, enable, vc);
> + }
> + }
> +}
> +
> +static int csid_configure_testgen_pattern_980(struct csid_device *csid,
> + s32 val)
> +{
> + return 0;
> +}
> +
> +static void csid_subdev_reg_update_980(struct csid_device *csid, int port_id,
> + bool clear)
> +{
> + if (clear)
> + __csid_aup_rup_clear(csid, port_id);
> + else
> + __csid_aup_update(csid, port_id);
> +}
> +
> +/**
> + * csid_isr - CSID module interrupt service routine
> + * @irq: Interrupt line
> + * @dev: CSID device
> + *
> + * Return IRQ_HANDLED on success
> + */
> +static irqreturn_t csid_isr_980(int irq, void *dev)
> +{
> + struct csid_device *csid = dev;
> + u32 val, buf_done_val;
> + u8 reset_done;
> + int i;
> +
> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> +
> + reset_done = val & INFO_RST_DONE;
> +
> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> +
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
> + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
> +
> + if (val & INFO_RUP_DONE)
> + csid_subdev_reg_update_980(csid, i, true);
> +
> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
> + camss_buf_done(csid->camss, csid->id, i);
> + }
> + }
> +
> + val = IRQ_CMD_CLEAR;
> + writel(val, csid->base + CSID_IRQ_CMD);
> +
> + if (reset_done)
> + complete(&csid->reset_complete);
> +
> + return IRQ_HANDLED;
> +}
> +
> +/**
> + * csid_reset - Trigger reset on CSID module and wait to complete
> + * @csid: CSID device
> + *
> + * Return 0 on success or a negative error code otherwise
> + */
> +static int csid_reset_980(struct csid_device *csid)
> +{
> + unsigned long time;
> + u32 val;
> + int i;
> +
> + reinit_completion(&csid->reset_complete);
> +
> + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
> + writel(val, csid->base + CSID_TOP_IRQ_MASK);
> +
> + val = 0;
> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
> + if (csid->phy.en_vc & BIT(i)) {
> + /*
> + * Only need to clear buf done IRQ status here,
> + * RUP done IRQ status will be cleared once isr
> + * strobe generated by CSID_RST_CMD
> + */
> + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
> + }
> + }
> + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
> + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
> +
> + /* Clear all IRQ status with CLEAR bits set */
> + val = IRQ_CMD_CLEAR;
> + writel(val, csid->base + CSID_IRQ_CMD);
> +
> + val = RST_LOCATION | RST_MODE;
> + writel(val, csid->base + CSID_RST_CFG);
> +
> + val = SELECT_HW_RST | SELECT_IRQ_RST;
> + writel(val, csid->base + CSID_RST_CMD);
> +
> + time = wait_for_completion_timeout(&csid->reset_complete,
> + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
> +
> + if (!time) {
> + dev_err(csid->camss->dev, "CSID reset timeout\n");
> + return -EIO;
-ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static void csid_subdev_init_980(struct csid_device *csid)
> +{
> + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
> +}
> +
> +const struct csid_hw_ops csid_ops_980 = {
> + .configure_stream = csid_configure_stream_980,
> + .configure_testgen_pattern = csid_configure_testgen_pattern_980,
> + .hw_version = csid_hw_version,
> + .isr = csid_isr_980,
> + .reset = csid_reset_980,
> + .src_pad_code = csid_src_pad_code,
> + .subdev_init = csid_subdev_init_980,
> + .reg_update = csid_subdev_reg_update_980,
> +};
> +
> diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
> index 6c214b487003..c77c61ab9c3a 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid.h
> +++ b/drivers/media/platform/qcom/camss/camss-csid.h
> @@ -223,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
> extern const struct csid_hw_ops csid_ops_4_7;
> extern const struct csid_hw_ops csid_ops_340;
> extern const struct csid_hw_ops csid_ops_680;
> +extern const struct csid_hw_ops csid_ops_980;
> extern const struct csid_hw_ops csid_ops_1080;
> extern const struct csid_hw_ops csid_ops_gen2;
> extern const struct csid_hw_ops csid_ops_gen3;
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index bfc942635682..9dea343c1ac5 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -3975,6 +3975,84 @@ static const struct camss_subdev_resources csiphy_res_8750[] = {
> },
> };
>
> +static const struct camss_subdev_resources csid_res_8750[] = {
> + /* CSID0 */
> + {
> + .regulators = {},
You don't need to initialise to the empty set.
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid0" },
> + .interrupt = { "csid0" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_980,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID1 */
> + {
> + .regulators = {},
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid1" },
> + .interrupt = { "csid1" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_980,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID2 */
> + {
> + .regulators = {},
> + .clock = { "csid", "csid_csiphy_rx" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid2" },
> + .interrupt = { "csid2" },
> + .csid = {
> + .is_lite = false,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_980,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID_LITE0 */
> + {
> + .regulators = {},
> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid_lite0" },
> + .interrupt = { "csid_lite0" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_980,
> + .formats = &csid_formats_gen2
> + }
> + },
> + /* CSID_LITE1 */
> + {
> + .regulators = {},
> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
> + .clock_rate = { { 400000000, 480000000 },
> + { 400000000, 480000000 } },
> + .reg = { "csid_lite1" },
> + .interrupt = { "csid_lite1" },
> + .csid = {
> + .is_lite = true,
> + .parent_dev_ops = &vfe_parent_dev_ops,
> + .hw_ops = &csid_ops_980,
> + .formats = &csid_formats_gen2
> + }
> + }
> +};
> +
> static const struct resources_icc icc_res_sm8750[] = {
> {
> .name = "ahb",
> @@ -5406,8 +5484,10 @@ static const struct camss_resources sm8750_resources = {
> .version = CAMSS_8750,
> .pd_name = "top",
> .csiphy_res = csiphy_res_8750,
> + .csid_res = csid_res_8750,
> .icc_res = icc_res_sm8750,
> .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
> + .csid_num = ARRAY_SIZE(csid_res_8750),
> .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
> };
>
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980
2025-11-27 10:01 ` Bryan O'Donoghue
@ 2026-01-06 18:07 ` Vijay Kumar Tumati
0 siblings, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:07 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Atiya Kailany
On 11/27/2025 2:01 AM, Bryan O'Donoghue wrote:
> On 26/11/2025 09:38, Hangxiang Ma wrote:
>> Add more detailed resource information for CSID devices along with the
>> driver for CSID 980 that is responsible for CSID register
>> configuration, module reset and IRQ handling for BUF_DONE events.
>>
>> In SM8750, RUP and AUP updates for the CSID Full modules are split into
>> two registers along with a SET register. However, CSID Lite modules
>> still use a single register to update RUP and AUP without the additional
>> SET register. Handled the difference in the driver.
>>
>> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/camss/Makefile | 1 +
>> drivers/media/platform/qcom/camss/camss-csid-980.c | 428
>> +++++++++++++++++++++
>> drivers/media/platform/qcom/camss/camss-csid.h | 1 +
>> drivers/media/platform/qcom/camss/camss.c | 80 ++++
>> 4 files changed, 510 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/camss/Makefile
>> b/drivers/media/platform/qcom/camss/Makefile
>> index a0abbca2b83d..74e12ec65427 100644
>> --- a/drivers/media/platform/qcom/camss/Makefile
>> +++ b/drivers/media/platform/qcom/camss/Makefile
>> @@ -8,6 +8,7 @@ qcom-camss-objs += \
>> camss-csid-4-7.o \
>> camss-csid-340.o \
>> camss-csid-680.o \
>> + camss-csid-980.o \
>> camss-csid-1080.o \
>> camss-csid-gen2.o \
>> camss-csid-gen3.o \
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c
>> b/drivers/media/platform/qcom/camss/camss-csid-980.c
>> new file mode 100644
>> index 000000000000..0656a912505a
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c
>> @@ -0,0 +1,428 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * camss-csid-980.c
>> + *
>> + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module
>> + *
>> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> + */
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of.h>
>> +#include "camss.h"
>> +#include "camss-csid.h"
>> +#include "camss-csid-gen3.h"
>> +
>> +/* Reset and Command Registers */
>> +#define CSID_RST_CFG 0xC
>> +#define RST_MODE BIT(0)
>> +#define RST_LOCATION BIT(4)
>> +
>> +/* Reset and Command Registers */
>> +#define CSID_RST_CMD 0x10
>> +#define SELECT_HW_RST BIT(0)
>> +#define SELECT_IRQ_RST BIT(2)
>> +#define CSID_IRQ_CMD 0x14
>> +#define IRQ_CMD_CLEAR BIT(0)
>> +
>> +/* Register Update Commands, RUP/AUP */
>> +#define CSID_RUP_CMD 0x18
>> +#define CSID_AUP_CMD 0x1C
>> +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi))
>> +#define CSID_RUP_AUP_CMD 0x20
>> +#define RUP_SET BIT(0)
>> +#define MUP BIT(4)
>> +
>> +#define CSID_LITE_RUP_AUP_CMD 0x18
>> +#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi))
>> +#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi))
>> +
>> +/* Top level interrupt registers */
>> +#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C :
>> 0x84)
>> +#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88)
>> +#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 :
>> 0x8C)
>> +#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90)
>> +#define INFO_RST_DONE BIT(0)
>> +#define CSI2_RX_IRQ_STATUS BIT(2)
>> +#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3)
>> +
>> +/* Buffer done interrupt registers */
>> +#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C :
>> 0xA4)
>> +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ?
>> 1 : 16)
>> +#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90
>> : 0xA8)
>> +#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ?
>> 0x94 : 0xAC)
>> +#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98
>> : 0xB0)
>> +
>> +/* CSI2 RX interrupt registers */
>> +#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ?
>> 0x9C : 0xB4)
>> +#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0
>> : 0xB8)
>> +#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4
>> : 0xBC)
>> +#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 :
>> 0xC0)
>> +
>> +/* CSI2 RX Configuration */
>> +#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 :
>> 0x400)
>> +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0
>> +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
>> +#define CSI2_RX_CFG0_PHY_NUM_SEL 20
>> +#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 :
>> 0x404)
>> +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0)
>> +#define CSI2_RX_CFG1_VC_MODE BIT(2)
>> +
>> +#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4
>> : 5)
>> +
>> +#define CSID_RDI_CFG0(rdi) \
>> + ({ \
>> + __typeof__(rdi) _rdi = (rdi); \
>> + csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \
>> + 0xE00 + 0x200 * _rdi; \
>> + })
>> +#define RDI_CFG0_RETIME_BS BIT(5)
>> +#define RDI_CFG0_TIMESTAMP_EN BIT(6)
>> +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8)
>> +#define RDI_CFG0_DECODE_FORMAT 12
>> +#define RDI_CFG0_DT 16
>> +#define RDI_CFG0_VC 22
>> +#define RDI_CFG0_DT_ID 27
>> +#define RDI_CFG0_EN BIT(31)
>> +
>> +/* RDI Control and Configuration */
>> +#define CSID_RDI_CTRL(rdi) \
>> + ({ \
>> + __typeof__(rdi) _rdi = (rdi); \
>> + csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \
>> + 0xE04 + 0x200 * _rdi; \
>> + })
>> +#define RDI_CTRL_START_CMD BIT(0)
>> +
>> +#define CSID_RDI_CFG1(rdi) \
>> + ({ \
>> + __typeof__(rdi) _rdi = (rdi); \
>> + csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \
>> + 0xE10 + 0x200 * _rdi; \
>> + })
>> +#define RDI_CFG1_DROP_H_EN BIT(5)
>> +#define RDI_CFG1_DROP_V_EN BIT(6)
>> +#define RDI_CFG1_CROP_H_EN BIT(7)
>> +#define RDI_CFG1_CROP_V_EN BIT(8)
>> +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15)
>> +
>> +/* RDI Pixel Store Configuration */
>> +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi))
>> +#define RDI_PIX_STORE_CFG0_EN BIT(0)
>> +#define RDI_PIX_STORE_CFG0_MIN_HBI 1
>> +
>> +/* RDI IRQ Status in wrapper */
>> +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \
>> + (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi))
>> +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \
>> + (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi))
>> +#define INFO_RUP_DONE BIT(23)
>> +
>> +static void __csid_full_aup_rup_trigger(struct csid_device *csid)
>> +{
>> + /* trigger SET in combined register */
>> + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD);
>> +}
>> +
>> +static void __csid_aup_update(struct csid_device *csid, int port_id)
>> +{
>> + if (!csid_is_lite(csid)) {
>> + csid->aup_update |= CSID_RUP_AUP_RDI(port_id);
>> + writel(csid->aup_update, csid->base + CSID_AUP_CMD);
>> +
>> + __csid_full_aup_rup_trigger(csid);
>> + } else {
>> + csid->reg_update |= CSID_LITE_AUP_RDI(port_id);
>> + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
>> + }
>
> This is backwards logic
>
> if (csid_is_lite()) {
> /* do stuff */
> } else {
> /* do other stuff */
> }
>
> Please add a comment to the code to explain why
> __csid_full_aup_rup_trigger is omitted in one case.
Ack.
>
>> +}
>> +
>> +static void __csid_rup_update(struct csid_device *csid, int port_id)
>> +{
>> + if (!csid_is_lite(csid)) {
>> + csid->rup_update |= CSID_RUP_AUP_RDI(port_id);
>> + writel(csid->rup_update, csid->base + CSID_RUP_CMD);
>> +
>> + __csid_full_aup_rup_trigger(csid);
>> + } else {
>> + csid->reg_update |= CSID_LITE_RUP_RDI(port_id);
>> + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD);
>> + }
>> +}
>> +
>> +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id)
>> +{
>> + /* Hardware clears the registers upon consuming the settings */
>> + if (csid_is_lite(csid)) {
>> + csid->reg_update &= ~CSID_LITE_RUP_RDI(port_id);
>> + csid->reg_update &= ~CSID_LITE_AUP_RDI(port_id);
>> + } else {
>> + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id);
>> + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id);
>> + }
>> +}
>
> Please be consistent with if (csid_is_lite())
Ack
>> +
>> +static void __csid_configure_rx(struct csid_device *csid,
>> + struct csid_phy_config *phy)
>> +{
>> + int val;
>> +
>> + val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
>> + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
>> + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX)
>> + << CSI2_RX_CFG0_PHY_NUM_SEL;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG0);
>> +
>> + val = CSI2_RX_CFG1_ECC_CORRECTION_EN;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
>> +}
>> +
>> +static void __csid_configure_rx_vc(struct csid_device *csid, int vc)
>> +{
>> + int val;
>> +
>> + if (vc > 3) {
>> + val = readl(csid->base + CSID_CSI2_RX_CFG1);
>> + val |= CSI2_RX_CFG1_VC_MODE;
>> + writel(val, csid->base + CSID_CSI2_RX_CFG1);
>> + }
>> +}
>> +
>> +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8
>> rdi)
>> +{
>> + int val = 0;
>> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(rdi);
>> +
>> + if (enable)
>> + val = RDI_CTRL_START_CMD;
>> +
>> + writel(val, csid->base + rdi_ctrl_offset);
>> +}
>> +
>> +static void __csid_configure_rdi_pix_store(struct csid_device *csid,
>> u8 rdi)
>> +{
>> + u32 val;
>> +
>> + /* Configure pixel store to allow absorption of hblanking or
>> idle time.
>> + * This helps with horizontal crop and prevents line buffer
>> conflicts.
>> + * Reset state is 0x8 which has MIN_HBI=4, we keep the default
>> MIN_HBI
>> + * and just enable the pixel store functionality.
>> + */
>> + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN;
>> + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi));
>> +}
>> +
>> +static void __csid_configure_rdi_stream(struct csid_device *csid, u8
>> enable, u8 vc)
>> +{
>> + u32 val;
>> + u8 lane_cnt = csid->phy.lane_cnt;
>> +
>> + /* Source pads matching RDI channels on hardware.
>> + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc.
>> + */
>> + struct v4l2_mbus_framefmt *input_format =
>> &csid->fmt[MSM_CSID_PAD_FIRST_SRC + vc];
>> + const struct csid_format_info *format =
>> csid_get_fmt_entry(csid->res->formats->formats,
>> + csid->res->formats->nformats,
>> + input_format->code);
>> +
>> + if (!lane_cnt)
>> + lane_cnt = 4;
>> +
>> + /*
>> + * DT_ID is a two bit bitfield that is concatenated with
>> + * the four least significant bits of the five bit VC
>> + * bitfield to generate an internal CID value.
>> + *
>> + * CSID_RDI_CFG0(vc)
>> + * DT_ID : 28:27
>> + * VC : 26:22
>> + * DT : 21:16
>> + *
>> + * CID : VC 3:0 << 2 | DT_ID 1:0
>> + */
>> + u8 dt_id = vc & 0x03;
>> + u32 rdi_cfg0_offset = CSID_RDI_CFG0(vc);
>> + u32 rdi_cfg1_offset = CSID_RDI_CFG1(vc);
>> + u32 rdi_ctrl_offset = CSID_RDI_CTRL(vc);
>> +
>> + val = RDI_CFG0_TIMESTAMP_EN;
>> + val |= RDI_CFG0_TIMESTAMP_STB_SEL;
>> + val |= RDI_CFG0_RETIME_BS;
>> +
>> + /* note: for non-RDI path, this should be format->decode_format */
>> + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT;
>> + val |= vc << RDI_CFG0_VC;
>> + val |= format->data_type << RDI_CFG0_DT;
>> + val |= dt_id << RDI_CFG0_DT_ID;
>> + writel(val, csid->base + rdi_cfg0_offset);
>> +
>> + val = RDI_CFG1_PACKING_FORMAT_MIPI;
>> + writel(val, csid->base + rdi_cfg1_offset);
>> +
>> + /* Configure pixel store using dedicated register in 980 */
>> + if (!csid_is_lite(csid))
>> + __csid_configure_rdi_pix_store(csid, vc);
>> +
>> + val = 0;
>> + writel(val, csid->base + rdi_ctrl_offset);
>> +
>> + val = readl(csid->base + rdi_cfg0_offset);
>> +
>> + if (enable)
>> + val |= RDI_CFG0_EN;
>> +
>> + writel(val, csid->base + rdi_cfg0_offset);
>> +}
>> +
>> +static void csid_configure_stream_980(struct csid_device *csid, u8
>> enable)
>> +{
>> + u8 vc, i;
>> +
>> + __csid_configure_rx(csid, &csid->phy);
>> +
>> + for (vc = 0; vc < MSM_CSID_MAX_SRC_STREAMS_980; vc++) {
>> + if (csid->phy.en_vc & BIT(vc)) {
>> + __csid_configure_rdi_stream(csid, enable, vc);
>> + __csid_configure_rx_vc(csid, vc);
>> +
>> + for (i = 0; i < CAMSS_INIT_BUF_COUNT; i++) {
>> + __csid_aup_update(csid, vc);
>> + __csid_rup_update(csid, vc);
>> + }
>> +
>> + __csid_ctrl_rdi(csid, enable, vc);
>> + }
>> + }
>> +}
>> +
>> +static int csid_configure_testgen_pattern_980(struct csid_device *csid,
>> + s32 val)
>> +{
>> + return 0;
>> +}
>> +
>> +static void csid_subdev_reg_update_980(struct csid_device *csid, int
>> port_id,
>> + bool clear)
>> +{
>> + if (clear)
>> + __csid_aup_rup_clear(csid, port_id);
>> + else
>> + __csid_aup_update(csid, port_id);
>> +}
>> +
>> +/**
>> + * csid_isr - CSID module interrupt service routine
>> + * @irq: Interrupt line
>> + * @dev: CSID device
>> + *
>> + * Return IRQ_HANDLED on success
>> + */
>> +static irqreturn_t csid_isr_980(int irq, void *dev)
>> +{
>> + struct csid_device *csid = dev;
>> + u32 val, buf_done_val;
>> + u8 reset_done;
>> + int i;
>> +
>> + val = readl(csid->base + CSID_TOP_IRQ_STATUS);
>> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
>> +
>> + reset_done = val & INFO_RST_DONE;
>> +
>> + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS);
>> + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
>> +
>> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
>> + if (csid->phy.en_vc & BIT(i)) {
>> + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i));
>> + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i));
>> +
>> + if (val & INFO_RUP_DONE)
>> + csid_subdev_reg_update_980(csid, i, true);
>> +
>> + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i))
>> + camss_buf_done(csid->camss, csid->id, i);
>> + }
>> + }
>> +
>> + val = IRQ_CMD_CLEAR;
>> + writel(val, csid->base + CSID_IRQ_CMD);
>> +
>> + if (reset_done)
>> + complete(&csid->reset_complete);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +/**
>> + * csid_reset - Trigger reset on CSID module and wait to complete
>> + * @csid: CSID device
>> + *
>> + * Return 0 on success or a negative error code otherwise
>> + */
>> +static int csid_reset_980(struct csid_device *csid)
>> +{
>> + unsigned long time;
>> + u32 val;
>> + int i;
>> +
>> + reinit_completion(&csid->reset_complete);
>> +
>> + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS;
>> + writel(val, csid->base + CSID_TOP_IRQ_CLEAR);
>> + writel(val, csid->base + CSID_TOP_IRQ_MASK);
>> +
>> + val = 0;
>> + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) {
>> + if (csid->phy.en_vc & BIT(i)) {
>> + /*
>> + * Only need to clear buf done IRQ status here,
>> + * RUP done IRQ status will be cleared once isr
>> + * strobe generated by CSID_RST_CMD
>> + */
>> + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i);
>> + }
>> + }
>> + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR);
>> + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK);
>> +
>> + /* Clear all IRQ status with CLEAR bits set */
>> + val = IRQ_CMD_CLEAR;
>> + writel(val, csid->base + CSID_IRQ_CMD);
>> +
>> + val = RST_LOCATION | RST_MODE;
>> + writel(val, csid->base + CSID_RST_CFG);
>> +
>> + val = SELECT_HW_RST | SELECT_IRQ_RST;
>> + writel(val, csid->base + CSID_RST_CMD);
>> +
>> + time = wait_for_completion_timeout(&csid->reset_complete,
>> + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS));
>> +
>> + if (!time) {
>> + dev_err(csid->camss->dev, "CSID reset timeout\n");
>> + return -EIO;
>
> -ETIMEDOUT;
Ack
>
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void csid_subdev_init_980(struct csid_device *csid)
>> +{
>> + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED;
>> +}
>> +
>> +const struct csid_hw_ops csid_ops_980 = {
>> + .configure_stream = csid_configure_stream_980,
>> + .configure_testgen_pattern = csid_configure_testgen_pattern_980,
>> + .hw_version = csid_hw_version,
>> + .isr = csid_isr_980,
>> + .reset = csid_reset_980,
>> + .src_pad_code = csid_src_pad_code,
>> + .subdev_init = csid_subdev_init_980,
>> + .reg_update = csid_subdev_reg_update_980,
>> +};
>> +
>> diff --git a/drivers/media/platform/qcom/camss/camss-csid.h
>> b/drivers/media/platform/qcom/camss/camss-csid.h
>> index 6c214b487003..c77c61ab9c3a 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csid.h
>> +++ b/drivers/media/platform/qcom/camss/camss-csid.h
>> @@ -223,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1;
>> extern const struct csid_hw_ops csid_ops_4_7;
>> extern const struct csid_hw_ops csid_ops_340;
>> extern const struct csid_hw_ops csid_ops_680;
>> +extern const struct csid_hw_ops csid_ops_980;
>> extern const struct csid_hw_ops csid_ops_1080;
>> extern const struct csid_hw_ops csid_ops_gen2;
>> extern const struct csid_hw_ops csid_ops_gen3;
>> diff --git a/drivers/media/platform/qcom/camss/camss.c
>> b/drivers/media/platform/qcom/camss/camss.c
>> index bfc942635682..9dea343c1ac5 100644
>> --- a/drivers/media/platform/qcom/camss/camss.c
>> +++ b/drivers/media/platform/qcom/camss/camss.c
>> @@ -3975,6 +3975,84 @@ static const struct camss_subdev_resources
>> csiphy_res_8750[] = {
>> },
>> };
>> +static const struct camss_subdev_resources csid_res_8750[] = {
>> + /* CSID0 */
>> + {
>> + .regulators = {},
>
> You don't need to initialise to the empty set.
Ack
>
>> + .clock = { "csid", "csid_csiphy_rx" },
>> + .clock_rate = { { 400000000, 480000000 },
>> + { 400000000, 480000000 } },
>> + .reg = { "csid0" },
>> + .interrupt = { "csid0" },
>> + .csid = {
>> + .is_lite = false,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .hw_ops = &csid_ops_980,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID1 */
>> + {
>> + .regulators = {},
>> + .clock = { "csid", "csid_csiphy_rx" },
>> + .clock_rate = { { 400000000, 480000000 },
>> + { 400000000, 480000000 } },
>> + .reg = { "csid1" },
>> + .interrupt = { "csid1" },
>> + .csid = {
>> + .is_lite = false,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .hw_ops = &csid_ops_980,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID2 */
>> + {
>> + .regulators = {},
>> + .clock = { "csid", "csid_csiphy_rx" },
>> + .clock_rate = { { 400000000, 480000000 },
>> + { 400000000, 480000000 } },
>> + .reg = { "csid2" },
>> + .interrupt = { "csid2" },
>> + .csid = {
>> + .is_lite = false,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .hw_ops = &csid_ops_980,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID_LITE0 */
>> + {
>> + .regulators = {},
>> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
>> + .clock_rate = { { 400000000, 480000000 },
>> + { 400000000, 480000000 } },
>> + .reg = { "csid_lite0" },
>> + .interrupt = { "csid_lite0" },
>> + .csid = {
>> + .is_lite = true,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .hw_ops = &csid_ops_980,
>> + .formats = &csid_formats_gen2
>> + }
>> + },
>> + /* CSID_LITE1 */
>> + {
>> + .regulators = {},
>> + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" },
>> + .clock_rate = { { 400000000, 480000000 },
>> + { 400000000, 480000000 } },
>> + .reg = { "csid_lite1" },
>> + .interrupt = { "csid_lite1" },
>> + .csid = {
>> + .is_lite = true,
>> + .parent_dev_ops = &vfe_parent_dev_ops,
>> + .hw_ops = &csid_ops_980,
>> + .formats = &csid_formats_gen2
>> + }
>> + }
>> +};
>> +
>> static const struct resources_icc icc_res_sm8750[] = {
>> {
>> .name = "ahb",
>> @@ -5406,8 +5484,10 @@ static const struct camss_resources
>> sm8750_resources = {
>> .version = CAMSS_8750,
>> .pd_name = "top",
>> .csiphy_res = csiphy_res_8750,
>> + .csid_res = csid_res_8750,
>> .icc_res = icc_res_sm8750,
>> .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
>> + .csid_num = ARRAY_SIZE(csid_res_8750),
>> .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
>> };
>>
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (4 preceding siblings ...)
2025-11-26 9:38 ` [PATCH 5/7] media: qcom: camss: csid: Add support for CSID 980 Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 10:04 ` Bryan O'Donoghue
2025-11-26 9:38 ` [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss Hangxiang Ma
6 siblings, 1 reply; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma,
Atiya Kailany
Add support for Video Front End (VFE) that is on the SM8750 SoCs. The
bus_wr configuration and the registers offsets closely match with the
driver that had been added for Kaanapali. Hence, rename the previously
added driver as 'gen4' and use that for both to avoid redundancy. Handle
the minor differences in the driver using the chipset version.
This change limits SM8750 VFE output lines to 3 for now as constrained
by the CAMSS driver framework.
Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
drivers/media/platform/qcom/camss/Makefile | 4 +-
.../camss/{camss-vfe-1080.c => camss-vfe-gen4.c} | 60 +++++----
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss-vfe.h | 2 +-
drivers/media/platform/qcom/camss/camss.c | 150 ++++++++++++++++++++-
5 files changed, 182 insertions(+), 36 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
index 74e12ec65427..6e54d2d11ed3 100644
--- a/drivers/media/platform/qcom/camss/Makefile
+++ b/drivers/media/platform/qcom/camss/Makefile
@@ -23,9 +23,9 @@ qcom-camss-objs += \
camss-vfe-340.o \
camss-vfe-480.o \
camss-vfe-680.o \
- camss-vfe-1080.o \
- camss-vfe-gen3.o \
camss-vfe-gen1.o \
+ camss-vfe-gen3.o \
+ camss-vfe-gen4.o \
camss-vfe-vbif.o \
camss-vfe.o \
camss-video.o \
diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
similarity index 75%
rename from drivers/media/platform/qcom/camss/camss-vfe-1080.c
rename to drivers/media/platform/qcom/camss/camss-vfe-gen4.c
index 9ad3dee2e80b..d0218950c05c 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe-1080.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * camss-vfe-1080.c
+ * camss-vfe-gen4.c
*
- * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
+ * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
@@ -13,8 +13,12 @@
#include "camss.h"
#include "camss-vfe.h"
-/* VFE-1080 Bus Register Base Addresses */
-#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define IS_VFE_980(vfe) ((vfe)->camss->res->version == CAMSS_8750)
+
+#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800)
+#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
+#define BUS_REG_BASE \
+ (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080)
#define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
#define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
@@ -55,7 +59,7 @@
* DISPLAY_DS2_C 6
* FD_Y 7
* FD_C 8
- * PIXEL_RAW 9
+ * RAW_OUT(1080)/IR_OUT(980) 9
* STATS_AEC_BG 10
* STATS_AEC_BHIST 11
* STATS_TINTLESS_BG 12
@@ -86,7 +90,7 @@
*/
#define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
-static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
+static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
{
struct v4l2_pix_format_mplane *pix =
&line->video_out.active_fmt.fmt.pix_mp;
@@ -121,14 +125,14 @@ static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *li
writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
}
-static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
+static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
{
wm = RDI_WM(wm);
writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
}
-static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
- struct vfe_line *line)
+static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
+ struct vfe_line *line)
{
wm = RDI_WM(wm);
writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
@@ -136,62 +140,62 @@ static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
}
-static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
+static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
{
int port_id = line_id;
camss_reg_update(vfe->camss, vfe->id, port_id, false);
}
-static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
- enum vfe_line_id line_id)
+static inline void vfe_reg_update_clear(struct vfe_device *vfe,
+ enum vfe_line_id line_id)
{
int port_id = line_id;
camss_reg_update(vfe->camss, vfe->id, port_id, true);
}
-static const struct camss_video_ops vfe_video_ops_1080 = {
+static const struct camss_video_ops vfe_video_ops = {
.queue_buffer = vfe_queue_buffer_v2,
.flush_buffers = vfe_flush_buffers,
};
-static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
+static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
{
- vfe->video_ops = vfe_video_ops_1080;
+ vfe->video_ops = vfe_video_ops;
}
-static void vfe_global_reset_1080(struct vfe_device *vfe)
+static void vfe_global_reset(struct vfe_device *vfe)
{
vfe_isr_reset_ack(vfe);
}
-static irqreturn_t vfe_isr_1080(int irq, void *dev)
+static irqreturn_t vfe_isr(int irq, void *dev)
{
/* nop */
return IRQ_HANDLED;
}
-static int vfe_halt_1080(struct vfe_device *vfe)
+static int vfe_halt(struct vfe_device *vfe)
{
/* rely on vfe_disable_output() to stop the VFE */
return 0;
}
-const struct vfe_hw_ops vfe_ops_1080 = {
- .global_reset = vfe_global_reset_1080,
+const struct vfe_hw_ops vfe_ops_gen4 = {
+ .global_reset = vfe_global_reset,
.hw_version = vfe_hw_version,
- .isr = vfe_isr_1080,
+ .isr = vfe_isr,
.pm_domain_off = vfe_pm_domain_off,
.pm_domain_on = vfe_pm_domain_on,
- .reg_update = vfe_reg_update_1080,
- .reg_update_clear = vfe_reg_update_clear_1080,
- .subdev_init = vfe_subdev_init_1080,
+ .reg_update = vfe_reg_update,
+ .reg_update_clear = vfe_reg_update_clear,
+ .subdev_init = vfe_subdev_init,
.vfe_disable = vfe_disable,
.vfe_enable = vfe_enable_v2,
- .vfe_halt = vfe_halt_1080,
- .vfe_wm_start = vfe_wm_start_1080,
- .vfe_wm_stop = vfe_wm_stop_1080,
+ .vfe_halt = vfe_halt,
+ .vfe_wm_start = vfe_wm_start,
+ .vfe_wm_stop = vfe_wm_stop,
.vfe_buf_done = vfe_buf_done,
- .vfe_wm_update = vfe_wm_update_1080,
+ .vfe_wm_update = vfe_wm_update,
};
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 399be8b70fed..b8aa4b7d1a8d 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -350,6 +350,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
@@ -2012,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
case CAMSS_845:
case CAMSS_8550:
case CAMSS_8650:
+ case CAMSS_8750:
case CAMSS_8775P:
case CAMSS_KAANAPALI:
case CAMSS_X1E80100:
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
index 118cac5daf37..c402ef170c81 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.h
+++ b/drivers/media/platform/qcom/camss/camss-vfe.h
@@ -249,8 +249,8 @@ extern const struct vfe_hw_ops vfe_ops_170;
extern const struct vfe_hw_ops vfe_ops_340;
extern const struct vfe_hw_ops vfe_ops_480;
extern const struct vfe_hw_ops vfe_ops_680;
-extern const struct vfe_hw_ops vfe_ops_1080;
extern const struct vfe_hw_ops vfe_ops_gen3;
+extern const struct vfe_hw_ops vfe_ops_gen4;
int vfe_get(struct vfe_device *vfe);
void vfe_put(struct vfe_device *vfe);
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 9dea343c1ac5..48d8f282d780 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -245,7 +245,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
.reg_update_after_csid_config = true,
.has_pd = true,
.pd_name = "vfe0",
- .hw_ops = &vfe_ops_1080,
+ .hw_ops = &vfe_ops_gen4,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -274,7 +274,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
.reg_update_after_csid_config = true,
.has_pd = true,
.pd_name = "vfe1",
- .hw_ops = &vfe_ops_1080,
+ .hw_ops = &vfe_ops_gen4,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -303,7 +303,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
.reg_update_after_csid_config = true,
.has_pd = true,
.pd_name = "vfe2",
- .hw_ops = &vfe_ops_1080,
+ .hw_ops = &vfe_ops_gen4,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -327,7 +327,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
.line_num = 4,
.is_lite = true,
.reg_update_after_csid_config = true,
- .hw_ops = &vfe_ops_1080,
+ .hw_ops = &vfe_ops_gen4,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -351,7 +351,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
.line_num = 4,
.is_lite = true,
.reg_update_after_csid_config = true,
- .hw_ops = &vfe_ops_1080,
+ .hw_ops = &vfe_ops_gen4,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
@@ -4053,6 +4053,144 @@ static const struct camss_subdev_resources csid_res_8750[] = {
}
};
+static const struct camss_subdev_resources vfe_res_8750[] = {
+ /* VFE0 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "vfe0",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "vfe1",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 - TFE Full */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
+ "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
+ "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 360280000, 480000000, 630000000, 716000000,
+ 833000000 },
+ { 0 },
+ { 0 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .is_lite = false,
+ .reg_update_after_csid_config = true,
+ .has_pd = true,
+ .pd_name = "vfe2",
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite0" },
+ .interrupt = { "vfe_lite0" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE_LITE1 */
+ {
+ .regulators = {},
+ .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
+ "camnoc_rt_vfe_lite", "camnoc_rt_axi",
+ "camnoc_nrt_axi", "qdss_debug_xo" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 266666667, 400000000, 480000000 },
+ { 0 },
+ { 200000000, 300000000, 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite1" },
+ .interrupt = { "vfe_lite1" },
+ .vfe = {
+ .line_num = 4,
+ .is_lite = true,
+ .reg_update_after_csid_config = true,
+ .hw_ops = &vfe_ops_gen4,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ }
+};
+
static const struct resources_icc icc_res_sm8750[] = {
{
.name = "ahb",
@@ -5485,9 +5623,11 @@ static const struct camss_resources sm8750_resources = {
.pd_name = "top",
.csiphy_res = csiphy_res_8750,
.csid_res = csid_res_8750,
+ .vfe_res = vfe_res_8750,
.icc_res = icc_res_sm8750,
.csiphy_num = ARRAY_SIZE(csiphy_res_8750),
.csid_num = ARRAY_SIZE(csid_res_8750),
+ .vfe_num = ARRAY_SIZE(vfe_res_8750),
.icc_path_num = ARRAY_SIZE(icc_res_sm8750),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4
2025-11-26 9:38 ` [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4 Hangxiang Ma
@ 2025-11-27 10:04 ` Bryan O'Donoghue
2026-01-06 18:17 ` Vijay Kumar Tumati
0 siblings, 1 reply; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 10:04 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Atiya Kailany
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add support for Video Front End (VFE) that is on the SM8750 SoCs. The
> bus_wr configuration and the registers offsets closely match with the
> driver that had been added for Kaanapali. Hence, rename the previously
> added driver as 'gen4' and use that for both to avoid redundancy. Handle
> the minor differences in the driver using the chipset version.
Specify you are renaming a file and dropping the 1080 postfix in its
naming convention.
>
> This change limits SM8750 VFE output lines to 3 for now as constrained
> by the CAMSS driver framework.
What does that mean ?
>
> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/camss/Makefile | 4 +-
> .../camss/{camss-vfe-1080.c => camss-vfe-gen4.c} | 60 +++++----
> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
> drivers/media/platform/qcom/camss/camss-vfe.h | 2 +-
> drivers/media/platform/qcom/camss/camss.c | 150 ++++++++++++++++++++-
> 5 files changed, 182 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile
> index 74e12ec65427..6e54d2d11ed3 100644
> --- a/drivers/media/platform/qcom/camss/Makefile
> +++ b/drivers/media/platform/qcom/camss/Makefile
> @@ -23,9 +23,9 @@ qcom-camss-objs += \
> camss-vfe-340.o \
> camss-vfe-480.o \
> camss-vfe-680.o \
> - camss-vfe-1080.o \
> - camss-vfe-gen3.o \
> camss-vfe-gen1.o \
> + camss-vfe-gen3.o \
> + camss-vfe-gen4.o \
> camss-vfe-vbif.o \
> camss-vfe.o \
> camss-video.o \
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
> similarity index 75%
> rename from drivers/media/platform/qcom/camss/camss-vfe-1080.c
> rename to drivers/media/platform/qcom/camss/camss-vfe-gen4.c
> index 9ad3dee2e80b..d0218950c05c 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe-1080.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
> @@ -1,8 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * camss-vfe-1080.c
> + * camss-vfe-gen4.c
> *
> - * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4
> *
> * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> */
> @@ -13,8 +13,12 @@
> #include "camss.h"
> #include "camss-vfe.h"
>
> -/* VFE-1080 Bus Register Base Addresses */
> -#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
> +#define IS_VFE_980(vfe) ((vfe)->camss->res->version == CAMSS_8750)
> +
> +#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800)
> +#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
> +#define BUS_REG_BASE \
> + (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080)
>
> #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
> #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
> @@ -55,7 +59,7 @@
> * DISPLAY_DS2_C 6
> * FD_Y 7
> * FD_C 8
> - * PIXEL_RAW 9
> + * RAW_OUT(1080)/IR_OUT(980) 9
> * STATS_AEC_BG 10
> * STATS_AEC_BHIST 11
> * STATS_TINTLESS_BG 12
> @@ -86,7 +90,7 @@
> */
> #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
>
> -static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
> {
> struct v4l2_pix_format_mplane *pix =
> &line->video_out.active_fmt.fmt.pix_mp;
> @@ -121,14 +125,14 @@ static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm, struct vfe_line *li
> writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
> }
>
> -static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
> +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
> {
> wm = RDI_WM(wm);
> writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
> }
>
> -static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
> - struct vfe_line *line)
> +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
> + struct vfe_line *line)
> {
> wm = RDI_WM(wm);
> writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
> @@ -136,62 +140,62 @@ static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32 addr,
> dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm, addr);
> }
>
> -static void vfe_reg_update_1080(struct vfe_device *vfe, enum vfe_line_id line_id)
> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
> {
> int port_id = line_id;
>
> camss_reg_update(vfe->camss, vfe->id, port_id, false);
> }
>
> -static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
> - enum vfe_line_id line_id)
> +static inline void vfe_reg_update_clear(struct vfe_device *vfe,
> + enum vfe_line_id line_id)
> {
> int port_id = line_id;
>
> camss_reg_update(vfe->camss, vfe->id, port_id, true);
> }
>
> -static const struct camss_video_ops vfe_video_ops_1080 = {
> +static const struct camss_video_ops vfe_video_ops = {
> .queue_buffer = vfe_queue_buffer_v2,
> .flush_buffers = vfe_flush_buffers,
> };
>
> -static void vfe_subdev_init_1080(struct device *dev, struct vfe_device *vfe)
> +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
> {
> - vfe->video_ops = vfe_video_ops_1080;
> + vfe->video_ops = vfe_video_ops;
> }
>
> -static void vfe_global_reset_1080(struct vfe_device *vfe)
> +static void vfe_global_reset(struct vfe_device *vfe)
> {
> vfe_isr_reset_ack(vfe);
> }
>
> -static irqreturn_t vfe_isr_1080(int irq, void *dev)
> +static irqreturn_t vfe_isr(int irq, void *dev)
> {
> /* nop */
> return IRQ_HANDLED;
> }
>
> -static int vfe_halt_1080(struct vfe_device *vfe)
> +static int vfe_halt(struct vfe_device *vfe)
> {
> /* rely on vfe_disable_output() to stop the VFE */
> return 0;
> }
>
> -const struct vfe_hw_ops vfe_ops_1080 = {
> - .global_reset = vfe_global_reset_1080,
> +const struct vfe_hw_ops vfe_ops_gen4 = {
> + .global_reset = vfe_global_reset,
> .hw_version = vfe_hw_version,
> - .isr = vfe_isr_1080,
> + .isr = vfe_isr,
> .pm_domain_off = vfe_pm_domain_off,
> .pm_domain_on = vfe_pm_domain_on,
> - .reg_update = vfe_reg_update_1080,
> - .reg_update_clear = vfe_reg_update_clear_1080,
> - .subdev_init = vfe_subdev_init_1080,
> + .reg_update = vfe_reg_update,
> + .reg_update_clear = vfe_reg_update_clear,
> + .subdev_init = vfe_subdev_init,
> .vfe_disable = vfe_disable,
> .vfe_enable = vfe_enable_v2,
> - .vfe_halt = vfe_halt_1080,
> - .vfe_wm_start = vfe_wm_start_1080,
> - .vfe_wm_stop = vfe_wm_stop_1080,
> + .vfe_halt = vfe_halt,
> + .vfe_wm_start = vfe_wm_start,
> + .vfe_wm_stop = vfe_wm_stop,
> .vfe_buf_done = vfe_buf_done,
> - .vfe_wm_update = vfe_wm_update_1080,
> + .vfe_wm_update = vfe_wm_update,
> };
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
> index 399be8b70fed..b8aa4b7d1a8d 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
> @@ -350,6 +350,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8650:
> + case CAMSS_8750:
> case CAMSS_8775P:
> case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> @@ -2012,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
> case CAMSS_845:
> case CAMSS_8550:
> case CAMSS_8650:
> + case CAMSS_8750:
> case CAMSS_8775P:
> case CAMSS_KAANAPALI:
> case CAMSS_X1E80100:
> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h b/drivers/media/platform/qcom/camss/camss-vfe.h
> index 118cac5daf37..c402ef170c81 100644
> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
> @@ -249,8 +249,8 @@ extern const struct vfe_hw_ops vfe_ops_170;
> extern const struct vfe_hw_ops vfe_ops_340;
> extern const struct vfe_hw_ops vfe_ops_480;
> extern const struct vfe_hw_ops vfe_ops_680;
> -extern const struct vfe_hw_ops vfe_ops_1080;
> extern const struct vfe_hw_ops vfe_ops_gen3;
> +extern const struct vfe_hw_ops vfe_ops_gen4;
>
> int vfe_get(struct vfe_device *vfe);
> void vfe_put(struct vfe_device *vfe);
> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
> index 9dea343c1ac5..48d8f282d780 100644
> --- a/drivers/media/platform/qcom/camss/camss.c
> +++ b/drivers/media/platform/qcom/camss/camss.c
> @@ -245,7 +245,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> .reg_update_after_csid_config = true,
> .has_pd = true,
> .pd_name = "vfe0",
> - .hw_ops = &vfe_ops_1080,
> + .hw_ops = &vfe_ops_gen4,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -274,7 +274,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> .reg_update_after_csid_config = true,
> .has_pd = true,
> .pd_name = "vfe1",
> - .hw_ops = &vfe_ops_1080,
> + .hw_ops = &vfe_ops_gen4,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -303,7 +303,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> .reg_update_after_csid_config = true,
> .has_pd = true,
> .pd_name = "vfe2",
> - .hw_ops = &vfe_ops_1080,
> + .hw_ops = &vfe_ops_gen4,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -327,7 +327,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> .line_num = 4,
> .is_lite = true,
> .reg_update_after_csid_config = true,
> - .hw_ops = &vfe_ops_1080,
> + .hw_ops = &vfe_ops_gen4,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -351,7 +351,7 @@ static const struct camss_subdev_resources vfe_res_kaanapali[] = {
> .line_num = 4,
> .is_lite = true,
> .reg_update_after_csid_config = true,
> - .hw_ops = &vfe_ops_1080,
> + .hw_ops = &vfe_ops_gen4,
> .formats_rdi = &vfe_formats_rdi_845,
> .formats_pix = &vfe_formats_pix_845
> }
> @@ -4053,6 +4053,144 @@ static const struct camss_subdev_resources csid_res_8750[] = {
> }
> };
>
> +static const struct camss_subdev_resources vfe_res_8750[] = {
> + /* VFE0 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe0" },
> + .interrupt = { "vfe0" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "vfe0",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE1 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe1" },
> + .interrupt = { "vfe1" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "vfe1",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE2 - TFE Full */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 360280000, 480000000, 630000000, 716000000,
> + 833000000 },
> + { 0 },
> + { 0 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe2" },
> + .interrupt = { "vfe2" },
> + .vfe = {
> + .line_num = 3,
> + .is_lite = false,
> + .reg_update_after_csid_config = true,
> + .has_pd = true,
> + .pd_name = "vfe2",
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE_LITE0 */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
> + "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 266666667, 400000000, 480000000 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite0" },
> + .interrupt = { "vfe_lite0" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .reg_update_after_csid_config = true,
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + },
> + /* VFE_LITE1 */
> + {
> + .regulators = {},
> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
> + "camnoc_nrt_axi", "qdss_debug_xo" },
> + .clock_rate = { { 0 },
> + { 0 },
> + { 266666667, 400000000, 480000000 },
> + { 0 },
> + { 200000000, 300000000, 400000000, 480000000 },
> + { 0 },
> + { 0 } },
> + .reg = { "vfe_lite1" },
> + .interrupt = { "vfe_lite1" },
> + .vfe = {
> + .line_num = 4,
> + .is_lite = true,
> + .reg_update_after_csid_config = true,
> + .hw_ops = &vfe_ops_gen4,
> + .formats_rdi = &vfe_formats_rdi_845,
> + .formats_pix = &vfe_formats_pix_845
> + }
> + }
> +};
> +
> static const struct resources_icc icc_res_sm8750[] = {
> {
> .name = "ahb",
> @@ -5485,9 +5623,11 @@ static const struct camss_resources sm8750_resources = {
> .pd_name = "top",
> .csiphy_res = csiphy_res_8750,
> .csid_res = csid_res_8750,
> + .vfe_res = vfe_res_8750,
> .icc_res = icc_res_sm8750,
> .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
> .csid_num = ARRAY_SIZE(csid_res_8750),
> + .vfe_num = ARRAY_SIZE(vfe_res_8750),
> .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
> };
>
>
Once done.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4
2025-11-27 10:04 ` Bryan O'Donoghue
@ 2026-01-06 18:17 ` Vijay Kumar Tumati
0 siblings, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:17 UTC (permalink / raw)
To: Bryan O'Donoghue, Hangxiang Ma, Loic Poulain, Robert Foss,
Andi Shyti, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Todor Tomov, Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Atiya Kailany
On 11/27/2025 2:04 AM, Bryan O'Donoghue wrote:
> On 26/11/2025 09:38, Hangxiang Ma wrote:
>> Add support for Video Front End (VFE) that is on the SM8750 SoCs. The
>> bus_wr configuration and the registers offsets closely match with the
>> driver that had been added for Kaanapali. Hence, rename the previously
>> added driver as 'gen4' and use that for both to avoid redundancy. Handle
>> the minor differences in the driver using the chipset version.
>
> Specify you are renaming a file and dropping the 1080 postfix in its
> naming convention.
We renamed this already in Kaanapali patches. Will rebase this on that.
>
>>
>> This change limits SM8750 VFE output lines to 3 for now as constrained
>> by the CAMSS driver framework.
>
> What does that mean ?
This is coming from
enum vfe_line_id {
VFE_LINE_NONE = -1,
VFE_LINE_RDI0 = 0,
VFE_LINE_RDI1 = 1,
VFE_LINE_RDI2 = 2,
VFE_LINE_PIX = 3,
VFE_LINE_NUM_MAX = 4
};
The way the VFE driver is currently implemented, expanding the RDIX
enums might break previous generations if they were using
'VFE_LINE_PIX'. If there is a need for more than 3 RDIs, we need to
cleanly fix this, probably in a dedicated patch. Please advise. Thanks.
>
>>
>> Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com>
>> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/camss/Makefile | 4 +-
>> .../camss/{camss-vfe-1080.c => camss-vfe-gen4.c} | 60 +++++----
>> drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
>> drivers/media/platform/qcom/camss/camss-vfe.h | 2 +-
>> drivers/media/platform/qcom/camss/camss.c | 150
>> ++++++++++++++++++++-
>> 5 files changed, 182 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/Makefile
>> b/drivers/media/platform/qcom/camss/Makefile
>> index 74e12ec65427..6e54d2d11ed3 100644
>> --- a/drivers/media/platform/qcom/camss/Makefile
>> +++ b/drivers/media/platform/qcom/camss/Makefile
>> @@ -23,9 +23,9 @@ qcom-camss-objs += \
>> camss-vfe-340.o \
>> camss-vfe-480.o \
>> camss-vfe-680.o \
>> - camss-vfe-1080.o \
>> - camss-vfe-gen3.o \
>> camss-vfe-gen1.o \
>> + camss-vfe-gen3.o \
>> + camss-vfe-gen4.o \
>> camss-vfe-vbif.o \
>> camss-vfe.o \
>> camss-video.o \
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
>> similarity index 75%
>> rename from drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> rename to drivers/media/platform/qcom/camss/camss-vfe-gen4.c
>> index 9ad3dee2e80b..d0218950c05c 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe-1080.c
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen4.c
>> @@ -1,8 +1,8 @@
>> // SPDX-License-Identifier: GPL-2.0
>> /*
>> - * camss-vfe-1080.c
>> + * camss-vfe-gen4.c
>> *
>> - * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v1080
>> + * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module gen4
>> *
>> * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>> */
>> @@ -13,8 +13,12 @@
>> #include "camss.h"
>> #include "camss-vfe.h"
>> -/* VFE-1080 Bus Register Base Addresses */
>> -#define BUS_REG_BASE (vfe_is_lite(vfe) ? 0x800 : 0x1000)
>> +#define IS_VFE_980(vfe) ((vfe)->camss->res->version == CAMSS_8750)
>> +
>> +#define BUS_REG_BASE_980 (vfe_is_lite(vfe) ? 0x200 : 0x800)
>> +#define BUS_REG_BASE_1080 (vfe_is_lite(vfe) ? 0x800 : 0x1000)
>> +#define BUS_REG_BASE \
>> + (IS_VFE_980(vfe) ? BUS_REG_BASE_980 : BUS_REG_BASE_1080)
>> #define VFE_BUS_WM_CGC_OVERRIDE (BUS_REG_BASE + 0x08)
>> #define WM_CGC_OVERRIDE_ALL (0x7FFFFFF)
>> @@ -55,7 +59,7 @@
>> * DISPLAY_DS2_C 6
>> * FD_Y 7
>> * FD_C 8
>> - * PIXEL_RAW 9
>> + * RAW_OUT(1080)/IR_OUT(980) 9
>> * STATS_AEC_BG 10
>> * STATS_AEC_BHIST 11
>> * STATS_TINTLESS_BG 12
>> @@ -86,7 +90,7 @@
>> */
>> #define RDI_WM(n) ((vfe_is_lite(vfe) ? 0x0 : 0x17) + (n))
>> -static void vfe_wm_start_1080(struct vfe_device *vfe, u8 wm,
>> struct vfe_line *line)
>> +static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct
>> vfe_line *line)
>> {
>> struct v4l2_pix_format_mplane *pix =
>> &line->video_out.active_fmt.fmt.pix_mp;
>> @@ -121,14 +125,14 @@ static void vfe_wm_start_1080(struct vfe_device
>> *vfe, u8 wm, struct vfe_line *li
>> writel(WM_CFG_EN | WM_CFG_MODE, vfe->base + VFE_BUS_WM_CFG(wm));
>> }
>> -static void vfe_wm_stop_1080(struct vfe_device *vfe, u8 wm)
>> +static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
>> {
>> wm = RDI_WM(wm);
>> writel(0, vfe->base + VFE_BUS_WM_CFG(wm));
>> }
>> -static void vfe_wm_update_1080(struct vfe_device *vfe, u8 wm, u32
>> addr,
>> - struct vfe_line *line)
>> +static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
>> + struct vfe_line *line)
>> {
>> wm = RDI_WM(wm);
>> writel(addr >> 8, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
>> @@ -136,62 +140,62 @@ static void vfe_wm_update_1080(struct
>> vfe_device *vfe, u8 wm, u32 addr,
>> dev_dbg(vfe->camss->dev, "wm:%d, image buf addr:0x%x\n", wm,
>> addr);
>> }
>> -static void vfe_reg_update_1080(struct vfe_device *vfe, enum
>> vfe_line_id line_id)
>> +static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id
>> line_id)
>> {
>> int port_id = line_id;
>> camss_reg_update(vfe->camss, vfe->id, port_id, false);
>> }
>> -static inline void vfe_reg_update_clear_1080(struct vfe_device *vfe,
>> - enum vfe_line_id line_id)
>> +static inline void vfe_reg_update_clear(struct vfe_device *vfe,
>> + enum vfe_line_id line_id)
>> {
>> int port_id = line_id;
>> camss_reg_update(vfe->camss, vfe->id, port_id, true);
>> }
>> -static const struct camss_video_ops vfe_video_ops_1080 = {
>> +static const struct camss_video_ops vfe_video_ops = {
>> .queue_buffer = vfe_queue_buffer_v2,
>> .flush_buffers = vfe_flush_buffers,
>> };
>> -static void vfe_subdev_init_1080(struct device *dev, struct
>> vfe_device *vfe)
>> +static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
>> {
>> - vfe->video_ops = vfe_video_ops_1080;
>> + vfe->video_ops = vfe_video_ops;
>> }
>> -static void vfe_global_reset_1080(struct vfe_device *vfe)
>> +static void vfe_global_reset(struct vfe_device *vfe)
>> {
>> vfe_isr_reset_ack(vfe);
>> }
>> -static irqreturn_t vfe_isr_1080(int irq, void *dev)
>> +static irqreturn_t vfe_isr(int irq, void *dev)
>> {
>> /* nop */
>> return IRQ_HANDLED;
>> }
>> -static int vfe_halt_1080(struct vfe_device *vfe)
>> +static int vfe_halt(struct vfe_device *vfe)
>> {
>> /* rely on vfe_disable_output() to stop the VFE */
>> return 0;
>> }
>> -const struct vfe_hw_ops vfe_ops_1080 = {
>> - .global_reset = vfe_global_reset_1080,
>> +const struct vfe_hw_ops vfe_ops_gen4 = {
>> + .global_reset = vfe_global_reset,
>> .hw_version = vfe_hw_version,
>> - .isr = vfe_isr_1080,
>> + .isr = vfe_isr,
>> .pm_domain_off = vfe_pm_domain_off,
>> .pm_domain_on = vfe_pm_domain_on,
>> - .reg_update = vfe_reg_update_1080,
>> - .reg_update_clear = vfe_reg_update_clear_1080,
>> - .subdev_init = vfe_subdev_init_1080,
>> + .reg_update = vfe_reg_update,
>> + .reg_update_clear = vfe_reg_update_clear,
>> + .subdev_init = vfe_subdev_init,
>> .vfe_disable = vfe_disable,
>> .vfe_enable = vfe_enable_v2,
>> - .vfe_halt = vfe_halt_1080,
>> - .vfe_wm_start = vfe_wm_start_1080,
>> - .vfe_wm_stop = vfe_wm_stop_1080,
>> + .vfe_halt = vfe_halt,
>> + .vfe_wm_start = vfe_wm_start,
>> + .vfe_wm_stop = vfe_wm_stop,
>> .vfe_buf_done = vfe_buf_done,
>> - .vfe_wm_update = vfe_wm_update_1080,
>> + .vfe_wm_update = vfe_wm_update,
>> };
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c
>> b/drivers/media/platform/qcom/camss/camss-vfe.c
>> index 399be8b70fed..b8aa4b7d1a8d 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe.c
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c
>> @@ -350,6 +350,7 @@ static u32 vfe_src_pad_code(struct vfe_line
>> *line, u32 sink_code,
>> case CAMSS_845:
>> case CAMSS_8550:
>> case CAMSS_8650:
>> + case CAMSS_8750:
>> case CAMSS_8775P:
>> case CAMSS_KAANAPALI:
>> case CAMSS_X1E80100:
>> @@ -2012,6 +2013,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
>> case CAMSS_845:
>> case CAMSS_8550:
>> case CAMSS_8650:
>> + case CAMSS_8750:
>> case CAMSS_8775P:
>> case CAMSS_KAANAPALI:
>> case CAMSS_X1E80100:
>> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.h
>> b/drivers/media/platform/qcom/camss/camss-vfe.h
>> index 118cac5daf37..c402ef170c81 100644
>> --- a/drivers/media/platform/qcom/camss/camss-vfe.h
>> +++ b/drivers/media/platform/qcom/camss/camss-vfe.h
>> @@ -249,8 +249,8 @@ extern const struct vfe_hw_ops vfe_ops_170;
>> extern const struct vfe_hw_ops vfe_ops_340;
>> extern const struct vfe_hw_ops vfe_ops_480;
>> extern const struct vfe_hw_ops vfe_ops_680;
>> -extern const struct vfe_hw_ops vfe_ops_1080;
>> extern const struct vfe_hw_ops vfe_ops_gen3;
>> +extern const struct vfe_hw_ops vfe_ops_gen4;
>> int vfe_get(struct vfe_device *vfe);
>> void vfe_put(struct vfe_device *vfe);
>> diff --git a/drivers/media/platform/qcom/camss/camss.c
>> b/drivers/media/platform/qcom/camss/camss.c
>> index 9dea343c1ac5..48d8f282d780 100644
>> --- a/drivers/media/platform/qcom/camss/camss.c
>> +++ b/drivers/media/platform/qcom/camss/camss.c
>> @@ -245,7 +245,7 @@ static const struct camss_subdev_resources
>> vfe_res_kaanapali[] = {
>> .reg_update_after_csid_config = true,
>> .has_pd = true,
>> .pd_name = "vfe0",
>> - .hw_ops = &vfe_ops_1080,
>> + .hw_ops = &vfe_ops_gen4,
>> .formats_rdi = &vfe_formats_rdi_845,
>> .formats_pix = &vfe_formats_pix_845
>> }
>> @@ -274,7 +274,7 @@ static const struct camss_subdev_resources
>> vfe_res_kaanapali[] = {
>> .reg_update_after_csid_config = true,
>> .has_pd = true,
>> .pd_name = "vfe1",
>> - .hw_ops = &vfe_ops_1080,
>> + .hw_ops = &vfe_ops_gen4,
>> .formats_rdi = &vfe_formats_rdi_845,
>> .formats_pix = &vfe_formats_pix_845
>> }
>> @@ -303,7 +303,7 @@ static const struct camss_subdev_resources
>> vfe_res_kaanapali[] = {
>> .reg_update_after_csid_config = true,
>> .has_pd = true,
>> .pd_name = "vfe2",
>> - .hw_ops = &vfe_ops_1080,
>> + .hw_ops = &vfe_ops_gen4,
>> .formats_rdi = &vfe_formats_rdi_845,
>> .formats_pix = &vfe_formats_pix_845
>> }
>> @@ -327,7 +327,7 @@ static const struct camss_subdev_resources
>> vfe_res_kaanapali[] = {
>> .line_num = 4,
>> .is_lite = true,
>> .reg_update_after_csid_config = true,
>> - .hw_ops = &vfe_ops_1080,
>> + .hw_ops = &vfe_ops_gen4,
>> .formats_rdi = &vfe_formats_rdi_845,
>> .formats_pix = &vfe_formats_pix_845
>> }
>> @@ -351,7 +351,7 @@ static const struct camss_subdev_resources
>> vfe_res_kaanapali[] = {
>> .line_num = 4,
>> .is_lite = true,
>> .reg_update_after_csid_config = true,
>> - .hw_ops = &vfe_ops_1080,
>> + .hw_ops = &vfe_ops_gen4,
>> .formats_rdi = &vfe_formats_rdi_845,
>> .formats_pix = &vfe_formats_pix_845
>> }
>> @@ -4053,6 +4053,144 @@ static const struct camss_subdev_resources
>> csid_res_8750[] = {
>> }
>> };
>> +static const struct camss_subdev_resources vfe_res_8750[] = {
>> + /* VFE0 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe0_fast_ahb", "vfe0",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe0" },
>> + .interrupt = { "vfe0" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .reg_update_after_csid_config = true,
>> + .has_pd = true,
>> + .pd_name = "vfe0",
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE1 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe1_fast_ahb", "vfe1",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe1" },
>> + .interrupt = { "vfe1" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .reg_update_after_csid_config = true,
>> + .has_pd = true,
>> + .pd_name = "vfe1",
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE2 - TFE Full */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe2_fast_ahb", "vfe2",
>> + "camnoc_rt_vfe0", "camnoc_rt_vfe1", "camnoc_rt_vfe2",
>> + "camnoc_rt_axi", "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 360280000, 480000000, 630000000, 716000000,
>> + 833000000 },
>> + { 0 },
>> + { 0 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe2" },
>> + .interrupt = { "vfe2" },
>> + .vfe = {
>> + .line_num = 3,
>> + .is_lite = false,
>> + .reg_update_after_csid_config = true,
>> + .has_pd = true,
>> + .pd_name = "vfe2",
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE_LITE0 */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
>> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
>> + "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 266666667, 400000000, 480000000 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe_lite0" },
>> + .interrupt = { "vfe_lite0" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .reg_update_after_csid_config = true,
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + },
>> + /* VFE_LITE1 */
>> + {
>> + .regulators = {},
>> + .clock = { "gcc_hf_axi", "vfe_lite_ahb", "vfe_lite",
>> + "camnoc_rt_vfe_lite", "camnoc_rt_axi",
>> + "camnoc_nrt_axi", "qdss_debug_xo" },
>> + .clock_rate = { { 0 },
>> + { 0 },
>> + { 266666667, 400000000, 480000000 },
>> + { 0 },
>> + { 200000000, 300000000, 400000000, 480000000 },
>> + { 0 },
>> + { 0 } },
>> + .reg = { "vfe_lite1" },
>> + .interrupt = { "vfe_lite1" },
>> + .vfe = {
>> + .line_num = 4,
>> + .is_lite = true,
>> + .reg_update_after_csid_config = true,
>> + .hw_ops = &vfe_ops_gen4,
>> + .formats_rdi = &vfe_formats_rdi_845,
>> + .formats_pix = &vfe_formats_pix_845
>> + }
>> + }
>> +};
>> +
>> static const struct resources_icc icc_res_sm8750[] = {
>> {
>> .name = "ahb",
>> @@ -5485,9 +5623,11 @@ static const struct camss_resources
>> sm8750_resources = {
>> .pd_name = "top",
>> .csiphy_res = csiphy_res_8750,
>> .csid_res = csid_res_8750,
>> + .vfe_res = vfe_res_8750,
>> .icc_res = icc_res_sm8750,
>> .csiphy_num = ARRAY_SIZE(csiphy_res_8750),
>> .csid_num = ARRAY_SIZE(csid_res_8750),
>> + .vfe_num = ARRAY_SIZE(vfe_res_8750),
>> .icc_path_num = ARRAY_SIZE(icc_res_sm8750),
>> };
>>
>
> Once done.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2025-11-26 9:38 [PATCH 0/7] media: qcom: camss: Add SM8750 support Hangxiang Ma
` (5 preceding siblings ...)
2025-11-26 9:38 ` [PATCH 6/7] media: qcom: camss: vfe: Add support for VFE gen4 Hangxiang Ma
@ 2025-11-26 9:38 ` Hangxiang Ma
2025-11-27 8:12 ` Krzysztof Kozlowski
2025-11-27 10:06 ` Bryan O'Donoghue
6 siblings, 2 replies; 29+ messages in thread
From: Hangxiang Ma @ 2025-11-26 9:38 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati, Hangxiang Ma
Add support for the camera subsystem on the SM8750 Qualcomm SoC. This
includes bringing up the CSIPHY, CSID, VFE/RDI interfaces. This change
also introduces the necessary modules for enabling future extended
functionalities.
The SM8750 platform provides:
- 3 x VFE, 5 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE
- 3 x CSID
- 2 x CSID Lite
- 6 x CSI PHY
- 2 x ICP
- 1 x IPE
- 2 x JPEG DMA & Downscaler
- 2 x JPEG Encoder
- 1 x OFE
- 5 x RT CDM
- 3 x TPG
Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 +++++++++++++++++++++++++++++++++++
1 file changed, 599 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 1937b48fac5a..b83389c3456b 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3332,6 +3332,605 @@ data-pins {
bias-pull-up;
};
};
+
+ cci0_0_default: cci0-0-default-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_0_sleep: cci0-0-sleep-state {
+ sda-pins {
+ pins = "gpio113";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio114";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci0_1_default: cci0-1-default-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_1_sleep: cci0-1-sleep-state {
+ sda-pins {
+ pins = "gpio115";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio116";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_0_default: cci1-0-default-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_0_sleep: cci1-0-sleep-state {
+ sda-pins {
+ pins = "gpio117";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio118";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_1_default: cci1-1-default-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_1_sleep: cci1-1-sleep-state {
+ sda-pins {
+ pins = "gpio111";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio164";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_0_default: cci2-0-default-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_0_sleep: cci2-0-sleep-state {
+ sda-pins {
+ pins = "gpio112";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio153";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci2_1_default: cci2-1-default-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci2_1_sleep: cci2-1-sleep-state {
+ sda-pins {
+ pins = "gpio119";
+ function = "cci_i2c_sda";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ scl-pins {
+ pins = "gpio120";
+ function = "cci_i2c_scl";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ cci0: cci@ac7b000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7b000 0x0 0x1000>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci0_0_default &cci0_1_default>;
+ pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac7c000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7c000 0x0 0x1000>;
+ interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci1_0_default &cci1_1_default>;
+ pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci2: cci@ac7d000 {
+ compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
+ reg = <0x0 0x0ac7d000 0x0 0x1000>;
+ interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CCI_2_CLK>;
+ clock-names = "ahb", "cci";
+ pinctrl-0 = <&cci2_0_default &cci2_1_default>;
+ pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
+ pinctrl-names = "default", "sleep";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cci2_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci2_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ camss: isp@ad27000 {
+ compatible = "qcom,sm8750-camss";
+
+ reg = <0x0 0x0ad27000 0x0 0x2b00>,
+ <0x0 0x0ad2a000 0x0 0x2b00>,
+ <0x0 0x0ad2d000 0x0 0x2b00>,
+ <0x0 0x0ad6d000 0x0 0xa00>,
+ <0x0 0x0ad72000 0x0 0xa00>,
+ <0x0 0x0ada9000 0x0 0x2000>,
+ <0x0 0x0adab000 0x0 0x2000>,
+ <0x0 0x0adad000 0x0 0x2000>,
+ <0x0 0x0adaf000 0x0 0x2000>,
+ <0x0 0x0adb1000 0x0 0x2000>,
+ <0x0 0x0adb3000 0x0 0x2000>,
+ <0x0 0x0ac86000 0x0 0x10000>,
+ <0x0 0x0ac96000 0x0 0x10000>,
+ <0x0 0x0aca6000 0x0 0x10000>,
+ <0x0 0x0ad6e000 0x0 0x1800>,
+ <0x0 0x0ad73000 0x0 0x1800>,
+ <0x0 0x0ac06000 0x0 0x1000>,
+ <0x0 0x0ac05000 0x0 0x1000>,
+ <0x0 0x0ac16000 0x0 0x1000>,
+ <0x0 0x0ac15000 0x0 0x1000>,
+ <0x0 0x0ac42000 0x0 0x18000>,
+ <0x0 0x0ac26000 0x0 0x1000>,
+ <0x0 0x0ac25000 0x0 0x1000>,
+ <0x0 0x0ac28000 0x0 0x1000>,
+ <0x0 0x0ac27000 0x0 0x1000>,
+ <0x0 0x0ac2a000 0x0 0x18000>,
+ <0x0 0x0ac7f000 0x0 0x580>,
+ <0x0 0x0ac80000 0x0 0x580>,
+ <0x0 0x0ac81000 0x0 0x580>,
+ <0x0 0x0ac82000 0x0 0x580>,
+ <0x0 0x0ac83000 0x0 0x580>,
+ <0x0 0x0ad8b000 0x0 0x400>,
+ <0x0 0x0ad8c000 0x0 0x400>,
+ <0x0 0x0ad8d000 0x0 0x400>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "icp0",
+ "icp0_sys",
+ "icp1",
+ "icp1_sys",
+ "ipe",
+ "jpeg_dma0",
+ "jpeg_enc0",
+ "jpeg_dma1",
+ "jpeg_enc1",
+ "ofe",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
+ <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_CLK>,
+ <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+ <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>,
+ <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_ICP_0_CLK>,
+ <&camcc CAM_CC_ICP_0_AHB_CLK>,
+ <&camcc CAM_CC_ICP_1_CLK>,
+ <&camcc CAM_CC_ICP_1_AHB_CLK>,
+ <&camcc CAM_CC_IPE_NPS_CLK>,
+ <&camcc CAM_CC_IPE_NPS_AHB_CLK>,
+ <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IPE_PPS_CLK>,
+ <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_JPEG_0_CLK>,
+ <&camcc CAM_CC_JPEG_1_CLK>,
+ <&camcc CAM_CC_OFE_AHB_CLK>,
+ <&camcc CAM_CC_OFE_ANCHOR_CLK>,
+ <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>,
+ <&camcc CAM_CC_OFE_HDR_CLK>,
+ <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>,
+ <&camcc CAM_CC_OFE_MAIN_CLK>,
+ <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_0_BAYER_CLK>,
+ <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_1_BAYER_CLK>,
+ <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>,
+ <&camcc CAM_CC_TFE_2_BAYER_CLK>,
+ <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>;
+ clock-names = "camnoc_nrt_axi",
+ "camnoc_rt_axi",
+ "camnoc_rt_vfe0",
+ "camnoc_rt_vfe1",
+ "camnoc_rt_vfe2",
+ "camnoc_rt_vfe_lite",
+ "cam_top_ahb",
+ "cam_top_fast_ahb",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "csiphy5",
+ "csiphy5_timer",
+ "gcc_hf_axi",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe2",
+ "vfe2_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "qdss_debug_xo",
+ "camnoc_ipe_nps",
+ "camnoc_ofe",
+ "gcc_sf_axi",
+ "icp0",
+ "icp0_ahb",
+ "icp1",
+ "icp1_ahb",
+ "ipe_nps",
+ "ipe_nps_ahb",
+ "ipe_nps_fast_ahb",
+ "ipe_pps",
+ "ipe_pps_fast_ahb",
+ "jpeg0",
+ "jpeg1",
+ "ofe_ahb",
+ "ofe_anchor",
+ "ofe_anchor_fast_ahb",
+ "ofe_hdr",
+ "ofe_hdr_fast_ahb",
+ "ofe_main",
+ "ofe_main_fast_ahb",
+ "vfe0_bayer",
+ "vfe0_bayer_fast_ahb",
+ "vfe1_bayer",
+ "vfe1_bayer_fast_ahb",
+ "vfe2_bayer",
+ "vfe2_bayer_fast_ahb";
+
+ interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "csiphy4",
+ "csiphy5",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "camnoc_nrt",
+ "camnoc_rt",
+ "icp0",
+ "icp1",
+ "jpeg_dma0",
+ "jpeg_enc0",
+ "jpeg_dma1",
+ "jpeg_enc1",
+ "rt_cdm0",
+ "rt_cdm1",
+ "rt_cdm2",
+ "rt_cdm3",
+ "rt_cdm4",
+ "tpg0",
+ "tpg1",
+ "tpg2";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_icp_mnoc",
+ "sf_mnoc";
+
+ iommus = <&apps_smmu 0x1c00 0x00>,
+ <&apps_smmu 0x18c0 0x00>,
+ <&apps_smmu 0x1980 0x00>,
+ <&apps_smmu 0x1840 0x00>,
+ <&apps_smmu 0x1800 0x00>,
+ <&apps_smmu 0x18a0 0x00>,
+ <&apps_smmu 0x1880 0x00>,
+ <&apps_smmu 0x1820 0x00>,
+ <&apps_smmu 0x1860 0x00>;
+
+ power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
+ <&camcc CAM_CC_TFE_1_GDSC>,
+ <&camcc CAM_CC_TFE_2_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>,
+ <&camcc CAM_CC_IPE_0_GDSC>,
+ <&camcc CAM_CC_OFE_GDSC>;
+ power-domain-names = "vfe0",
+ "vfe1",
+ "vfe2",
+ "top",
+ "ipe",
+ "ofe";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+ };
+
};
tcsrcc: clock-controller@f204008 {
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2025-11-26 9:38 ` [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss Hangxiang Ma
@ 2025-11-27 8:12 ` Krzysztof Kozlowski
2026-01-06 18:40 ` Vijay Kumar Tumati
2025-11-27 10:06 ` Bryan O'Donoghue
1 sibling, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-27 8:12 UTC (permalink / raw)
To: Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
+
> + cci1_1_default: cci1-1-default-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_1_sleep: cci1-1-sleep-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_0_default: cci2-0-default-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_0_sleep: cci2-0-sleep-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_1_default: cci2-1-default-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_1_sleep: cci2-1-sleep-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> + };
> +
> + cci0: cci@ac7b000 {
Looks completely mis-ordered/sorted. What are the nodes above and below?
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7b000 0x0 0x1000>;
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2025-11-27 8:12 ` Krzysztof Kozlowski
@ 2026-01-06 18:40 ` Vijay Kumar Tumati
2026-01-06 19:18 ` Krzysztof Kozlowski
0 siblings, 1 reply; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 18:40 UTC (permalink / raw)
To: Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:
> On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
> +
>> + cci1_1_default: cci1-1-default-state {
>> + sda-pins {
>> + pins = "gpio111";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio164";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + cci1_1_sleep: cci1-1-sleep-state {
>> + sda-pins {
>> + pins = "gpio111";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio164";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + cci2_0_default: cci2-0-default-state {
>> + sda-pins {
>> + pins = "gpio112";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio153";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + cci2_0_sleep: cci2-0-sleep-state {
>> + sda-pins {
>> + pins = "gpio112";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio153";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> +
>> + cci2_1_default: cci2-1-default-state {
>> + sda-pins {
>> + pins = "gpio119";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio120";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>> +
>> + cci2_1_sleep: cci2-1-sleep-state {
>> + sda-pins {
>> + pins = "gpio119";
>> + function = "cci_i2c_sda";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + scl-pins {
>> + pins = "gpio120";
>> + function = "cci_i2c_scl";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> + };
>> + };
>> +
>> + cci0: cci@ac7b000 {
> Looks completely mis-ordered/sorted. What are the nodes above and below?
Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are
the pinctrl nodes. Each CCI has two masters using two GPIOs each, one
for clk and one for data. The ones below are the actual CCI HW nodes
that make use of the pinctrls. I believe this is inline with previous
generations. Have I missed something? Thanks.
>
>
>> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
>> + reg = <0x0 0x0ac7b000 0x0 0x1000>;
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2026-01-06 18:40 ` Vijay Kumar Tumati
@ 2026-01-06 19:18 ` Krzysztof Kozlowski
2026-01-06 19:20 ` Krzysztof Kozlowski
0 siblings, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-06 19:18 UTC (permalink / raw)
To: Vijay Kumar Tumati, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 06/01/2026 19:40, Vijay Kumar Tumati wrote:
>
> On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:
>> On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
>> +
>>> + cci1_1_default: cci1-1-default-state {
>>> + sda-pins {
>>> + pins = "gpio111";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio164";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> + };
>>> +
>>> + cci1_1_sleep: cci1-1-sleep-state {
>>> + sda-pins {
>>> + pins = "gpio111";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio164";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> + };
>>> +
>>> + cci2_0_default: cci2-0-default-state {
>>> + sda-pins {
>>> + pins = "gpio112";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio153";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> + };
>>> +
>>> + cci2_0_sleep: cci2-0-sleep-state {
>>> + sda-pins {
>>> + pins = "gpio112";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio153";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> + };
>>> +
>>> + cci2_1_default: cci2-1-default-state {
>>> + sda-pins {
>>> + pins = "gpio119";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio120";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-up;
>>> + };
>>> + };
>>> +
>>> + cci2_1_sleep: cci2-1-sleep-state {
>>> + sda-pins {
>>> + pins = "gpio119";
>>> + function = "cci_i2c_sda";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> +
>>> + scl-pins {
>>> + pins = "gpio120";
>>> + function = "cci_i2c_scl";
>>> + drive-strength = <2>;
>>> + bias-pull-down;
>>> + };
>>> + };
>>> + };
>>> +
>>> + cci0: cci@ac7b000 {
>> Looks completely mis-ordered/sorted. What are the nodes above and below?
> Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are
> the pinctrl nodes. Each CCI has two masters using two GPIOs each, one
Why would pinctrl nodes matter anyhow? Please read how DTS syntax works.
> for clk and one for data. The ones below are the actual CCI HW nodes
> that make use of the pinctrls. I believe this is inline with previous
> generations. Have I missed something? Thanks.
I wrote what is wrong. Is this maintaining proper sorting? Did you read
DTS coding style?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2026-01-06 19:18 ` Krzysztof Kozlowski
@ 2026-01-06 19:20 ` Krzysztof Kozlowski
2026-01-06 19:43 ` Vijay Kumar Tumati
0 siblings, 1 reply; 29+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-06 19:20 UTC (permalink / raw)
To: Vijay Kumar Tumati, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 06/01/2026 20:18, Krzysztof Kozlowski wrote:
> On 06/01/2026 19:40, Vijay Kumar Tumati wrote:
>>
>> On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:
>>> On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
Look here^
>>>> + };
>>>> +
>>>> + cci0: cci@ac7b000 {
>>> Looks completely mis-ordered/sorted. What are the nodes above and below?
>> Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are
>> the pinctrl nodes. Each CCI has two masters using two GPIOs each, one
>
> Why would pinctrl nodes matter anyhow? Please read how DTS syntax works.
>
>> for clk and one for data. The ones below are the actual CCI HW nodes
>> that make use of the pinctrls. I believe this is inline with previous
>> generations. Have I missed something? Thanks.
> I wrote what is wrong. Is this maintaining proper sorting? Did you read
> DTS coding style?
>
Heh, you received my review 1 day after your posting.
You replied to my review 5-6 weeks after, yet you still expect me to
understand the context and provide clarifications.
There is simpler way: NAK.
You will not get your patches merged with such latency and such replies
not even trying to address the problem or learn about it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2026-01-06 19:20 ` Krzysztof Kozlowski
@ 2026-01-06 19:43 ` Vijay Kumar Tumati
0 siblings, 0 replies; 29+ messages in thread
From: Vijay Kumar Tumati @ 2026-01-06 19:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Hangxiang Ma
Cc: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Bryan O'Donoghue,
linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian
On 1/6/2026 11:20 AM, Krzysztof Kozlowski wrote:
> On 06/01/2026 20:18, Krzysztof Kozlowski wrote:
>> On 06/01/2026 19:40, Vijay Kumar Tumati wrote:
>>> On 11/27/2025 12:12 AM, Krzysztof Kozlowski wrote:
>>>> On Wed, Nov 26, 2025 at 01:38:40AM -0800, Hangxiang Ma wrote:
> Look here^
>
>>>>> + };
>>>>> +
>>>>> + cci0: cci@ac7b000 {
>>>> Looks completely mis-ordered/sorted. What are the nodes above and below?
>>> Hi Krzysztof, sorry, not sure how you mean exactly. The ones above are
>>> the pinctrl nodes. Each CCI has two masters using two GPIOs each, one
>> Why would pinctrl nodes matter anyhow? Please read how DTS syntax works.
>>
>>> for clk and one for data. The ones below are the actual CCI HW nodes
>>> that make use of the pinctrls. I believe this is inline with previous
>>> generations. Have I missed something? Thanks.
>> I wrote what is wrong. Is this maintaining proper sorting? Did you read
>> DTS coding style?
>>
>
> Heh, you received my review 1 day after your posting.
>
> You replied to my review 5-6 weeks after, yet you still expect me to
> understand the context and provide clarifications.
>
> There is simpler way: NAK.
>
> You will not get your patches merged with such latency and such replies
> not even trying to address the problem or learn about it.
Agreed. Apologies for the delay. It was partly caused by the dependency
that these patches have on Kaanapali patches and partly by vacations
during Christmas. We will explore and address your concerns reg CCI
nodes and push the next revision ASAP. Thanks for your understanding,
Krzysztof.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss
2025-11-26 9:38 ` [PATCH 7/7] arm64: dts: qcom: sm8750: Add support for camss Hangxiang Ma
2025-11-27 8:12 ` Krzysztof Kozlowski
@ 2025-11-27 10:06 ` Bryan O'Donoghue
1 sibling, 0 replies; 29+ messages in thread
From: Bryan O'Donoghue @ 2025-11-27 10:06 UTC (permalink / raw)
To: Hangxiang Ma, Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
jeyaprakash.soundrapandian, Vijay Kumar Tumati
On 26/11/2025 09:38, Hangxiang Ma wrote:
> Add support for the camera subsystem on the SM8750 Qualcomm SoC. This
> includes bringing up the CSIPHY, CSID, VFE/RDI interfaces. This change
> also introduces the necessary modules for enabling future extended
> functionalities.
>
> The SM8750 platform provides:
> - 3 x VFE, 5 RDI per VFE
> - 2 x VFE Lite, 4 RDI per VFE
> - 3 x CSID
> - 2 x CSID Lite
> - 6 x CSI PHY
> - 2 x ICP
> - 1 x IPE
> - 2 x JPEG DMA & Downscaler
> - 2 x JPEG Encoder
> - 1 x OFE
> - 5 x RT CDM
> - 3 x TPG
>
> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 599 +++++++++++++++++++++++++++++++++++
> 1 file changed, 599 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 1937b48fac5a..b83389c3456b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3332,6 +3332,605 @@ data-pins {
> bias-pull-up;
> };
> };
> +
> + cci0_0_default: cci0-0-default-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_0_sleep: cci0-0-sleep-state {
> + sda-pins {
> + pins = "gpio113";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio114";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci0_1_default: cci0-1-default-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci0_1_sleep: cci0-1-sleep-state {
> + sda-pins {
> + pins = "gpio115";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio116";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_0_default: cci1-0-default-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_0_sleep: cci1-0-sleep-state {
> + sda-pins {
> + pins = "gpio117";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio118";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci1_1_default: cci1-1-default-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci1_1_sleep: cci1-1-sleep-state {
> + sda-pins {
> + pins = "gpio111";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio164";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_0_default: cci2-0-default-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_0_sleep: cci2-0-sleep-state {
> + sda-pins {
> + pins = "gpio112";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio153";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> +
> + cci2_1_default: cci2-1-default-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> + cci2_1_sleep: cci2-1-sleep-state {
> + sda-pins {
> + pins = "gpio119";
> + function = "cci_i2c_sda";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + scl-pins {
> + pins = "gpio120";
> + function = "cci_i2c_scl";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> + };
> + };
> +
> + cci0: cci@ac7b000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7b000 0x0 0x1000>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@ac7c000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7c000 0x0 0x1000>;
> + interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci1_0_default &cci1_1_default>;
> + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci2: cci@ac7d000 {
> + compatible = "qcom,sm8750-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac7d000 0x0 0x1000>;
> + interrupts = <GIC_SPI 428 IRQ_TYPE_EDGE_RISING>;
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CCI_2_CLK>;
> + clock-names = "ahb", "cci";
> + pinctrl-0 = <&cci2_0_default &cci2_1_default>;
> + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
> + pinctrl-names = "default", "sleep";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cci2_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci2_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <400000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + camss: isp@ad27000 {
> + compatible = "qcom,sm8750-camss";
> +
> + reg = <0x0 0x0ad27000 0x0 0x2b00>,
> + <0x0 0x0ad2a000 0x0 0x2b00>,
> + <0x0 0x0ad2d000 0x0 0x2b00>,
> + <0x0 0x0ad6d000 0x0 0xa00>,
> + <0x0 0x0ad72000 0x0 0xa00>,
> + <0x0 0x0ada9000 0x0 0x2000>,
> + <0x0 0x0adab000 0x0 0x2000>,
> + <0x0 0x0adad000 0x0 0x2000>,
> + <0x0 0x0adaf000 0x0 0x2000>,
> + <0x0 0x0adb1000 0x0 0x2000>,
> + <0x0 0x0adb3000 0x0 0x2000>,
> + <0x0 0x0ac86000 0x0 0x10000>,
> + <0x0 0x0ac96000 0x0 0x10000>,
> + <0x0 0x0aca6000 0x0 0x10000>,
> + <0x0 0x0ad6e000 0x0 0x1800>,
> + <0x0 0x0ad73000 0x0 0x1800>,
> + <0x0 0x0ac06000 0x0 0x1000>,
> + <0x0 0x0ac05000 0x0 0x1000>,
> + <0x0 0x0ac16000 0x0 0x1000>,
> + <0x0 0x0ac15000 0x0 0x1000>,
> + <0x0 0x0ac42000 0x0 0x18000>,
> + <0x0 0x0ac26000 0x0 0x1000>,
> + <0x0 0x0ac25000 0x0 0x1000>,
> + <0x0 0x0ac28000 0x0 0x1000>,
> + <0x0 0x0ac27000 0x0 0x1000>,
> + <0x0 0x0ac2a000 0x0 0x18000>,
> + <0x0 0x0ac7f000 0x0 0x580>,
> + <0x0 0x0ac80000 0x0 0x580>,
> + <0x0 0x0ac81000 0x0 0x580>,
> + <0x0 0x0ac82000 0x0 0x580>,
> + <0x0 0x0ac83000 0x0 0x580>,
> + <0x0 0x0ad8b000 0x0 0x400>,
> + <0x0 0x0ad8c000 0x0 0x400>,
> + <0x0 0x0ad8d000 0x0 0x400>;
> + reg-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "icp0",
> + "icp0_sys",
> + "icp1",
> + "icp1_sys",
> + "ipe",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "ofe",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + clocks = <&camcc CAM_CC_CAMNOC_NRT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_AXI_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_CAMNOC_RT_IFE_LITE_CLK>,
> + <&camcc CAM_CC_CAM_TOP_AHB_CLK>,
> + <&camcc CAM_CC_CAM_TOP_FAST_AHB_CLK>,
> + <&camcc CAM_CC_CSID_CLK>,
> + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
> + <&camcc CAM_CC_CSIPHY0_CLK>,
> + <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY1_CLK>,
> + <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY2_CLK>,
> + <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY3_CLK>,
> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY4_CLK>,
> + <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
> + <&camcc CAM_CC_CSIPHY5_CLK>,
> + <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
> + <&gcc GCC_CAMERA_HF_AXI_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_0_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_1_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_CLK>,
> + <&camcc CAM_CC_TFE_2_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CLK>,
> + <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
> + <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
> + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
> + <&camcc CAM_CC_CAMNOC_NRT_IPE_NPS_CLK>,
> + <&camcc CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK>,
> + <&gcc GCC_CAMERA_SF_AXI_CLK>,
> + <&camcc CAM_CC_ICP_0_CLK>,
> + <&camcc CAM_CC_ICP_0_AHB_CLK>,
> + <&camcc CAM_CC_ICP_1_CLK>,
> + <&camcc CAM_CC_ICP_1_AHB_CLK>,
> + <&camcc CAM_CC_IPE_NPS_CLK>,
> + <&camcc CAM_CC_IPE_NPS_AHB_CLK>,
> + <&camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_IPE_PPS_CLK>,
> + <&camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>,
> + <&camcc CAM_CC_JPEG_0_CLK>,
> + <&camcc CAM_CC_JPEG_1_CLK>,
> + <&camcc CAM_CC_OFE_AHB_CLK>,
> + <&camcc CAM_CC_OFE_ANCHOR_CLK>,
> + <&camcc CAM_CC_OFE_ANCHOR_FAST_AHB_CLK>,
> + <&camcc CAM_CC_OFE_HDR_CLK>,
> + <&camcc CAM_CC_OFE_HDR_FAST_AHB_CLK>,
> + <&camcc CAM_CC_OFE_MAIN_CLK>,
> + <&camcc CAM_CC_OFE_MAIN_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_0_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_0_BAYER_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_1_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_1_BAYER_FAST_AHB_CLK>,
> + <&camcc CAM_CC_TFE_2_BAYER_CLK>,
> + <&camcc CAM_CC_TFE_2_BAYER_FAST_AHB_CLK>;
> + clock-names = "camnoc_nrt_axi",
> + "camnoc_rt_axi",
> + "camnoc_rt_vfe0",
> + "camnoc_rt_vfe1",
> + "camnoc_rt_vfe2",
> + "camnoc_rt_vfe_lite",
> + "cam_top_ahb",
> + "cam_top_fast_ahb",
> + "csid",
> + "csid_csiphy_rx",
> + "csiphy0",
> + "csiphy0_timer",
> + "csiphy1",
> + "csiphy1_timer",
> + "csiphy2",
> + "csiphy2_timer",
> + "csiphy3",
> + "csiphy3_timer",
> + "csiphy4",
> + "csiphy4_timer",
> + "csiphy5",
> + "csiphy5_timer",
> + "gcc_hf_axi",
> + "vfe0",
> + "vfe0_fast_ahb",
> + "vfe1",
> + "vfe1_fast_ahb",
> + "vfe2",
> + "vfe2_fast_ahb",
> + "vfe_lite",
> + "vfe_lite_ahb",
> + "vfe_lite_cphy_rx",
> + "vfe_lite_csid",
> + "qdss_debug_xo",
> + "camnoc_ipe_nps",
> + "camnoc_ofe",
> + "gcc_sf_axi",
> + "icp0",
> + "icp0_ahb",
> + "icp1",
> + "icp1_ahb",
> + "ipe_nps",
> + "ipe_nps_ahb",
> + "ipe_nps_fast_ahb",
> + "ipe_pps",
> + "ipe_pps_fast_ahb",
> + "jpeg0",
> + "jpeg1",
> + "ofe_ahb",
> + "ofe_anchor",
> + "ofe_anchor_fast_ahb",
> + "ofe_hdr",
> + "ofe_hdr_fast_ahb",
> + "ofe_main",
> + "ofe_main_fast_ahb",
> + "vfe0_bayer",
> + "vfe0_bayer_fast_ahb",
> + "vfe1_bayer",
> + "vfe1_bayer_fast_ahb",
> + "vfe2_bayer",
> + "vfe2_bayer_fast_ahb";
> +
> + interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 457 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 657 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 664 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 702 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "csid0",
> + "csid1",
> + "csid2",
> + "csid_lite0",
> + "csid_lite1",
> + "csiphy0",
> + "csiphy1",
> + "csiphy2",
> + "csiphy3",
> + "csiphy4",
> + "csiphy5",
> + "vfe0",
> + "vfe1",
> + "vfe2",
> + "vfe_lite0",
> + "vfe_lite1",
> + "camnoc_nrt",
> + "camnoc_rt",
> + "icp0",
> + "icp1",
> + "jpeg_dma0",
> + "jpeg_enc0",
> + "jpeg_dma1",
> + "jpeg_enc1",
> + "rt_cdm0",
> + "rt_cdm1",
> + "rt_cdm2",
> + "rt_cdm3",
> + "rt_cdm4",
> + "tpg0",
> + "tpg1",
> + "tpg2";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_NRT_ICP_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "ahb",
> + "hf_mnoc",
> + "sf_icp_mnoc",
> + "sf_mnoc";
> +
> + iommus = <&apps_smmu 0x1c00 0x00>,
> + <&apps_smmu 0x18c0 0x00>,
> + <&apps_smmu 0x1980 0x00>,
> + <&apps_smmu 0x1840 0x00>,
> + <&apps_smmu 0x1800 0x00>,
> + <&apps_smmu 0x18a0 0x00>,
> + <&apps_smmu 0x1880 0x00>,
> + <&apps_smmu 0x1820 0x00>,
> + <&apps_smmu 0x1860 0x00>;
> +
> + power-domains = <&camcc CAM_CC_TFE_0_GDSC>,
> + <&camcc CAM_CC_TFE_1_GDSC>,
> + <&camcc CAM_CC_TFE_2_GDSC>,
> + <&camcc CAM_CC_TITAN_TOP_GDSC>,
> + <&camcc CAM_CC_IPE_0_GDSC>,
> + <&camcc CAM_CC_OFE_GDSC>;
> + power-domain-names = "vfe0",
> + "vfe1",
> + "vfe2",
> + "top",
> + "ipe",
> + "ofe";
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + };
> + };
> +
> };
>
> tcsrcc: clock-controller@f204008 {
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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