From: paul-pl.chen <paul-pl.chen@mediatek.com>
To: <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<chunkuang.hu@kernel.org>,
<angelogioacchino.delregno@collabora.com>
Cc: devicetree@vger.kernel.org, xiandong.wang@mediatek.com,
jason-jh.lin@mediatek.com, singo.chang@mediatek.com,
treapking@chromium.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
Project_Global_Chrome_Upstream_Group@mediatek.com,
paul-pl.chen@mediatek.com, nancy.lin@mediatek.com,
linux-mediatek@lists.infradead.org, sunny.shen@mediatek.com,
p.zabel@pengutronix.de, sirius.wang@mediatek.com,
matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 09/17] soc: mediatek: mutex: add mutex support for MT8196
Date: Thu, 15 May 2025 17:34:21 +0800 [thread overview]
Message-ID: <20250515093454.1729720-10-paul-pl.chen@mediatek.com> (raw)
In-Reply-To: <20250515093454.1729720-1-paul-pl.chen@mediatek.com>
From: Nancy Lin <nancy.lin@mediatek.com>
Add mutex support for the main and external displays in MT8196:
- Introduce a new DVO0 output component for the new mutex
settings of MT8196.
- Add a need_sof_mof flag to configure both SOF and MOD settings
for the output component.
Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 140 ++++++++++++++++++++++++++++++-
1 file changed, 138 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index b2a9992fb232..183f3abcd7dd 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -19,6 +19,7 @@
#define MT2701_MUTEX0_SOF0 0x30
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8196_MUTEX0_MOD0 0x34
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
@@ -237,6 +238,47 @@
#define MT8195_MUTEX_MOD_MDP_WROT2 32
#define MT8195_MUTEX_MOD_MDP_WROT3 33
+/* OVLSYS */
+#define MT8196_MUTEX_MOD0_OVL_EXDMA2 2
+#define MT8196_MUTEX_MOD0_OVL_EXDMA3 3
+#define MT8196_MUTEX_MOD0_OVL_EXDMA4 4
+#define MT8196_MUTEX_MOD0_OVL_EXDMA5 5
+#define MT8196_MUTEX_MOD0_OVL_EXDMA6 6
+#define MT8196_MUTEX_MOD0_OVL_EXDMA7 7
+#define MT8196_MUTEX_MOD0_OVL_EXDMA8 8
+#define MT8196_MUTEX_MOD0_OVL_EXDMA9 9
+#define MT8196_MUTEX_MOD0_OVL_BLENDER1 11
+#define MT8196_MUTEX_MOD0_OVL_BLENDER2 12
+#define MT8196_MUTEX_MOD0_OVL_BLENDER3 13
+#define MT8196_MUTEX_MOD0_OVL_BLENDER4 14
+#define MT8196_MUTEX_MOD0_OVL_BLENDER5 15
+#define MT8196_MUTEX_MOD0_OVL_BLENDER6 16
+#define MT8196_MUTEX_MOD0_OVL_BLENDER7 17
+#define MT8196_MUTEX_MOD0_OVL_BLENDER8 18
+#define MT8196_MUTEX_MOD0_OVL_BLENDER9 19
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC0 20
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC1 21
+#define MT8196_MUTEX_MOD0_OVL_OUTPROC2 22
+#define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5 (32 + 16)
+#define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6 (32 + 17)
+
+/* DISP0 */
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0 16
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1 17
+#define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8 24
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC1 (32 + 1)
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2 (32 + 2)
+#define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3 (32 + 3)
+
+/* DISP1 */
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21 1
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22 2
+#define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC23 3
+#define MT8196_MUTEX_MOD0_DISP1_DP_INTF0 13
+#define MT8196_MUTEX_MOD0_DISP1_DP_INTF1 14
+#define MT8196_MUTEX_MOD0_DISP1_DSI0 23
+#define MT8196_MUTEX_MOD0_DISP1_DVO 29
+
#define MT8365_MUTEX_MOD_DISP_OVL0 7
#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
#define MT8365_MUTEX_MOD_DISP_RDMA0 9
@@ -297,6 +339,12 @@
#define MT8195_MUTEX_SOF_DP_INTF1 4
#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
+#define MT8196_MUTEX_SOF_DSI0 1
+#define MT8196_MUTEX_SOF_DSI1 2
+#define MT8196_MUTEX_SOF_DSI2 4
+#define MT8196_MUTEX_SOF_DPI0 5
+#define MT8196_MUTEX_SOF_DPI1 6
+#define MT8196_MUTEX_SOF_DVO0 7
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
@@ -310,6 +358,12 @@
#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
+#define MT8196_MUTEX_EOF_DSI0 (MT8196_MUTEX_SOF_DSI0 << 7)
+#define MT8196_MUTEX_EOF_DSI1 (MT8196_MUTEX_SOF_DSI1 << 7)
+#define MT8196_MUTEX_EOF_DSI2 (MT8196_MUTEX_SOF_DSI2 << 7)
+#define MT8196_MUTEX_EOF_DPI0 (MT8196_MUTEX_SOF_DPI0 << 7)
+#define MT8196_MUTEX_EOF_DPI1 (MT8196_MUTEX_SOF_DPI1 << 7)
+#define MT8196_MUTEX_EOF_DVO0 (MT8196_MUTEX_SOF_DVO0 << 7)
struct mtk_mutex {
u8 id;
@@ -326,6 +380,7 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DSI3,
MUTEX_SOF_DP_INTF0,
MUTEX_SOF_DP_INTF1,
+ MUTEX_SOF_DVO0,
DDP_MUTEX_SOF_MAX,
};
@@ -336,6 +391,7 @@ struct mtk_mutex_data {
const u16 mutex_mod_reg;
const u16 mutex_sof_reg;
const bool no_clk;
+ const bool need_sof_mod;
};
struct mtk_mutex_ctx {
@@ -625,6 +681,64 @@ static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
[MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3,
};
+static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
+ [DDP_COMPONENT_OVL0_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
+ [DDP_COMPONENT_OVL0_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
+ [DDP_COMPONENT_OVL0_EXDMA5] = MT8196_MUTEX_MOD0_OVL_EXDMA5,
+ [DDP_COMPONENT_OVL0_EXDMA6] = MT8196_MUTEX_MOD0_OVL_EXDMA6,
+ [DDP_COMPONENT_OVL0_EXDMA7] = MT8196_MUTEX_MOD0_OVL_EXDMA7,
+ [DDP_COMPONENT_OVL0_EXDMA8] = MT8196_MUTEX_MOD0_OVL_EXDMA8,
+ [DDP_COMPONENT_OVL0_EXDMA9] = MT8196_MUTEX_MOD0_OVL_EXDMA9,
+ [DDP_COMPONENT_OVL0_BLENDER1] = MT8196_MUTEX_MOD0_OVL_BLENDER1,
+ [DDP_COMPONENT_OVL0_BLENDER2] = MT8196_MUTEX_MOD0_OVL_BLENDER2,
+ [DDP_COMPONENT_OVL0_BLENDER3] = MT8196_MUTEX_MOD0_OVL_BLENDER3,
+ [DDP_COMPONENT_OVL0_BLENDER4] = MT8196_MUTEX_MOD0_OVL_BLENDER4,
+ [DDP_COMPONENT_OVL0_BLENDER5] = MT8196_MUTEX_MOD0_OVL_BLENDER5,
+ [DDP_COMPONENT_OVL0_BLENDER6] = MT8196_MUTEX_MOD0_OVL_BLENDER6,
+ [DDP_COMPONENT_OVL0_BLENDER7] = MT8196_MUTEX_MOD0_OVL_BLENDER7,
+ [DDP_COMPONENT_OVL0_BLENDER8] = MT8196_MUTEX_MOD0_OVL_BLENDER8,
+ [DDP_COMPONENT_OVL0_BLENDER9] = MT8196_MUTEX_MOD0_OVL_BLENDER9,
+ [DDP_COMPONENT_OVL0_OUTPROC0] = MT8196_MUTEX_MOD0_OVL_OUTPROC0,
+ [DDP_COMPONENT_OVL0_OUTPROC1] = MT8196_MUTEX_MOD0_OVL_OUTPROC1,
+ [DDP_COMPONENT_OVL0_DLO_ASYNC5] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5,
+ [DDP_COMPONENT_OVL0_DLO_ASYNC6] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6,
+ [DDP_COMPONENT_OVL1_EXDMA2] = MT8196_MUTEX_MOD0_OVL_EXDMA2,
+ [DDP_COMPONENT_OVL1_EXDMA3] = MT8196_MUTEX_MOD0_OVL_EXDMA3,
+ [DDP_COMPONENT_OVL1_EXDMA4] = MT8196_MUTEX_MOD0_OVL_EXDMA4,
+ [DDP_COMPONENT_OVL1_EXDMA5] = MT8196_MUTEX_MOD0_OVL_EXDMA5,
+ [DDP_COMPONENT_OVL1_EXDMA6] = MT8196_MUTEX_MOD0_OVL_EXDMA6,
+ [DDP_COMPONENT_OVL1_EXDMA7] = MT8196_MUTEX_MOD0_OVL_EXDMA7,
+ [DDP_COMPONENT_OVL1_EXDMA8] = MT8196_MUTEX_MOD0_OVL_EXDMA8,
+ [DDP_COMPONENT_OVL1_EXDMA9] = MT8196_MUTEX_MOD0_OVL_EXDMA9,
+ [DDP_COMPONENT_OVL1_BLENDER1] = MT8196_MUTEX_MOD0_OVL_BLENDER1,
+ [DDP_COMPONENT_OVL1_BLENDER2] = MT8196_MUTEX_MOD0_OVL_BLENDER2,
+ [DDP_COMPONENT_OVL1_BLENDER3] = MT8196_MUTEX_MOD0_OVL_BLENDER3,
+ [DDP_COMPONENT_OVL1_BLENDER4] = MT8196_MUTEX_MOD0_OVL_BLENDER4,
+ [DDP_COMPONENT_OVL1_BLENDER5] = MT8196_MUTEX_MOD0_OVL_BLENDER5,
+ [DDP_COMPONENT_OVL1_BLENDER6] = MT8196_MUTEX_MOD0_OVL_BLENDER6,
+ [DDP_COMPONENT_OVL1_BLENDER7] = MT8196_MUTEX_MOD0_OVL_BLENDER7,
+ [DDP_COMPONENT_OVL1_BLENDER8] = MT8196_MUTEX_MOD0_OVL_BLENDER8,
+ [DDP_COMPONENT_OVL1_BLENDER9] = MT8196_MUTEX_MOD0_OVL_BLENDER9,
+ [DDP_COMPONENT_OVL1_OUTPROC0] = MT8196_MUTEX_MOD0_OVL_OUTPROC0,
+ [DDP_COMPONENT_OVL1_OUTPROC1] = MT8196_MUTEX_MOD0_OVL_OUTPROC1,
+ [DDP_COMPONENT_OVL1_DLO_ASYNC5] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC5,
+ [DDP_COMPONENT_OVL1_DLO_ASYNC6] = MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6,
+ [DDP_COMPONENT_DLI_ASYNC0] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0,
+ [DDP_COMPONENT_DLI_ASYNC1] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1,
+ [DDP_COMPONENT_DLI_ASYNC8] = MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8,
+ [DDP_COMPONENT_DLO_ASYNC1] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC1,
+ [DDP_COMPONENT_DLO_ASYNC2] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2,
+ [DDP_COMPONENT_DLO_ASYNC3] = MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3,
+ [DDP_COMPONENT_DLI_ASYNC21] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21,
+ [DDP_COMPONENT_DLI_ASYNC22] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22,
+ [DDP_COMPONENT_DLI_ASYNC23] = MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC23,
+ [DDP_COMPONENT_DVO0] = MT8196_MUTEX_MOD0_DISP1_DVO,
+ [DDP_COMPONENT_DP_INTF0] = MT8196_MUTEX_MOD0_DISP1_DP_INTF0,
+ [DDP_COMPONENT_DP_INTF1] = MT8196_MUTEX_MOD0_DISP1_DP_INTF1,
+ [DDP_COMPONENT_DSI0] = MT8196_MUTEX_MOD0_DISP1_DSI0,
+};
+
static const u8 mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
@@ -710,6 +824,17 @@ static const u16 mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
};
+static const u16 mt8196_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8196_MUTEX_SOF_DSI0 | MT8196_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8196_MUTEX_SOF_DSI1 | MT8196_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8196_MUTEX_SOF_DPI0 | MT8196_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8196_MUTEX_SOF_DPI1 | MT8196_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DVO0] = MT8196_MUTEX_SOF_DVO0 | MT8196_MUTEX_EOF_DVO0,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -803,6 +928,14 @@ static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = {
.mutex_table_mod = mt8195_mutex_table_mod,
};
+static const struct mtk_mutex_data mt8196_mutex_driver_data = {
+ .mutex_mod = mt8196_mutex_mod,
+ .mutex_sof = mt8196_mutex_sof,
+ .mutex_mod_reg = MT8196_MUTEX0_MOD0,
+ .mutex_sof_reg = MT2701_MUTEX0_SOF0,
+ .need_sof_mod = true,
+};
+
static const struct mtk_mutex_data mt8365_mutex_driver_data = {
.mutex_mod = mt8365_mutex_mod,
.mutex_sof = mt8183_mutex_sof,
@@ -872,6 +1005,8 @@ static int mtk_mutex_get_output_comp_sof(enum mtk_ddp_comp_id id)
return MUTEX_SOF_DP_INTF0;
case DDP_COMPONENT_DP_INTF1:
return MUTEX_SOF_DP_INTF1;
+ case DDP_COMPONENT_DVO0:
+ return MUTEX_SOF_DVO0;
default:
break;
}
@@ -929,7 +1064,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
WARN_ON(&mtx->mutex[mutex->id] != mutex);
- if (!is_output_comp) {
+ if (!is_output_comp || mtx->data->need_sof_mod) {
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
@@ -960,7 +1095,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
WARN_ON(&mtx->mutex[mutex->id] != mutex);
- if (!is_output_comp) {
+ if (!is_output_comp || mtx->data->need_sof_mod) {
if (mtx->data->mutex_mod[id] < 32) {
offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
mutex->id);
@@ -1169,6 +1304,7 @@ static const struct of_device_id mutex_driver_dt_match[] = {
{ .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data },
{ .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data },
{ .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data },
+ { .compatible = "mediatek,mt8196-disp-mutex", .data = &mt8196_mutex_driver_data },
{ .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data },
{ /* sentinel */ },
};
--
2.45.2
next prev parent reply other threads:[~2025-05-15 10:20 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-15 9:34 [PATCH v3 00/17] Add MediaTek SoC DRM support for MT8196 paul-pl.chen
2025-05-15 9:34 ` [PATCH v3 01/17] dt-bindings: soc: mediatek: add mutex yaml " paul-pl.chen
2025-05-15 9:34 ` [PATCH v3 02/17] dt-bindings: display: mediatek: add EXDMA " paul-pl.chen
2025-05-15 10:48 ` Rob Herring (Arm)
2025-06-26 9:10 ` CK Hu (胡俊光)
2025-05-15 9:34 ` [PATCH v3 03/17] dt-bindings: display: mediatek: add BLENDER " paul-pl.chen
2025-05-19 6:41 ` Krzysztof Kozlowski
2025-05-15 9:34 ` [PATCH v3 04/17] dt-bindings: display: mediatek: add OUTPROC " paul-pl.chen
2025-05-19 6:43 ` Krzysztof Kozlowski
2025-05-15 9:34 ` [PATCH v3 05/17] soc: mediatek: Add runtime PM and top clocks and async controls for MMSYS paul-pl.chen
2025-05-15 9:34 ` [PATCH v3 06/17] soc: mediatek: add mmsys support for MT8196 paul-pl.chen
2025-05-15 9:34 ` [PATCH v3 07/17] soc: mediatek: mutex: Reused the switch case for SOF ID paul-pl.chen
2025-05-15 9:34 ` [PATCH v3 08/17] soc: mediatek: mutex: refactor SOF settings for output components paul-pl.chen
2025-05-15 9:34 ` paul-pl.chen [this message]
2025-05-15 9:34 ` [PATCH v3 10/17] drm/mediatek: Export OVL formats definitions and format conversion API paul-pl.chen
2025-06-17 5:43 ` CK Hu (胡俊光)
2025-06-17 6:47 ` CK Hu (胡俊光)
2025-05-15 9:34 ` [PATCH v3 11/17] drm/mediatek: drm/mediatek: Export OVL ignore pixel alpha function paul-pl.chen
2025-06-17 6:06 ` CK Hu (胡俊光)
2025-05-15 9:34 ` [PATCH v3 12/17] drm/mediatek: add EXDMA support for MT8196 paul-pl.chen
2025-06-17 9:17 ` CK Hu (胡俊光)
2025-07-04 6:26 ` Paul-pl Chen (陳柏霖)
2025-05-15 9:34 ` [PATCH v3 13/17] drm/mediatek: add BLENDER " paul-pl.chen
2025-06-18 6:40 ` CK Hu (胡俊光)
2025-07-04 6:36 ` Paul-pl Chen (陳柏霖)
2025-05-15 9:34 ` [PATCH v3 14/17] drm/mediatek: add OUTPROC " paul-pl.chen
2025-06-18 8:23 ` CK Hu (胡俊光)
2025-07-04 7:24 ` Paul-pl Chen (陳柏霖)
2025-05-15 9:34 ` [PATCH v3 15/17] drm/mediatek: add ovlsys_adaptor " paul-pl.chen
2025-05-16 6:34 ` kernel test robot
2025-06-24 5:46 ` CK Hu (胡俊光)
2025-05-15 9:34 ` [PATCH v3 16/17] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver paul-pl.chen
2025-05-16 7:36 ` kernel test robot
2025-06-24 5:49 ` CK Hu (胡俊光)
2025-05-15 9:34 ` [PATCH v3 17/17] drm/mediatek: Add support for MT8196 multiple mmsys paul-pl.chen
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