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From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"Xiandong Wang (王先冬)" <Xiandong.Wang@mediatek.com>,
	"Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>,
	"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@mediatek.com>,
	"treapking@chromium.org" <treapking@chromium.org>,
	"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
	"linux-mediatek@lists.infradead.org"
	<linux-mediatek@lists.infradead.org>,
	"Sunny Shen (沈姍姍)" <Sunny.Shen@mediatek.com>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
	"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v3 13/17] drm/mediatek: add BLENDER support for MT8196
Date: Wed, 18 Jun 2025 06:40:51 +0000	[thread overview]
Message-ID: <6b561f320d4e614f37d065f5769759bef5f08632.camel@mediatek.com> (raw)
In-Reply-To: <20250515093454.1729720-14-paul-pl.chen@mediatek.com>

On Thu, 2025-05-15 at 17:34 +0800, paul-pl.chen wrote:
> From: Paul-pl Chen <paul-pl.chen@mediatek.com>
> 
> BLENDER executes the alpha blending function for overlapping
> layers from different sources, which is the primary function
> of the overlapping system.
> 
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---

[snip]

> +++ b/drivers/gpu/drm/mediatek/mtk_disp_blender.c
> @@ -0,0 +1,264 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + */
> +
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_blend.h>
> +#include <drm/drm_framebuffer.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "mtk_crtc.h"
> +#include "mtk_ddp_comp.h"
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_drv.h"

alphabetic order.

> +#include "mtk_disp_blender.h"
> +#include "mtk_disp_ovl.h"
> +
> 

[snip]

> +
> +void mtk_disp_blender_config(struct device *dev, unsigned int w,
> +			     unsigned int h, unsigned int vrefresh,
> +			     unsigned int bpc, bool most_top,

vrefresh and bpc is useless, so drop them.

> +			     bool most_bottom, struct cmdq_pkt *cmdq_pkt)
> +{
> +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> +	u32 datapath;
> +
> +	dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
> +	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_OVL_BLD_ROI_SIZE);
> +	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_OVL_BLD_BGCLR_CLR);
> +
> +	/*
> +	 * The input source of blender layer can be EXDMA layer output or
> +	 * the blender constant layer itself.
> +	 * This color setting is configured for the blender constant layer.
> +	 */
> +	mtk_ddp_write(cmdq_pkt, DISP_REG_OVL_BLD_BGCLR_BALCK, &priv->cmdq_reg, priv->regs,
> +		      DISP_REG_OVL_BLD_L0_CLR);
> +
> +	if (most_top)
> +		datapath = OVL_BLD_BGCLR_OUT_TO_PROC;
> +	else
> +		datapath = OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER;
> +	/*
> +	 * The primary input is from EXDMA and the second input
> +	 * is optionally from another blender
> +	 */
> +	if (!most_bottom)
> +		datapath |= OVL_BLD_BGCLR_IN_SEL;
> +
> +	mtk_ddp_write_mask(cmdq_pkt, datapath,
> +			   &priv->cmdq_reg, priv->regs, DISP_REG_OVL_BLD_DATAPATH_CON,
> +			   OVL_BLD_BGCLR_OUT_TO_PROC | OVL_BLD_BGCLR_OUT_TO_NEXT_LAYER |
> +			   OVL_BLD_BGCLR_IN_SEL);
> +}
> +
> +void mtk_disp_blender_start(struct device *dev, struct cmdq_pkt *cmdq_pkt)

Drop cmdq_pkt.

> +{
> +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_BYPASS_SHADOW, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_BLD_SHADOW_CTRL, OVL_BLD_BYPASS_SHADOW);
> +	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_EN, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
> +}
> +
> +void mtk_disp_blender_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt)

Drop cmdq_pkt.

Regards,
CK

> +{
> +	struct mtk_disp_blender *priv = dev_get_drvdata(dev);
> +
> +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_BLD_EN, OVL_BLD_EN);
> +
> +	mtk_ddp_write_mask(cmdq_pkt, OVL_BLD_RST, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
> +	mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> +			   DISP_REG_OVL_BLD_RST, OVL_BLD_RST);
> +}
> +


  reply	other threads:[~2025-06-18  7:46 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15  9:34 [PATCH v3 00/17] Add MediaTek SoC DRM support for MT8196 paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 01/17] dt-bindings: soc: mediatek: add mutex yaml " paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 02/17] dt-bindings: display: mediatek: add EXDMA " paul-pl.chen
2025-05-15 10:48   ` Rob Herring (Arm)
2025-06-26  9:10   ` CK Hu (胡俊光)
2025-05-15  9:34 ` [PATCH v3 03/17] dt-bindings: display: mediatek: add BLENDER " paul-pl.chen
2025-05-19  6:41   ` Krzysztof Kozlowski
2025-05-15  9:34 ` [PATCH v3 04/17] dt-bindings: display: mediatek: add OUTPROC " paul-pl.chen
2025-05-19  6:43   ` Krzysztof Kozlowski
2025-05-15  9:34 ` [PATCH v3 05/17] soc: mediatek: Add runtime PM and top clocks and async controls for MMSYS paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 06/17] soc: mediatek: add mmsys support for MT8196 paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 07/17] soc: mediatek: mutex: Reused the switch case for SOF ID paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 08/17] soc: mediatek: mutex: refactor SOF settings for output components paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 09/17] soc: mediatek: mutex: add mutex support for MT8196 paul-pl.chen
2025-05-15  9:34 ` [PATCH v3 10/17] drm/mediatek: Export OVL formats definitions and format conversion API paul-pl.chen
2025-06-17  5:43   ` CK Hu (胡俊光)
2025-06-17  6:47     ` CK Hu (胡俊光)
2025-05-15  9:34 ` [PATCH v3 11/17] drm/mediatek: drm/mediatek: Export OVL ignore pixel alpha function paul-pl.chen
2025-06-17  6:06   ` CK Hu (胡俊光)
2025-05-15  9:34 ` [PATCH v3 12/17] drm/mediatek: add EXDMA support for MT8196 paul-pl.chen
2025-06-17  9:17   ` CK Hu (胡俊光)
2025-07-04  6:26     ` Paul-pl Chen (陳柏霖)
2025-05-15  9:34 ` [PATCH v3 13/17] drm/mediatek: add BLENDER " paul-pl.chen
2025-06-18  6:40   ` CK Hu (胡俊光) [this message]
2025-07-04  6:36     ` Paul-pl Chen (陳柏霖)
2025-05-15  9:34 ` [PATCH v3 14/17] drm/mediatek: add OUTPROC " paul-pl.chen
2025-06-18  8:23   ` CK Hu (胡俊光)
2025-07-04  7:24     ` Paul-pl Chen (陳柏霖)
2025-05-15  9:34 ` [PATCH v3 15/17] drm/mediatek: add ovlsys_adaptor " paul-pl.chen
2025-05-16  6:34   ` kernel test robot
2025-06-24  5:46   ` CK Hu (胡俊光)
2025-05-15  9:34 ` [PATCH v3 16/17] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver paul-pl.chen
2025-05-16  7:36   ` kernel test robot
2025-06-24  5:49   ` CK Hu (胡俊光)
2025-05-15  9:34 ` [PATCH v3 17/17] drm/mediatek: Add support for MT8196 multiple mmsys paul-pl.chen

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