Re: [PATCH v7 6/6] mailbox: Add support for i.MX7D messaging unit

Re: [PATCH v7 6/6] mailbox: Add support for i.MX7D messaging unit

[Oleksij Rempel]

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On 26.07.2018 12:15, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
> <o.rempel@pengutronix.de> wrote:
> 
> .....
> 
>> +
>> +/* Control Register */
>> +#define IMX_MU_xCR             0x24
>> +/* Transmit Interrupt Enable */
>> +#define IMX_MU_xCR_TIEn(x)     BIT(20 + (3 - (x)))
>> +/* Receive Interrupt Enable */
>> +#define IMX_MU_xCR_RIEn(x)     BIT(24 + (3 - (x)))
>> +
>> +#define IMX_MU_CHANS   4u
>> +
> The 'u' unnecessarily refreshes my knowledge of C  :)

ok

> 
>> +struct imx_mu_con_priv {
>> +       int                     irq;
>> +       unsigned int            idx;
>> +       char                    *irq_desc;
>>
> Having      char  irq_desc[16];    seems simpler than free/kfree upon
> each startup/shutdown. Simply use snprintf() in probe().

Currently all known configurations use one or two channels. I don't see
any sense to allocate all at the probe.


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Re: [PATCH v7 6/6] mailbox: Add support for i.MX7D messaging unit

[Jassi Brar]

On Thu, Jul 26, 2018 at 4:21 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:

>>
>>> +struct imx_mu_con_priv {
>>> +       int                     irq;
>>> +       unsigned int            idx;
>>> +       char                    *irq_desc;
>>>
>> Having      char  irq_desc[16];    seems simpler than free/kfree upon
>> each startup/shutdown. Simply use snprintf() in probe().
>
> Currently all known configurations use one or two channels. I don't see
> any sense to allocate all at the probe.
>
Just because only 2 out of 4 channels are being used, it doesn't make sense?

What is the concern?  "wasting" 16x2 bytes of memory?  How many bytes,
LOC and execution time does kasprintf() waste?

Re: [PATCH v7 6/6] mailbox: Add support for i.MX7D messaging unit

[Oleksij Rempel]

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On 26.07.2018 13:09, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 4:21 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> 
>>>
>>>> +struct imx_mu_con_priv {
>>>> +       int                     irq;
>>>> +       unsigned int            idx;
>>>> +       char                    *irq_desc;
>>>>
>>> Having      char  irq_desc[16];    seems simpler than free/kfree upon
>>> each startup/shutdown. Simply use snprintf() in probe().
>>
>> Currently all known configurations use one or two channels. I don't see
>> any sense to allocate all at the probe.
>>
> Just because only 2 out of 4 channels are being used, it doesn't make sense?
> 
> What is the concern?  "wasting" 16x2 bytes of memory?  How many bytes,
> LOC and execution time does kasprintf() waste?

Startup or shutdown is not speed critical path in this driver, or do i
miss some thing? Speed vs size is not valid argumentation here.


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Re: [PATCH v7 6/6] mailbox: Add support for i.MX7D messaging unit

[Jassi Brar]

On Thu, Jul 26, 2018 at 5:12 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>
>
> On 26.07.2018 13:09, Jassi Brar wrote:
>> On Thu, Jul 26, 2018 at 4:21 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>>
>>>>
>>>>> +struct imx_mu_con_priv {
>>>>> +       int                     irq;
>>>>> +       unsigned int            idx;
>>>>> +       char                    *irq_desc;
>>>>>
>>>> Having      char  irq_desc[16];    seems simpler than free/kfree upon
>>>> each startup/shutdown. Simply use snprintf() in probe().
>>>
>>> Currently all known configurations use one or two channels. I don't see
>>> any sense to allocate all at the probe.
>>>
>> Just because only 2 out of 4 channels are being used, it doesn't make sense?
>>
>> What is the concern?  "wasting" 16x2 bytes of memory?  How many bytes,
>> LOC and execution time does kasprintf() waste?
>
> Startup or shutdown is not speed critical path in this driver, or do i
> miss some thing?
>
No they are not.

> Speed vs size is not valid argumentation here.
>
If the code looks cleaner and smaller and lesser expensive execution
wise, at least I see that as a valid enough argument.

But OK, if you insist.  If someone sends a "cleanup" patch tomorrow, I
am going to thank and apply.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Oleksij Rempel]

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On 26.07.2018 11:49, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
> <o.rempel@pengutronix.de> wrote:
> 
>> Each MU has four pairs of rx/tx data register with four rx/tx interrupts
>> which can also be used as a separate channel.
>>
> So the hardware actually supports 4 channels.
> 
>> -- #mbox-cells:  Must be 0. Number of cells in a mailbox
>> +- #mbox-cells:  Must be:
>> +               0 - for single channel mode. i.MX8* SCU protocol specific.
>> +               1 - for multichannel (generic) mode.
>> +
> No, please.
> DT bindings should reflect the real hardware, and not the software
> mode we want the driver to work in.
> Please define mbox-cells=1  and have the i.MX8* platform always ask
> for channel-0.

We spend already some week to publicly talk about this..
The problem is, imx8 has multiple MUs, only some of them communicate
directly with SCU. SCU has some well defined protocol and
MU should be used and configured in some SCU specific way. From NXP
perspective, SCU firmware should not be replaceable and from Linux side
seen as part of the HW.

@Dong, is it correct description?


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Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Thu, Jul 26, 2018 at 4:27 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>
>
> On 26.07.2018 11:49, Jassi Brar wrote:
>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>> <o.rempel@pengutronix.de> wrote:
>>
>>> Each MU has four pairs of rx/tx data register with four rx/tx interrupts
>>> which can also be used as a separate channel.
>>>
>> So the hardware actually supports 4 channels.
>>
>>> -- #mbox-cells:  Must be 0. Number of cells in a mailbox
>>> +- #mbox-cells:  Must be:
>>> +               0 - for single channel mode. i.MX8* SCU protocol specific.
>>> +               1 - for multichannel (generic) mode.
>>> +
>> No, please.
>> DT bindings should reflect the real hardware, and not the software
>> mode we want the driver to work in.
>> Please define mbox-cells=1  and have the i.MX8* platform always ask
>> for channel-0.
>
> We spend already some week to publicly talk about this..
>
You should have kept me in the loop.
I know, I am not that important, but for the sake of the protocol you
should have CC'ed the mailbox maintainer :)

> The problem is, imx8 has multiple MUs
>
You mean multiple instances of the MU. Some have 4 channels, some 1.
Is that correct?

>, only some of them communicate
> directly with SCU.
>
OK

> SCU has some well defined protocol and
> MU should be used and configured in some SCU specific way. From NXP
> perspective, SCU firmware should not be replaceable and from Linux side
> seen as part of the HW.
>
Sure. But the behaviour (protocol) should be implemented in the client
driver, not the controller driver.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Oleksij Rempel]

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Hi Aishen, Jassie,

i'm lost in this discussion. Please, as soon as I need to add some
changes to my patches, notify me. Preferably on top for email.

On 28.07.2018 15:09, Jassi Brar wrote:
> On Fri, Jul 27, 2018 at 2:12 PM, A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> 
>>>>>>>
>>>>>>> MU has 4 pairs of TX_Reg + TX_IRQ, and 4 pairs of RX_Reg + RX_IRQ.
>>>>>>> (MU also has 4 "doorbell" type channels that it calls GP, but
>>>>>>> those are not managed here, so lets not worry atm).
>>>>>>>
>>>>>>> By definition, a mailbox channel is simply a signal, optionally
>>>>>>> with data attached. So, MU has 4 TX and 4 RX channels.
>>>>>>>
>>>>>>> The MU driver should populate 8 unidirectional (4 Tx and 4 RX)
>>>>>>> channels and set each tx/rx operation to trigger the corresponding
>>>>>>> interrupt. This is not my whim, this is how the controller is!
>>>>>>>
>>>>>>
>>>>>> This looks like reasonable to me, theoretically.
>>>>>> Just not sure whether it's necessary to support it because we
>>>>>> probably will never use like that in reality, then it might become
>>>>>> meaningless complicity introduced and error prone.
>>>>>>
>>>>> It _is_ necessary to write controller driver independent of client drivers.
>>>>>
>>>>
>>>> Yes, that's true. What if we think we're writing driver against HW
>>>> capabilities which support 4 pair of channel links(tx/rx)?
>>>> It looks like independent of client drivers and may make life easily.
>>>> Does it make sense?
>>>>
>>> No, that would be emulation.
>>> Why doesn't a usb device controller (udc) driver emulate FSG/HID etc, by
>>> "thinking" it has a hardware backed storage/keyboard? It doesn't because
>>> that is the job of upper protocol layer.
>>>
>>
>> Sorry I'm not quite familiar with USB device.
>>
> Which subsystem are you familiar with? Every stack is designed like
> that -- controller drivers reflect the physical hardware, any
> emulation/protocol is implemented in the user layer.
> 
> 
>> Another reason is I doubt that we may never use per register mode in a different register pair
>> in the future.
>>
> You may never use, but if the driver reflects the controller as
> precisely as it is, linux could support any usecase that some
> baremetal code could support on your platform.
> For example, you could support "normal" and "scu" mode over the 3-cell
> mechanism I suggested. But your original proposal/assumption of
> "scu-mode", failed immediately, hence Oleksij had to imlpement the
> "normal" mode.
> 
> 
>> For example:
>> AP:
>> node {
>>         ...
>>         // cell 0 meaning: 0: tx 1: rx  cell1 meaning: channel id
>>         Mboxes = <&mbox 0 1 &mbox 1 2>
>>         Mbox-names = "tx", "rx";
>>>
>>
>> M4:
>> node {
>>         ...
>>         Mboxes = <&mbox 0 2 &mbox 1 1>
>>         Mbox-names = "tx", "rx";
>>>
>> This make things complicated and error prone as I said before.
>>
> I don't see how.
> 
> 
>> But that's just my understanding and may overlook something, if you still think
>> we should do exactly as above, I will not against it because it does work for M4 case.
>>
> Cool, done.
> 
> 
>> Then the left question is how we handle SCU case?
>>
> Please point me to the code that you worry might not work.
> 
> 
>>
>> I'm a bit confusing....
>> The section 3.6 you pointed is the MHU register description. It does not conflict
>> with what I see from ARM doc center that each physical channel is unidirectional.
>>
>> See below:
>> Chan 1:
>> 0x000 SCP_INTR_L_STAT
>> 0x008 SCP_INTR_L_SET
>> 0x010 SCP _INTR_L_CLEAR
>>
>> Chan 2:
>> 0x020 SCP_INTR_H_STAT
>> 0x028 SCP_INTR_H_SET
>> 0x030 SCP _INTR_H_CLEAR
>>
>> Chan 3:
>> 0x100 CPU_INTR_L_STAT
>> 0x108 CPU_INTR_L_SET
>> 0x110 CPU_INTR_L_CLEAR
>>
>> Chan 4:
>> 0x120 CPU_INTR_H_STAT
>> 0x128 CPU_INTR_H_SET
>> 0x130 CPU_INTR_H_CLEAR
>>
>> Chan 5:
>> 0x200 SCP_INTR_S_STAT
>> 0x208 SCP_INTR_S_SET
>> 0x210 SCP _INTR_S_CLEAR
>>
>> Chan 6:
>> 0x300 CPU_INTR_S_STAT
>> 0x308 CPU_INTR_S_SET
>> 0x310 CPU_INTR_S_CLEAR
>>
>> And the driver compose them into 3 channel links (lp, hp and sec).
>> Am I wrong?
>>
> The RX and TX are not independent of each other, their priorities are
> tied together in hardware. So it makes more sense (as compared to
> declaring them independent) to club them together as one channel.
> Whatever example you take - MHU or TI - you won't find a driver that
> implements a virtual mode like "scu-mode".
> 
> 
>>>>
>>>> Sorry for may not clear, "Passing short message' usecase is to tell
>>>> how the HW is working on one channel mode sending up to 4 words in one
>>>> time As specified in reference manual.
>>>>
>>>> SCU does work that way, the only difference is it's using polling mode
>>>> rather than interrupt driven.  The point is the data size may be
>>>> different for each msg, so we can't simply know which data register
>>>> interrupt should be enable from static data defined in device tree.
>>>>
>>> And you think passing variable data through registers is a better idea than
>>> passing packets via shared-memory?
>>>
>>
>> You got me. :-)
>> I've no idea about which one is better.
>>
> Passing data directly via controller makes sense only when your
> protocol defines fixed length packets that fit into registers (usually
> FIFOs) or there is no shared memory between the processors.
> Otherwise, you write a data packet at some located in shmem, and
> provide its start and size along with the code of expected operation
> on it, over the mailbox. Please refer to "Passing frame information"
> para of page-2743 of your manual.
> That is another reason the SCU implementation is broken - it has
> variable length packets and yet use registers to pass them around.
> 
> 
>> The problem is SCU firmware is already
>> there passing packets through data registers, we have no way to change it.
>>
> OK. But what is SCU exactly? Part of ATF? Do you get some binary from
> third party? If the last, you shouldn't be paying hsit for such a
> design.
> 
> 
>>>
>>> The hardware has 8 unidirectional channels. But your protocol (SCU
>>> implementation) assumes there is one _virtual_ channel that has 4 registers
>>> and 1/0 irq --- which is not true. Instead of fixing the assumption in your
>>> protocol or emulating the virtual channel in the protocol level (user of a MU),
>>> you want to add code in the controller driver that ignores interrupts and club
>>> the 4 independent channels together.
>>>
>>
>> This stucks me. This is how the hardware is designed  and suggested to use
>> in hardware reference manual. And now you're telling me this is wrong and
>> we should not use the design in reference manual...
>>
> What you call "suggested to use in hardware reference manual" is just
> 1/5 examples of usecase.
> And SCU is not even doing that correctly (it uses variable length
> packet, unlike the fixed 4-words suggestion).
> 
> A manual can suggest multiple ways of implementing a usecase. It is
> our job to chose the best one.
> 


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RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

Hi Oleksij,

> -----Original Message-----
> From: Oleksij Rempel [mailto:o.rempel@pengutronix.de]
> Sent: Monday, July 30, 2018 3:36 PM
> To: Jassi Brar <jassisinghbrar@gmail.com>; A.s. Dong
> <aisheng.dong@nxp.com>
> Cc: , Sascha Hauer <kernel@pengutronix.de>; Shawn Guo
> <shawnguo@kernel.org>; Fabio Estevam <fabio.estevam@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>; ", linux-arm-
> kernel"@lists.infradead.org; linux-mediatek@lists.infradead.org;
> srv_heupstream <linux-arm-kernel@lists.infradead.org>; Devicetree List
> <devicetree@vger.kernel.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU
> channel support
> 
> Hi Aishen, Jassie,
> 
> i'm lost in this discussion. Please, as soon as I need to add some changes to
> my patches, notify me. Preferably on top for email.
> 

I just send you an email of Jassie's early suggestion.

According to the suggestion, the binding needs to be changed into 8 separate
TX/RX channels. You can quickly start from there.

Regards
Dong Aisheng

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> Hi Aishen, Jassie,
>
> i'm lost in this discussion. Please, as soon as I need to add some
> changes to my patches, notify me. Preferably on top for email.
>
I am ok with however you choose to implement, 8 unidirectional or 4
bidirectional channels or whatever.

We just can't have protocol specific s/w modes in the controller drivers.

The best solution is to fix the SCU firmware. If that is _really_
impossible, I provided a solution (3 cells work around). If you have a
better idea please feel free to propose and implement that.

It will also help if you could share the user code of "scu-mode". If
there is no such code (and we know the driver doesn't respect the
"scu-mode" property) why do we even have that binding? Maybe drop it.

thnx.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

> -----Original Message-----
> From: Jassi Brar [mailto:jassisinghbrar@gmail.com]
> Sent: Monday, July 30, 2018 9:05 PM
> To: Oleksij Rempel <o.rempel@pengutronix.de>
> Cc: A.s. Dong <aisheng.dong@nxp.com>; , Sascha Hauer
> <kernel@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; Fabio
> Estevam <fabio.estevam@nxp.com>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Vladimir Zapolskiy
> <vladimir_zapolskiy@mentor.com>; ", linux-arm-
> kernel"@lists.infradead.org; , linux-arm-kernel@lists.infradead.org, linux-
> mediatek@lists.infradead.org, srv_heupstream <linux-
> mediatek@lists.infradead.org>; srv_heupstream <linux-arm-
> kernel@lists.infradead.org>; Devicetree List <devicetree@vger.kernel.org>;
> dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU
> channel support
> 
> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de>
> wrote:
> > Hi Aishen, Jassie,
> >
> > i'm lost in this discussion. Please, as soon as I need to add some
> > changes to my patches, notify me. Preferably on top for email.
> >
> I am ok with however you choose to implement, 8 unidirectional or 4
> bidirectional channels or whatever.
> 
> We just can't have protocol specific s/w modes in the controller drivers.
> 

Do you think implement "Passing short messages" defined in reference
manual in controller driver is protocol specific?
That seems like our most argument before.

> The best solution is to fix the SCU firmware. If that is _really_ impossible, I
> provided a solution (3 cells work around). If you have a better idea please
> feel free to propose and implement that.
> 

That's out of our control.
SCU firmware is not using Linux and there's no mailbox framework.
It's simply follow "passing short messages" way to send multi words with 4 data
Registers.
 
> It will also help if you could share the user code of "scu-mode". If there is no
> such code (and we know the driver doesn't respect the "scu-mode" property)
> why do we even have that binding? Maybe drop it.

You can refer to this patch for the user code of "scu-mode".
[RFC PATCH v6 2/2] mailbox: imx-mailbox: add scu protocol support
https://www.spinics.net/lists/arm-kernel/msg665135.html

And I do admit that there're two protocol specific bits in the driver.
1. Unlike TI message header, SCU size is in the second u8.
Ti message header:
struct ti_msgmgr_message {
        size_t len;
        u8 *buf;
};
Controller get the size from the first u32.

SCU message header:
struct sc_rpc_msg {
        uint8_t ver;
        uint8_t size;
        uint8_t svc; 
        uint8_t func;
};
Controller get the size from the second u8.

And a full SCU message is like:
struct imx_sc_msg_req_set_clock_rate {
        struct sc_rpc_msg hdr;
        u32 rate;
        u16 resource;
        u8 clk;
} __packed;

2. There's no synchronous read function in mailbox framework,
So we use mbox_client_peek_data to read data which can't return
the read data. In order to save a mem copy from read data to the
data buffer, the controller driver saves the tx data buffer in itself. 
(Anyway to improve? Maybe we should implement a synchronous
mbox_client_read_data()?)

And for SCU IPC client, it's something like:
int sc_call_rpc(sc_ipc_t ipc, void *msg, bool no_resp)
{
        ...
        mbox_send_message(sc_ipc->chan, msg);

        if (!no_resp) 
                ret = mbox_client_peek_data(sc_ipc->chan);

        mbox_client_txdone(sc_ipc->chan, ret);
        ...
}

int sc_ipc_open(sc_ipc_t *ipc, struct device *dev)
{
        sc_ipc->cl.dev = dev; 
        sc_ipc->cl.tx_block = false;
        sc_ipc->cl.knows_txdone = true;

        sc_ipc->chan = mbox_request_channel(&sc_ipc->cl, 0);
        ...
}

Any better ideas?

Regards
Dong Aisheng

> 
> thnx.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

[...]
> > It will also help if you could share the user code of "scu-mode". If
> > there is no such code (and we know the driver doesn't respect the
> > "scu-mode" property) why do we even have that binding? Maybe drop it.
> 
> You can refer to this patch for the user code of "scu-mode".
> [RFC PATCH v6 2/2] mailbox: imx-mailbox: add scu protocol support
> https://www.spinics.net/lists/arm-kernel/msg665135.html
> 
> And I do admit that there're two protocol specific bits in the driver.
> 1. Unlike TI message header, SCU size is in the second u8.
> Ti message header:
> struct ti_msgmgr_message {
>         size_t len;
>         u8 *buf;
> };
> Controller get the size from the first u32.
> 
> SCU message header:
> struct sc_rpc_msg {
>         uint8_t ver;
>         uint8_t size;
>         uint8_t svc;
>         uint8_t func;
> };
> Controller get the size from the second u8.
> 
> And a full SCU message is like:
> struct imx_sc_msg_req_set_clock_rate {
>         struct sc_rpc_msg hdr;
>         u32 rate;
>         u16 resource;
>         u8 clk;
> } __packed;
> 
> 2. There's no synchronous read function in mailbox framework, So we use
> mbox_client_peek_data to read data which can't return the read data. In
> order to save a mem copy from read data to the data buffer, the controller
> driver saves the tx data buffer in itself.
> (Anyway to improve? Maybe we should implement a synchronous
> mbox_client_read_data()?)
> 
> And for SCU IPC client, it's something like:
> int sc_call_rpc(sc_ipc_t ipc, void *msg, bool no_resp) {
>         ...
>         mbox_send_message(sc_ipc->chan, msg);
> 
>         if (!no_resp)
>                 ret = mbox_client_peek_data(sc_ipc->chan);
> 
>         mbox_client_txdone(sc_ipc->chan, ret);
>         ...
> }
> 
> int sc_ipc_open(sc_ipc_t *ipc, struct device *dev) {
>         sc_ipc->cl.dev = dev;
>         sc_ipc->cl.tx_block = false;
>         sc_ipc->cl.knows_txdone = true;
> 
>         sc_ipc->chan = mbox_request_channel(&sc_ipc->cl, 0);
>         ...
> }
> 
> Any better ideas?
> 

And this the original implementation used by NXP internally without mailbox.
As it's quite simple and suppose more easy to help you understand the using of SCU.

void mu_send_msg(struct mu_priv *priv, uint32_t index, uint32_t msg)
{
        ...
        /* Wait TX register to be empty. */ 
        while (!(readl_relaxed(priv->base + MU_ASR) & mask))
                ;
        writel_relaxed(msg, priv->base + MU_ATR0  + (index * 4));
}

/*
 * Wait to receive message from the other core.
 */
void mu_receive_msg(struct mu_priv *priv, uint32_t index, uint32_t *msg)
{
        ...
        /* Wait RX register to be full. */
        while (!(readl_relaxed(priv->base + MU_ASR) & mask))
                ;
        *msg = readl_relaxed(priv->base + MU_ARR0 + (index * 4));
}

static void sc_ipc_read(struct sc_ipc *sc_ipc, void *data)
{
        sc_rpc_msg_t *msg = (sc_rpc_msg_t *)data;
 
        /* Read first word */
        mu_receive_msg(sc_ipc->mu, 0, (uint32_t *)msg);
        count++;
 
        /* Read remaining words */
        while (count < msg->size) {
                mu_receive_msg(sc_ipc->mu, count % MU_RR_COUNT,
                               &(msg->DATA.u32[count - 1]));
                count++;
        }
}

static void sc_ipc_write(struct sc_ipc *sc_ipc, void *data)
{
        sc_rpc_msg_t *msg = (sc_rpc_msg_t *)data;
        uint8_t count = 0;

        /* Write first word */
        mu_send_msg(sc_ipc->mu, 0, *((uint32_t *)msg));
        count++;

        while (count < msg->size) {
                mu_send_msg(sc_ipc->mu, count % MU_TR_COUNT,
                            msg->DATA.u32[count - 1]);
                count++;
        }
}

void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
{
        sc_ipc_write(sc_ipc, msg);
        if (!no_resp)
                sc_ipc_read(sc_ipc, msg);
}

For details, see:
https://www.spinics.net/lists/arm-kernel/msg659138.html

Regards
Dong Aisheng

> Regards
> Dong Aisheng
> 
> >
> > thnx.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

> -----Original Message-----
> From: Jassi Brar [mailto:jassisinghbrar@gmail.com]
> Sent: Monday, July 30, 2018 9:05 PM
> To: Oleksij Rempel <o.rempel@pengutronix.de>
> Cc: A.s. Dong <aisheng.dong@nxp.com>; , Sascha Hauer
> <kernel@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; Fabio
> Estevam <fabio.estevam@nxp.com>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Vladimir Zapolskiy
> <vladimir_zapolskiy@mentor.com>; ", linux-arm-
> kernel"@lists.infradead.org; , linux-arm-kernel@lists.infradead.org, linux-
> mediatek@lists.infradead.org, srv_heupstream <linux-
> mediatek@lists.infradead.org>; srv_heupstream <linux-arm-
> kernel@lists.infradead.org>; Devicetree List <devicetree@vger.kernel.org>;
> dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU
> channel support
> 
> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de>
> wrote:
> > Hi Aishen, Jassie,
> >
> > i'm lost in this discussion. Please, as soon as I need to add some
> > changes to my patches, notify me. Preferably on top for email.
> >
> I am ok with however you choose to implement, 8 unidirectional or 4
> bidirectional channels or whatever.
> 
> We just can't have protocol specific s/w modes in the controller drivers.
> 
> The best solution is to fix the SCU firmware. If that is _really_ impossible, I
> provided a solution (3 cells work around). If you have a better idea please
> feel free to propose and implement that.
> 
> It will also help if you could share the user code of "scu-mode". If there is no
> such code (and we know the driver doesn't respect the "scu-mode" property)
> why do we even have that binding? Maybe drop it.

The initial idea is using mbox-cells value to distinguish which MU mode is used
(single chan or multi chans).

Regards
Dong Aisheng

> 
> thnx.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Oleksij Rempel]

[-- Attachment #1.1: Type: text/plain, Size: 1610 bytes --]

On Mon, Jul 30, 2018 at 06:34:56PM +0530, Jassi Brar wrote:
> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> > Hi Aishen, Jassie,
> >
> > i'm lost in this discussion. Please, as soon as I need to add some
> > changes to my patches, notify me. Preferably on top for email.
> >
> I am ok with however you choose to implement, 8 unidirectional or 4
> bidirectional channels or whatever.
> 
> We just can't have protocol specific s/w modes in the controller drivers.
> 
> The best solution is to fix the SCU firmware. If that is _really_
> impossible, I provided a solution (3 cells work around). If you have a
> better idea please feel free to propose and implement that.
> 
> It will also help if you could share the user code of "scu-mode". If
> there is no such code (and we know the driver doesn't respect the
> "scu-mode" property) why do we even have that binding? Maybe drop it.

Tomorrow I have a time slot to address your generic iMX MU suggestions.
So, what is better, uni- or bi-directional channels? Should I implement
*all* (4TX+FIFO, 4RX+FIFO, 4TX-simple, 4RX-simple) channels in this run?
If yes, how should it be reflected in DT?
- 1 cell: &mu [0-15]
- 2 cells: &mu [0-7] [TX,RX]
- 3 cells: &mu [0-4] [FIFO,NOFIFO] [TX,RX]

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Mon, Jul 30, 2018 at 8:14 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> On Mon, Jul 30, 2018 at 06:34:56PM +0530, Jassi Brar wrote:
>> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>> > Hi Aishen, Jassie,
>> >
>> > i'm lost in this discussion. Please, as soon as I need to add some
>> > changes to my patches, notify me. Preferably on top for email.
>> >
>> I am ok with however you choose to implement, 8 unidirectional or 4
>> bidirectional channels or whatever.
>>
>> We just can't have protocol specific s/w modes in the controller drivers.
>>
>> The best solution is to fix the SCU firmware. If that is _really_
>> impossible, I provided a solution (3 cells work around). If you have a
>> better idea please feel free to propose and implement that.
>>
>> It will also help if you could share the user code of "scu-mode". If
>> there is no such code (and we know the driver doesn't respect the
>> "scu-mode" property) why do we even have that binding? Maybe drop it.
>
> Tomorrow I have a time slot to address your generic iMX MU suggestions.
> So, what is better, uni- or bi-directional channels?
>
The datasheet indicates there are 4 tx and 4 rx channels. So 8
uni-directional channels (which allow more fine-grained/efficient
resource allocation btw).

> Should I implement
> *all* (4TX+FIFO, 4RX+FIFO, 4TX-simple, 4RX-simple) channels in this run?
>
>From datasheet, each of 8 channels should be defined as signal+data
i.e, IRQ + TX/RX_Reg.
The rest 4 GP channels are doorbells (irq only).

So we can have 2-cells.
    First cell is 0->Tx, 1->RX, 2->Doorbell
    Second cell is index of the channel {0,3}

Now you may implement only RX+TX, and leave 'doorbell' out for future.
Thats ok, because we wouldn't have to change bindings then.

However, if SCU (in its current form) must be supported. We may need
to add the third cell (irq enable or not) or some better way, right
now.

> If yes, how should it be reflected in DT?
> - 1 cell: &mu [0-15]
> - 2 cells: &mu [0-7] [TX,RX]
> - 3 cells: &mu [0-4] [FIFO,NOFIFO] [TX,RX]
>
It may be possible for a device binding to have variable cells, but I
haven't seen any. And I am not sure that would look neat either.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

Hi Jassi,

> > If yes, how should it be reflected in DT?
> > - 1 cell: &mu [0-15]
> > - 2 cells: &mu [0-7] [TX,RX]
> > - 3 cells: &mu [0-4] [FIFO,NOFIFO] [TX,RX]
> >
> It may be possible for a device binding to have variable cells, but I haven't
> seen any. And I am not sure that would look neat either.

Please refer to 
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. Must be a single cell with a value of at least 3.
  If the system requires describing PPI affinity, then the value must
  be at least 4.

Regards
Dong Aisheng

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Mon, Jul 30, 2018 at 8:32 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
> On Mon, Jul 30, 2018 at 8:14 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>> On Mon, Jul 30, 2018 at 06:34:56PM +0530, Jassi Brar wrote:
>>> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>>> > Hi Aishen, Jassie,
>>> >
>>> > i'm lost in this discussion. Please, as soon as I need to add some
>>> > changes to my patches, notify me. Preferably on top for email.
>>> >
>>> I am ok with however you choose to implement, 8 unidirectional or 4
>>> bidirectional channels or whatever.
>>>
>>> We just can't have protocol specific s/w modes in the controller drivers.
>>>
>>> The best solution is to fix the SCU firmware. If that is _really_
>>> impossible, I provided a solution (3 cells work around). If you have a
>>> better idea please feel free to propose and implement that.
>>>
>>> It will also help if you could share the user code of "scu-mode". If
>>> there is no such code (and we know the driver doesn't respect the
>>> "scu-mode" property) why do we even have that binding? Maybe drop it.
>>
>> Tomorrow I have a time slot to address your generic iMX MU suggestions.
>> So, what is better, uni- or bi-directional channels?
>>
> The datasheet indicates there are 4 tx and 4 rx channels. So 8
> uni-directional channels (which allow more fine-grained/efficient
> resource allocation btw).
>
>> Should I implement
>> *all* (4TX+FIFO, 4RX+FIFO, 4TX-simple, 4RX-simple) channels in this run?
>>
> From datasheet, each of 8 channels should be defined as signal+data
> i.e, IRQ + TX/RX_Reg.
> The rest 4 GP channels are doorbells (irq only).
>
> So we can have 2-cells.
>     First cell is 0->Tx, 1->RX, 2->Doorbell
>     Second cell is index of the channel {0,3}
>
> Now you may implement only RX+TX, and leave 'doorbell' out for future.
> Thats ok, because we wouldn't have to change bindings then.
>
> However, if SCU (in its current form) must be supported. We may need
> to add the third cell (irq enable or not) or some better way, right
> now.
>
Looking at imx_mu_scu_send_data(), which simply polls on the tx, I
think we don't even need third cell for scu client. A simple 2-cell, 8
uni-dir channel setup should work.
If I see the scu client driver, I could confirm how it would work.

So, lets please do the 8 uni-directional, 2 cells implementation.

Regards.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Oleksij Rempel]

[-- Attachment #1.1: Type: text/plain, Size: 3101 bytes --]

On Mon, Jul 30, 2018 at 09:48:35PM +0530, Jassi Brar wrote:
> On Mon, Jul 30, 2018 at 8:32 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
> > On Mon, Jul 30, 2018 at 8:14 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> >> On Mon, Jul 30, 2018 at 06:34:56PM +0530, Jassi Brar wrote:
> >>> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
> >>> > Hi Aishen, Jassie,
> >>> >
> >>> > i'm lost in this discussion. Please, as soon as I need to add some
> >>> > changes to my patches, notify me. Preferably on top for email.
> >>> >
> >>> I am ok with however you choose to implement, 8 unidirectional or 4
> >>> bidirectional channels or whatever.
> >>>
> >>> We just can't have protocol specific s/w modes in the controller drivers.
> >>>
> >>> The best solution is to fix the SCU firmware. If that is _really_
> >>> impossible, I provided a solution (3 cells work around). If you have a
> >>> better idea please feel free to propose and implement that.
> >>>
> >>> It will also help if you could share the user code of "scu-mode". If
> >>> there is no such code (and we know the driver doesn't respect the
> >>> "scu-mode" property) why do we even have that binding? Maybe drop it.
> >>
> >> Tomorrow I have a time slot to address your generic iMX MU suggestions.
> >> So, what is better, uni- or bi-directional channels?
> >>
> > The datasheet indicates there are 4 tx and 4 rx channels. So 8
> > uni-directional channels (which allow more fine-grained/efficient
> > resource allocation btw).
> >
> >> Should I implement
> >> *all* (4TX+FIFO, 4RX+FIFO, 4TX-simple, 4RX-simple) channels in this run?
> >>
> > From datasheet, each of 8 channels should be defined as signal+data
> > i.e, IRQ + TX/RX_Reg.
> > The rest 4 GP channels are doorbells (irq only).
> >
> > So we can have 2-cells.
> >     First cell is 0->Tx, 1->RX, 2->Doorbell
> >     Second cell is index of the channel {0,3}
> >
> > Now you may implement only RX+TX, and leave 'doorbell' out for future.
> > Thats ok, because we wouldn't have to change bindings then.
> >
> > However, if SCU (in its current form) must be supported. We may need
> > to add the third cell (irq enable or not) or some better way, right
> > now.
> >
> Looking at imx_mu_scu_send_data(), which simply polls on the tx, I
> think we don't even need third cell for scu client. A simple 2-cell, 8
> uni-dir channel setup should work.
> If I see the scu client driver, I could confirm how it would work.
> 
> So, lets please do the 8 uni-directional, 2 cells implementation.

Just in case.. to avoid confusion (or add more...). There are 4 GIP (General Interrupt Request n
Pending bits) or RX-doorbell and 4 GIR (General Interrupt Request bits)
or TX-doorbell.

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Mon, Jul 30, 2018 at 10:19 PM, Oleksij Rempel
<o.rempel@pengutronix.de> wrote:
> On Mon, Jul 30, 2018 at 09:48:35PM +0530, Jassi Brar wrote:
>> On Mon, Jul 30, 2018 at 8:32 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
>> > On Mon, Jul 30, 2018 at 8:14 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>> >> On Mon, Jul 30, 2018 at 06:34:56PM +0530, Jassi Brar wrote:
>> >>> On Mon, Jul 30, 2018 at 1:05 PM, Oleksij Rempel <o.rempel@pengutronix.de> wrote:
>> >>> > Hi Aishen, Jassie,
>> >>> >
>> >>> > i'm lost in this discussion. Please, as soon as I need to add some
>> >>> > changes to my patches, notify me. Preferably on top for email.
>> >>> >
>> >>> I am ok with however you choose to implement, 8 unidirectional or 4
>> >>> bidirectional channels or whatever.
>> >>>
>> >>> We just can't have protocol specific s/w modes in the controller drivers.
>> >>>
>> >>> The best solution is to fix the SCU firmware. If that is _really_
>> >>> impossible, I provided a solution (3 cells work around). If you have a
>> >>> better idea please feel free to propose and implement that.
>> >>>
>> >>> It will also help if you could share the user code of "scu-mode". If
>> >>> there is no such code (and we know the driver doesn't respect the
>> >>> "scu-mode" property) why do we even have that binding? Maybe drop it.
>> >>
>> >> Tomorrow I have a time slot to address your generic iMX MU suggestions.
>> >> So, what is better, uni- or bi-directional channels?
>> >>
>> > The datasheet indicates there are 4 tx and 4 rx channels. So 8
>> > uni-directional channels (which allow more fine-grained/efficient
>> > resource allocation btw).
>> >
>> >> Should I implement
>> >> *all* (4TX+FIFO, 4RX+FIFO, 4TX-simple, 4RX-simple) channels in this run?
>> >>
>> > From datasheet, each of 8 channels should be defined as signal+data
>> > i.e, IRQ + TX/RX_Reg.
>> > The rest 4 GP channels are doorbells (irq only).
>> >
>> > So we can have 2-cells.
>> >     First cell is 0->Tx, 1->RX, 2->Doorbell
>> >     Second cell is index of the channel {0,3}
>> >
>> > Now you may implement only RX+TX, and leave 'doorbell' out for future.
>> > Thats ok, because we wouldn't have to change bindings then.
>> >
>> > However, if SCU (in its current form) must be supported. We may need
>> > to add the third cell (irq enable or not) or some better way, right
>> > now.
>> >
>> Looking at imx_mu_scu_send_data(), which simply polls on the tx, I
>> think we don't even need third cell for scu client. A simple 2-cell, 8
>> uni-dir channel setup should work.
>> If I see the scu client driver, I could confirm how it would work.
>>
>> So, lets please do the 8 uni-directional, 2 cells implementation.
>
> Just in case.. to avoid confusion (or add more...). There are 4 GIP (General Interrupt Request n
> Pending bits) or RX-doorbell and 4 GIR (General Interrupt Request bits)
> or TX-doorbell.
>
Ok. But the approach remains the same.

thanks.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

Hi Jassi,

> > However, if SCU (in its current form) must be supported. We may need
> > to add the third cell (irq enable or not) or some better way, right
> > now.
> >
> Looking at imx_mu_scu_send_data(), which simply polls on the tx, I think we
> don't even need third cell for scu client. A simple 2-cell, 8 uni-dir channel
> setup should work.

How would you suggest to use for SCU in 2 -cells?

> If I see the scu client driver, I could confirm how it would work.
> 

I've already given a general overview from here:
https://www.spinics.net/lists/arm-kernel/msg669202.html

Do you need me to send the full scu client driver patch for the reference?
If yes, please feel free to let me know.

Regards
Dong Aisheng

> So, lets please do the 8 uni-directional, 2 cells implementation.
> 
> Regards.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Tue, Jul 31, 2018 at 12:51 PM, A.s. Dong <aisheng.dong@nxp.com> wrote:
> Hi Jassi,
>
>> > However, if SCU (in its current form) must be supported. We may need
>> > to add the third cell (irq enable or not) or some better way, right
>> > now.
>> >
>> Looking at imx_mu_scu_send_data(), which simply polls on the tx, I think we
>> don't even need third cell for scu client. A simple 2-cell, 8 uni-dir channel
>> setup should work.
>
> How would you suggest to use for SCU in 2 -cells?
>
>> If I see the scu client driver, I could confirm how it would work.
>>
>
> I've already given a general overview from here:
> https://www.spinics.net/lists/arm-kernel/msg669202.html
>
No, that is controller side code.

> Do you need me to send the full scu client driver patch for the reference?
> If yes, please feel free to let me know.
>
Yes, that'll make it clearer.

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Tue, Jul 31, 2018 at 3:45 PM, Jassi Brar <jassisinghbrar@gmail.com> wrote:
> On Tue, Jul 31, 2018 at 12:51 PM, A.s. Dong <aisheng.dong@nxp.com> wrote:
>> Hi Jassi,
>>
>>> > However, if SCU (in its current form) must be supported. We may need
>>> > to add the third cell (irq enable or not) or some better way, right
>>> > now.
>>> >
>>> Looking at imx_mu_scu_send_data(), which simply polls on the tx, I think we
>>> don't even need third cell for scu client. A simple 2-cell, 8 uni-dir channel
>>> setup should work.
>>
>> How would you suggest to use for SCU in 2 -cells?
>>
>>> If I see the scu client driver, I could confirm how it would work.
>>>
>>
>> I've already given a general overview from here:
>> https://www.spinics.net/lists/arm-kernel/msg669202.html
>>
> No, that is controller side code.
>
>> Do you need me to send the full scu client driver patch for the reference?
>> If yes, please feel free to let me know.
>>
> Yes, that'll make it clearer.
>
Thanks for sharing the patch offline.

I don't see why it can't be adapted to work with the simple 2-cell
implementation. Instead of one virtual, ask for 4 physical channels
and send data in u32 chunks sequentially over them.
In fact, that should make it even better by removing the tight-loop
(zero delay!!) polling in send_data() -- MU does support interrupts,
why not use them to avoid polling?  If you find it hard, I can make a
patch on top of your client patchset, once Oleksij is done with the MU
driver.

I have some more suggestions for the client driver. But since I don't
have to live with them (you do), I can't demand you make those
changes. If you like, please feel free to cc me on the next revision
of the client driver.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

Hi Jassi,

> -----Original Message-----
> From: Jassi Brar [mailto:jassisinghbrar@gmail.com]
> Sent: Tuesday, July 31, 2018 8:42 PM
> To: A.s. Dong <aisheng.dong@nxp.com>

[...]

> >> Do you need me to send the full scu client driver patch for the reference?
> >> If yes, please feel free to let me know.
> >>
> > Yes, that'll make it clearer.
> >
> Thanks for sharing the patch offline.
> 
> I don't see why it can't be adapted to work with the simple 2-cell
> implementation. Instead of one virtual, ask for 4 physical channels and send
> data in u32 chunks sequentially over them.
> In fact, that should make it even better by removing the tight-loop (zero
> delay!!) polling in send_data() -- MU does support interrupts, why not use
> them to avoid polling?  If you find it hard, I can make a patch on top of your
> client patchset, once Oleksij is done with the MU driver.
> 

As you insist, I will try to implement multi channels mode, then we can do a
clear comparison to see which one is better for SCU mode rather than assumptions.

First of all,  using interrupt for each chan will likely to terribly slow down the SCU
Message handling speed. SCU Messages usually are handled by SCU firmware very
quickly in a few microseconds. (< 10us). That's why we use polling mode for SCU
message handling.

If we break down a SCU message into a few separate MU channel interrupts driven,
There will be a lot of unnecessary and meaningless interrupt handling.
And the whole flow may look like:

Sending Word 0 ->
Chan 0 interrupt -> (meaningless)
Sending Word 1 ->
Chan1 interrupt -> (meaningless)
Sending Word 2 ->
Chan2 interrupt -> (meaningless)
Sending Word 3 ->
Chan3 interrupt-> (meaningless)

Sending Word 4 on Chan 0 again ->
Wait for Chan 0 interrupt (meaningless) ->
...

Then waiting for Rx:

Chan 0 Rx interrupt ->
Read Word 0   ->
(Then we know response size here)

Chan 1 Rx interrupt ->
Read Word 1 ->
Chan 2 Rx interrupt ->
Read Word 2 ->
Chan 3 Rx interrupt ->
Read Word 3 ->

(If msg size > 4 words)
Chan 0 Rx interrupt ->
Read Word 4

...
And we must use a complicated way to map the received data of each channel
into one SCU msg buffer and need handle the sequence properly for size > 4
words case

Is this what you intended?

Per my understanding, there're several issues for this follow:
1) Many unnecessary and meaningless interrupts hanllding of Tx and RX
2) Performance downgrading
    A 4 word SCU MSG may need 8 interrupts to handle which terribly slow
    down the speed. (Interrupt latency will be terrible if many)
3) Complex RX flow in order to align with framework design

Any comments about these issues?

Generally, from what I see, the mailbox framework really is not designed for SCU type
devices that handling msg sending or receiving via multiple channels.  Including the
ring buffer supported for handling several msgs on the same channel and rich
completion mechanism, none of them are suitable for SCU MU in multiple channel mode.

What we really actually needed is a quite simple way to handle MSG Tx and Tx
synchronously.

int sc_call_rpc(sc_ipc_t ipc, void *msg, bool no_resp)
{       
        ...
        ret = mbox_send_message(sc_ipc->chan, msg);
        if (!no_resp) 
                ret = mbox_receive_message(sc_ipc->chan, msg);
        ...
        return ret;
}

For me, I don't think the above way driven by interrupt is suitable for SCU.
But I will still keep investigating if any better way to handle it in multi chan
mode as you wish.

How would you suggest for such situation in order to support SCU properly?

> I have some more suggestions for the client driver. But since I don't have to
> live with them (you do), I can't demand you make those changes. If you like,
> please feel free to cc me on the next revision of the client driver.

I certainly appreciate any clear and valuable improvement suggestions.
Just feel free to let me know if any better idea.

Regards
Dong Aisheng

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

Hi Jassi,

Do you have any comments about this reply?

Sascha,
What's your option?

Regards
Dong Aisheng

> -----Original Message-----
> From: A.s. Dong
> Sent: Thursday, August 2, 2018 5:24 PM
> To: 'Jassi Brar' <jassisinghbrar@gmail.com>
> Cc: Oleksij Rempel <o.rempel@pengutronix.de>; , Sascha Hauer
> <kernel@pengutronix.de>; Shawn Guo <shawnguo@kernel.org>; Fabio
> Estevam <fabio.estevam@nxp.com>; Rob Herring <robh+dt@kernel.org>;
> Mark Rutland <mark.rutland@arm.com>; Vladimir Zapolskiy
> <vladimir_zapolskiy@mentor.com>; , linux-arm-kernel@lists.infradead.org,
> linux-mediatek@lists.infradead.org, srv_heupstream <linux-arm-
> kernel@lists.infradead.org>; , linux-arm-kernel@lists.infradead.org, linux-
> mediatek@lists.infradead.org, srv_heupstream <linux-
> mediatek@lists.infradead.org>; Devicetree List
> <devicetree@vger.kernel.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU
> channel support
> 
> Hi Jassi,
> 
> > -----Original Message-----
> > From: Jassi Brar [mailto:jassisinghbrar@gmail.com]
> > Sent: Tuesday, July 31, 2018 8:42 PM
> > To: A.s. Dong <aisheng.dong@nxp.com>
> 
> [...]
> 
> > >> Do you need me to send the full scu client driver patch for the reference?
> > >> If yes, please feel free to let me know.
> > >>
> > > Yes, that'll make it clearer.
> > >
> > Thanks for sharing the patch offline.
> >
> > I don't see why it can't be adapted to work with the simple 2-cell
> > implementation. Instead of one virtual, ask for 4 physical channels
> > and send data in u32 chunks sequentially over them.
> > In fact, that should make it even better by removing the tight-loop
> > (zero
> > delay!!) polling in send_data() -- MU does support interrupts, why not
> > use them to avoid polling?  If you find it hard, I can make a patch on
> > top of your client patchset, once Oleksij is done with the MU driver.
> >
> 
> As you insist, I will try to implement multi channels mode, then we can do a
> clear comparison to see which one is better for SCU mode rather than
> assumptions.
> 
> First of all,  using interrupt for each chan will likely to terribly slow down the
> SCU Message handling speed. SCU Messages usually are handled by SCU
> firmware very quickly in a few microseconds. (< 10us). That's why we use
> polling mode for SCU message handling.
> 
> If we break down a SCU message into a few separate MU channel interrupts
> driven, There will be a lot of unnecessary and meaningless interrupt handling.
> And the whole flow may look like:
> 
> Sending Word 0 ->
> Chan 0 interrupt -> (meaningless)
> Sending Word 1 ->
> Chan1 interrupt -> (meaningless)
> Sending Word 2 ->
> Chan2 interrupt -> (meaningless)
> Sending Word 3 ->
> Chan3 interrupt-> (meaningless)
> 
> Sending Word 4 on Chan 0 again ->
> Wait for Chan 0 interrupt (meaningless) -> ...
> 
> Then waiting for Rx:
> 
> Chan 0 Rx interrupt ->
> Read Word 0   ->
> (Then we know response size here)
> 
> Chan 1 Rx interrupt ->
> Read Word 1 ->
> Chan 2 Rx interrupt ->
> Read Word 2 ->
> Chan 3 Rx interrupt ->
> Read Word 3 ->
> 
> (If msg size > 4 words)
> Chan 0 Rx interrupt ->
> Read Word 4
> 
> ...
> And we must use a complicated way to map the received data of each
> channel into one SCU msg buffer and need handle the sequence properly for
> size > 4 words case
> 
> Is this what you intended?
> 
> Per my understanding, there're several issues for this follow:
> 1) Many unnecessary and meaningless interrupts hanllding of Tx and RX
> 2) Performance downgrading
>     A 4 word SCU MSG may need 8 interrupts to handle which terribly slow
>     down the speed. (Interrupt latency will be terrible if many)
> 3) Complex RX flow in order to align with framework design
> 
> Any comments about these issues?
> 
> Generally, from what I see, the mailbox framework really is not designed for
> SCU type devices that handling msg sending or receiving via multiple
> channels.  Including the ring buffer supported for handling several msgs on
> the same channel and rich completion mechanism, none of them are suitable
> for SCU MU in multiple channel mode.
> 
> What we really actually needed is a quite simple way to handle MSG Tx and
> Tx synchronously.
> 
> int sc_call_rpc(sc_ipc_t ipc, void *msg, bool no_resp)
> {
>         ...
>         ret = mbox_send_message(sc_ipc->chan, msg);
>         if (!no_resp)
>                 ret = mbox_receive_message(sc_ipc->chan, msg);
>         ...
>         return ret;
> }
> 
> For me, I don't think the above way driven by interrupt is suitable for SCU.
> But I will still keep investigating if any better way to handle it in multi chan
> mode as you wish.
> 
> How would you suggest for such situation in order to support SCU properly?
> 
> > I have some more suggestions for the client driver. But since I don't
> > have to live with them (you do), I can't demand you make those
> > changes. If you like, please feel free to cc me on the next revision of the
> client driver.
> 
> I certainly appreciate any clear and valuable improvement suggestions.
> Just feel free to let me know if any better idea.
> 
> Regards
> Dong Aisheng

Re: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[Jassi Brar]

On Thu, Aug 9, 2018 at 7:52 AM, A.s. Dong <aisheng.dong@nxp.com> wrote:
> Hi Jassi,
>
> Do you have any comments about this reply?
>
I did read your post. And my opinion isn't changed. If mailbox is new
to you, please try to see how other subsystems works, especially SPI,
I2C and DMA.

Thanks.

RE: [PATCH v7 3/6] dt-bindings: mailbox: imx-mu: add generic MU channel support

[A.s. Dong]

> -----Original Message-----
> From: Jassi Brar [mailto:jassisinghbrar@gmail.com]
> Sent: Thursday, August 9, 2018 10:56 AM
[...]
> On Thu, Aug 9, 2018 at 7:52 AM, A.s. Dong <aisheng.dong@nxp.com> wrote:
> > Hi Jassi,
> >
> > Do you have any comments about this reply?
> >
> I did read your post. And my opinion isn't changed. If mailbox is new to you,
> please try to see how other subsystems works, especially SPI, I2C and DMA.
> 

Okay.
What's your comments about the known issues if doing that way?
1) Many unnecessary and meaningless interrupts handling of Tx and RX
2) Performance downgrading
    A 4 word SCU MSG may need 8 interrupts to handle which terribly slow
    down the speed. (Interrupt latency will be terrible if many). SCU msg
    are mostly handled within 10 us.
3) Complex RX flow in order to align with framework design

Are you referring to them as not a real issue?
Or even they're issues/limitations, you would still prefer multi channels way
In order to be consistent with mailbox subsystem by sacrificing the
performance drop?

And to be clear, the working flow you want is exactly as follows, right?
Sending Word 0 ->
Chan 0 interrupt -> (meaningless)
Sending Word 1 ->
Chan1 interrupt -> (meaningless)
Sending Word 2 ->
Chan2 interrupt -> (meaningless)
Sending Word 3 ->
Chan3 interrupt-> (meaningless)

Sending Word 4 on Chan 0 again ->
Wait for Chan 0 interrupt (meaningless) -> ...

Then waiting for Rx:

Chan 0 Rx interrupt ->
Read Word 0   ->
(Then we know response size here)

Chan 1 Rx interrupt ->
Read Word 1 ->
Chan 2 Rx interrupt ->
Read Word 2 ->
Chan 3 Rx interrupt ->
Read Word 3 ->

(If msg size > 4 words)
Chan 0 Rx interrupt ->
Read Word 4

Regards
Dong Aisheng

> Thanks.

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Vladimir Zapolskiy]

On 07/26/2018 02:15 PM, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>> Hi Jassi,
>>
>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>> <o.rempel@pengutronix.de> wrote:
>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>
>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>> ---
>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>> index 113d6ab931ef..5616d2afca45 100644
>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>  Required properties:
>>>>  -------------------
>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips include
>>>> -               imx8qxp, imx8qm.
>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>
>>>
>>> This is not scalable. Do we add every new SoC that contains the same controller?
>>
>> Yes, we do. This is a policy direction from the DT maintainers.
>>
> I would love to read the post/documentation.

Some notes are found in Documentation/devicetree/bindings/ABI.txt

To guarantee "a stable binding" of a compatible property, to avoid
unintentionally added incompatibilities and to fix a list of supported
compatibles in the device driver code there should be a SoC specific
compatible value in the list of 'compatible' property elements.

> Consider the same h/w - controller and platforms, but only the the MU
> chapter said the controller name is, say, 'MU121'. I am sure now you
> will see it correct to call it "fsl,mu121" compatible.
> What changed? just the name, right?
> 
> 
>> If we
>> ever going to want to validate DTs against the binding, all compatibles
>> used in the DTs must be specified in the binding.
>>
>> As we can't really tell if the controller is exactly the same or even
>> has some SoC integration bugs, we generally add a new compatible for
>> each SoC to key off any workarounds necessary in the driver without the
>> need to change the DTs, breaking compatibility.
>>
> I think if the h/w resources and behaviour remain the same and the
> documentation does not call it by a different name -- it is safe to
> assume its the same IP. Especially when the driver is absolutely
> indifferent to the 5 SoC names.
> 
> If/when we find the controller changes, we could revisit the binding
> and add another compatible option and modify the driver to catch that
> and adapt.
> 

Unfortunately it does not work well this way due to limited possibilities
to distinugush different device IPs on different SoCs, if identical
compatibles are given in both cases, and often it is not obvious that
two IPs are different.

--
Best wishes,
Vladimir

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Jassi Brar]

On Thu, Jul 26, 2018 at 5:14 PM, Vladimir Zapolskiy
<vladimir_zapolskiy@mentor.com> wrote:
> On 07/26/2018 02:15 PM, Jassi Brar wrote:
>> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>> Hi Jassi,
>>>
>>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>>> <o.rempel@pengutronix.de> wrote:
>>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>>
>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>> ---
>>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>> index 113d6ab931ef..5616d2afca45 100644
>>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>>  Required properties:
>>>>>  -------------------
>>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips include
>>>>> -               imx8qxp, imx8qm.
>>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>>
>>>>
>>>> This is not scalable. Do we add every new SoC that contains the same controller?
>>>
>>> Yes, we do. This is a policy direction from the DT maintainers.
>>>
>> I would love to read the post/documentation.
>
> Some notes are found in Documentation/devicetree/bindings/ABI.txt
>
Thanks. I have been through the ABI.txt.

> To guarantee "a stable binding" of a compatible property, to avoid
> unintentionally added incompatibilities and to fix a list of supported
> compatibles in the device driver code there should be a SoC specific
> compatible value in the list of 'compatible' property elements.
>
>> Consider the same h/w - controller and platforms, but only the the MU
>> chapter said the controller name is, say, 'MU121'. I am sure now you
>> will see it correct to call it "fsl,mu121" compatible.
>> What changed? just the name, right?
>>
>>
>>> If we
>>> ever going to want to validate DTs against the binding, all compatibles
>>> used in the DTs must be specified in the binding.
>>>
>>> As we can't really tell if the controller is exactly the same or even
>>> has some SoC integration bugs, we generally add a new compatible for
>>> each SoC to key off any workarounds necessary in the driver without the
>>> need to change the DTs, breaking compatibility.
>>>
>> I think if the h/w resources and behaviour remain the same and the
>> documentation does not call it by a different name -- it is safe to
>> assume its the same IP. Especially when the driver is absolutely
>> indifferent to the 5 SoC names.
>>
>> If/when we find the controller changes, we could revisit the binding
>> and add another compatible option and modify the driver to catch that
>> and adapt.
>>
>
> Unfortunately it does not work well this way due to limited possibilities
> to distinugush different device IPs on different SoCs, if identical
> compatibles are given in both cases, and often it is not obvious that
> two IPs are different.
>
Please note the submitted driver absolutely don't care which of the
five SoCs it is.
In other words, all these SoCs have the same controller.  So its about
have just one compatible right now, and add more if some new SoC comes
with a variation of the controller.

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Vladimir Zapolskiy]

On 07/26/2018 02:52 PM, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 5:14 PM, Vladimir Zapolskiy
> <vladimir_zapolskiy@mentor.com> wrote:
>> On 07/26/2018 02:15 PM, Jassi Brar wrote:
>>> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>>> Hi Jassi,
>>>>
>>>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>>>> <o.rempel@pengutronix.de> wrote:
>>>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>>>
>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>>> ---
>>>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> index 113d6ab931ef..5616d2afca45 100644
>>>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>>>  Required properties:
>>>>>>  -------------------
>>>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips include
>>>>>> -               imx8qxp, imx8qm.
>>>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>>>
>>>>>
>>>>> This is not scalable. Do we add every new SoC that contains the same controller?
>>>>
>>>> Yes, we do. This is a policy direction from the DT maintainers.
>>>>
>>> I would love to read the post/documentation.
>>
>> Some notes are found in Documentation/devicetree/bindings/ABI.txt
>>
> Thanks. I have been through the ABI.txt.
> 
>> To guarantee "a stable binding" of a compatible property, to avoid
>> unintentionally added incompatibilities and to fix a list of supported
>> compatibles in the device driver code there should be a SoC specific
>> compatible value in the list of 'compatible' property elements.
>>
>>> Consider the same h/w - controller and platforms, but only the the MU
>>> chapter said the controller name is, say, 'MU121'. I am sure now you
>>> will see it correct to call it "fsl,mu121" compatible.
>>> What changed? just the name, right?
>>>
>>>
>>>> If we
>>>> ever going to want to validate DTs against the binding, all compatibles
>>>> used in the DTs must be specified in the binding.
>>>>
>>>> As we can't really tell if the controller is exactly the same or even
>>>> has some SoC integration bugs, we generally add a new compatible for
>>>> each SoC to key off any workarounds necessary in the driver without the
>>>> need to change the DTs, breaking compatibility.
>>>>
>>> I think if the h/w resources and behaviour remain the same and the
>>> documentation does not call it by a different name -- it is safe to
>>> assume its the same IP. Especially when the driver is absolutely
>>> indifferent to the 5 SoC names.
>>>
>>> If/when we find the controller changes, we could revisit the binding
>>> and add another compatible option and modify the driver to catch that
>>> and adapt.
>>>
>>
>> Unfortunately it does not work well this way due to limited possibilities
>> to distinugush different device IPs on different SoCs, if identical
>> compatibles are given in both cases, and often it is not obvious that
>> two IPs are different.
>>
> Please note the submitted driver absolutely don't care which of the
> five SoCs it is.

True.

> In other words, all these SoCs have the same controller.

False :)

> So its about have just one compatible right now, and add more if some
> new SoC comes with a variation of the controller.
> 

True. The driver will be changed in this case, unfortunately the bindings
are not so volatile.

--
Best wishes,
Vladimir

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Jassi Brar]

On Thu, Jul 26, 2018 at 5:25 PM, Vladimir Zapolskiy
<vladimir_zapolskiy@mentor.com> wrote:
> On 07/26/2018 02:52 PM, Jassi Brar wrote:
>> On Thu, Jul 26, 2018 at 5:14 PM, Vladimir Zapolskiy
>> <vladimir_zapolskiy@mentor.com> wrote:

>>>
>> Please note the submitted driver absolutely don't care which of the
>> five SoCs it is.
>
> True.
>

>> In other words, all these SoCs have the same controller.
>
> False :)
>
OK, so the controllers are not identical, but same enough to have a
common driver?
Is the driver not tested enough or are you planning to add more features?

>> So its about have just one compatible right now, and add more if some
>> new SoC comes with a variation of the controller.
>>
>
> True. The driver will be changed in this case, unfortunately the bindings
> are not so volatile.
>
The volatility of the bindings will be same when you add a new SoC
compatible ;)  And you must add to bindings+driver, or the same h/w
and same driver won't work for your new platform.

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Vladimir Zapolskiy]

On 07/26/2018 03:10 PM, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 5:25 PM, Vladimir Zapolskiy
> <vladimir_zapolskiy-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> wrote:
>> On 07/26/2018 02:52 PM, Jassi Brar wrote:
>>> On Thu, Jul 26, 2018 at 5:14 PM, Vladimir Zapolskiy
>>> <vladimir_zapolskiy-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> wrote:
> 
>>>>
>>> Please note the submitted driver absolutely don't care which of the
>>> five SoCs it is.
>>
>> True.
>>
> 
>>> In other words, all these SoCs have the same controller.
>>
>> False :)
>>

To be more precice, the statement itself may be true or false, but
the implication ("In other words, ...") is definitely false.

> OK, so the controllers are not identical, but same enough to have a
> common driver?

Right, the controllers are compatible, but likely they are non-identical.

> Is the driver not tested enough or are you planning to add more features?
> 

Test results can not serve as a formal eternal proof, but they are good as
a hint. Also I'm not aware of any pending features to be added to the driver.

>>> So its about have just one compatible right now, and add more if some
>>> new SoC comes with a variation of the controller.
>>>
>>
>> True. The driver will be changed in this case, unfortunately the bindings
>> are not so volatile.
>>
> The volatility of the bindings will be same when you add a new SoC
> compatible ;)  And you must add to bindings+driver, or the same h/w
> and same driver won't work for your new platform.
> 

The (non-)volatilitily of the bindings is important only in retrospective
view.

Adding a new compatible to the documentation and unrelated board DTBs is
irrelevant, and it is quite predictable that it will happen, when a new
SoC with the same "compatible" IP is released.

--
Best wishes,
Vladimir

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Vladimir Zapolskiy]

On 07/26/2018 02:46 PM, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 5:05 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>> Am Donnerstag, den 26.07.2018, 16:45 +0530 schrieb Jassi Brar:
>>> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de>
>>> wrote:
>>>> Hi Jassi,
>>>>
>>>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>>>> <o.rempel@pengutronix.de> wrote:
>>>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>>>
>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>>>
>>>>>> ---
>>>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> index 113d6ab931ef..5616d2afca45 100644
>>>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>>>  Required properties:
>>>>>>  -------------------
>>>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips
>>>>>> include
>>>>>> -               imx8qxp, imx8qm.
>>>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>>>
>>>>>
>>>>> This is not scalable. Do we add every new SoC that contains the
>>>>> same controller?
>>>>
>>>> Yes, we do. This is a policy direction from the DT maintainers.
>>>>
>>>
>>> I would love to read the post/documentation.
>>>
>>> Consider the same h/w - controller and platforms, but only the the MU
>>> chapter said the controller name is, say, 'MU121'. I am sure now you
>>> will see it correct to call it "fsl,mu121" compatible.
>>> What changed? just the name, right?
>>>
>>>
>>>> If we
>>>> ever going to want to validate DTs against the binding, all
>>>> compatibles
>>>> used in the DTs must be specified in the binding.
>>>>
>>>> As we can't really tell if the controller is exactly the same or
>>>> even
>>>> has some SoC integration bugs, we generally add a new compatible
>>>> for
>>>> each SoC to key off any workarounds necessary in the driver without
>>>> the
>>>> need to change the DTs, breaking compatibility.
>>>>
>>>
>>> I think if the h/w resources and behaviour remain the same and the
>>> documentation does not call it by a different name -- it is safe to
>>> assume its the same IP. Especially when the driver is absolutely
>>> indifferent to the 5 SoC names.
>>
>> Even if it is the same IP core, the SoC integration might have bugs
>> that need different behavior from the driver. We've already had that
>> case with the i.MX6 SPI controller.
>>
> For h/w quirks/bugs, a new "has-that-bug" property makes better sense.
> Or, if you insist, a new compatible based on the first soc that has
> the buggy block.
> 

How do you propose to handle this property in the driver, if once flashed
DTB does not contain it?

>>> If/when we find the controller changes, we could revisit the binding
>>> and add another compatible option and modify the driver to catch that
>>> and adapt.
>>
>> That's way too late. If we want to keep DTs stable
>>
> How do you keep the DT stable by explicitly defining every new SoC to
> the compatible list in DT, _add_ to the driver.... only to have the
> driver absolutely not care which SoC is it?
> Which is the situation right now with this patchset.
> 

For sake of simplicity you can assume that a driver can be changed in
future, and SoC/board device tree bindings can not be changed ever.

--
Best wishes,
Vladimir

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Jassi Brar]

On Thu, Jul 26, 2018 at 5:21 PM, Vladimir Zapolskiy
<vladimir_zapolskiy@mentor.com> wrote:
> On 07/26/2018 02:46 PM, Jassi Brar wrote:
>> On Thu, Jul 26, 2018 at 5:05 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>> Am Donnerstag, den 26.07.2018, 16:45 +0530 schrieb Jassi Brar:
>>>> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de>
>>>> wrote:
>>>>> Hi Jassi,
>>>>>
>>>>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>>>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>>>>> <o.rempel@pengutronix.de> wrote:
>>>>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>>>>
>>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>>>>
>>>>>>> ---
>>>>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>>
>>>>>>> diff --git
>>>>>>> a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>> b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>> index 113d6ab931ef..5616d2afca45 100644
>>>>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>>>>  Required properties:
>>>>>>>  -------------------
>>>>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips
>>>>>>> include
>>>>>>> -               imx8qxp, imx8qm.
>>>>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>>>>
>>>>>>
>>>>>> This is not scalable. Do we add every new SoC that contains the
>>>>>> same controller?
>>>>>
>>>>> Yes, we do. This is a policy direction from the DT maintainers.
>>>>>
>>>>
>>>> I would love to read the post/documentation.
>>>>
>>>> Consider the same h/w - controller and platforms, but only the the MU
>>>> chapter said the controller name is, say, 'MU121'. I am sure now you
>>>> will see it correct to call it "fsl,mu121" compatible.
>>>> What changed? just the name, right?
>>>>
>>>>
>>>>> If we
>>>>> ever going to want to validate DTs against the binding, all
>>>>> compatibles
>>>>> used in the DTs must be specified in the binding.
>>>>>
>>>>> As we can't really tell if the controller is exactly the same or
>>>>> even
>>>>> has some SoC integration bugs, we generally add a new compatible
>>>>> for
>>>>> each SoC to key off any workarounds necessary in the driver without
>>>>> the
>>>>> need to change the DTs, breaking compatibility.
>>>>>
>>>>
>>>> I think if the h/w resources and behaviour remain the same and the
>>>> documentation does not call it by a different name -- it is safe to
>>>> assume its the same IP. Especially when the driver is absolutely
>>>> indifferent to the 5 SoC names.
>>>
>>> Even if it is the same IP core, the SoC integration might have bugs
>>> that need different behavior from the driver. We've already had that
>>> case with the i.MX6 SPI controller.
>>>
>> For h/w quirks/bugs, a new "has-that-bug" property makes better sense.
>> Or, if you insist, a new compatible based on the first soc that has
>> the buggy block.
>>
>
> How do you propose to handle this property in the driver, if once flashed
> DTB does not contain it?
>
I see, your point is - what if a bug appears only in a particular SoC ?
Well, if the controller is same the bug should appear to all SoCs.
Do you think these SoCs have different versions of MU ?

Re: [PATCH v7 4/6] dt-bindings: mailbox: imx-mu: add i.MX6SX and i.MX7S SoCs.

[Vladimir Zapolskiy]

On 07/26/2018 03:00 PM, Jassi Brar wrote:
> On Thu, Jul 26, 2018 at 5:21 PM, Vladimir Zapolskiy
> <vladimir_zapolskiy@mentor.com> wrote:
>> On 07/26/2018 02:46 PM, Jassi Brar wrote:
>>> On Thu, Jul 26, 2018 at 5:05 PM, Lucas Stach <l.stach@pengutronix.de> wrote:
>>>> Am Donnerstag, den 26.07.2018, 16:45 +0530 schrieb Jassi Brar:
>>>>> On Thu, Jul 26, 2018 at 4:11 PM, Lucas Stach <l.stach@pengutronix.de>
>>>>> wrote:
>>>>>> Hi Jassi,
>>>>>>
>>>>>> Am Donnerstag, den 26.07.2018, 15:25 +0530 schrieb Jassi Brar:
>>>>>>> On Thu, Jul 26, 2018 at 12:23 PM, Oleksij Rempel
>>>>>>>> <o.rempel@pengutronix.de> wrote:
>>>>>>>> This are currently tested SoCs with imx-mailbox driver.
>>>>>>>>
>>>>>>>>>> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
>>>>>>>>
>>>>>>>> ---
>>>>>>>>  Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 +-
>>>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>>>
>>>>>>>> diff --git
>>>>>>>> a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>>> b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>>> index 113d6ab931ef..5616d2afca45 100644
>>>>>>>> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>>> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
>>>>>>>> @@ -18,7 +18,7 @@ Messaging Unit Device Node:
>>>>>>>>  Required properties:
>>>>>>>>  -------------------
>>>>>>>>  - compatible : should be "fsl,<chip>-mu", the supported chips
>>>>>>>> include
>>>>>>>> -               imx8qxp, imx8qm.
>>>>>>>> +               imx6sx, imx7s, imx8qxp, imx8qm.
>>>>>>>>
>>>>>>>
>>>>>>> This is not scalable. Do we add every new SoC that contains the
>>>>>>> same controller?
>>>>>>
>>>>>> Yes, we do. This is a policy direction from the DT maintainers.
>>>>>>
>>>>>
>>>>> I would love to read the post/documentation.
>>>>>
>>>>> Consider the same h/w - controller and platforms, but only the the MU
>>>>> chapter said the controller name is, say, 'MU121'. I am sure now you
>>>>> will see it correct to call it "fsl,mu121" compatible.
>>>>> What changed? just the name, right?
>>>>>
>>>>>
>>>>>> If we
>>>>>> ever going to want to validate DTs against the binding, all
>>>>>> compatibles
>>>>>> used in the DTs must be specified in the binding.
>>>>>>
>>>>>> As we can't really tell if the controller is exactly the same or
>>>>>> even
>>>>>> has some SoC integration bugs, we generally add a new compatible
>>>>>> for
>>>>>> each SoC to key off any workarounds necessary in the driver without
>>>>>> the
>>>>>> need to change the DTs, breaking compatibility.
>>>>>>
>>>>>
>>>>> I think if the h/w resources and behaviour remain the same and the
>>>>> documentation does not call it by a different name -- it is safe to
>>>>> assume its the same IP. Especially when the driver is absolutely
>>>>> indifferent to the 5 SoC names.
>>>>
>>>> Even if it is the same IP core, the SoC integration might have bugs
>>>> that need different behavior from the driver. We've already had that
>>>> case with the i.MX6 SPI controller.
>>>>
>>> For h/w quirks/bugs, a new "has-that-bug" property makes better sense.
>>> Or, if you insist, a new compatible based on the first soc that has
>>> the buggy block.
>>>
>>
>> How do you propose to handle this property in the driver, if once flashed
>> DTB does not contain it?
>>
> I see, your point is - what if a bug appears only in a particular SoC ?
> Well, if the controller is same the bug should appear to all SoCs.
> Do you think these SoCs have different versions of MU ?
> 

I'm not a hardware developer, but I'm quite sure that strictly speaking
IPs are different on different SoCs, the diversity of differences can be
negligible, or it can be discovered in future and considered as
significant, i.e. two IPs may be found as incompatible ones. Note that
the DTBs flashed on boards are already prepared for the worst scenario.

But to some extend, and in today's knowledge, the IPs are compatible,
let's say they are compatible to "fsl,imx6sx-mu" version, the one which
is found in the published driver.

--
Best wishes,
Vladimir