[PATCH 0/4] MIPS16e2 ASE support

[PATCH 0/4] MIPS16e2 ASE support

[Maciej W. Rozycki]

Ralf,

 This patch series adds MIPS16e2 ASE support as per the architecture 
specification[1].  Included there's feature identification, reporting and 
necessary instruction emulation.  These patches have been checked with 
interAptiv MR2 hardware to verify that new MIPS16e2 functions operate 
correctly and with 74Kf hardware to verify that no regression has been 
casued with original MIPS16e support.  See individual descriptions for the 
details of each change made.

 Please queue for the next rc cycle.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

  Maciej

[PATCH 0/4] MIPS16e2 ASE support

[Maciej W. Rozycki]

Ralf,

 This patch series adds MIPS16e2 ASE support as per the architecture 
specification[1].  Included there's feature identification, reporting and 
necessary instruction emulation.  These patches have been checked with 
interAptiv MR2 hardware to verify that new MIPS16e2 functions operate 
correctly and with 74Kf hardware to verify that no regression has been 
casued with original MIPS16e support.  See individual descriptions for the 
details of each change made.

 Please queue for the next rc cycle.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

  Maciej

[PATCH 1/4] MIPS16e2: Identify ASE presence

[Maciej W. Rozycki]

Identify the presence of the MIPS16e2 ASE as per the architecture 
specification[1], by checking for CP0 Config5.CA2 bit being 1[2].

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
    Section 1.2 "Software Detection of the ASE", p. 5

[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision 
    02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 -- 
    Config5 (CP0 Register 16, Select 5)", pp. 71-72

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 NB the designation of the CP0 Config5.CA2 bit has not yet made it to a 
published release of the architecture specification, so the definition in 
the interAptiv MR2 core manual will have to do for the time being.

  Maciej

linux-mips16e2-ase-ident.diff
Index: linux-sfr-test/arch/mips/include/asm/cpu-features.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/cpu-features.h	2017-05-22 22:42:15.904852000 +0100
+++ linux-sfr-test/arch/mips/include/asm/cpu-features.h	2017-05-22 22:48:43.819622000 +0100
@@ -138,6 +138,9 @@
 #ifndef cpu_has_mips16
 #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
+#ifndef cpu_has_mips16e2
+#define cpu_has_mips16e2	(cpu_data[0].ases & MIPS_ASE_MIPS16E2)
+#endif
 #ifndef cpu_has_mdmx
 #define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
 #endif
Index: linux-sfr-test/arch/mips/include/asm/cpu.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/cpu.h	2017-05-22 22:42:15.905865000 +0100
+++ linux-sfr-test/arch/mips/include/asm/cpu.h	2017-05-22 22:48:43.827611000 +0100
@@ -430,5 +430,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
 #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
 #define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/
+#define MIPS_ASE_MIPS16E2	0x00000400 /* MIPS16e2 */
 
 #endif /* _ASM_CPU_H */
Index: linux-sfr-test/arch/mips/include/asm/mipsregs.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mipsregs.h	2017-05-22 22:42:16.046860000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mipsregs.h	2017-05-22 22:48:43.766613000 +0100
@@ -652,6 +652,7 @@
 #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
 #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
 #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
+#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
Index: linux-sfr-test/arch/mips/kernel/cpu-probe.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/cpu-probe.c	2017-05-22 22:41:59.908735000 +0100
+++ linux-sfr-test/arch/mips/kernel/cpu-probe.c	2017-05-22 22:48:43.798611000 +0100
@@ -861,6 +861,8 @@ static inline unsigned int decode_config
 		c->options |= MIPS_CPU_MVH;
 	if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 		c->options |= MIPS_CPU_VP;
+	if (config5 & MIPS_CONF5_CA2)
+		c->ases |= MIPS_ASE_MIPS16E2;
 
 	return config5 & MIPS_CONF_M;
 }

[PATCH 1/4] MIPS16e2: Identify ASE presence

[Maciej W. Rozycki]

Identify the presence of the MIPS16e2 ASE as per the architecture 
specification[1], by checking for CP0 Config5.CA2 bit being 1[2].

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
    Section 1.2 "Software Detection of the ASE", p. 5

[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision 
    02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 -- 
    Config5 (CP0 Register 16, Select 5)", pp. 71-72

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 NB the designation of the CP0 Config5.CA2 bit has not yet made it to a 
published release of the architecture specification, so the definition in 
the interAptiv MR2 core manual will have to do for the time being.

  Maciej

linux-mips16e2-ase-ident.diff
Index: linux-sfr-test/arch/mips/include/asm/cpu-features.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/cpu-features.h	2017-05-22 22:42:15.904852000 +0100
+++ linux-sfr-test/arch/mips/include/asm/cpu-features.h	2017-05-22 22:48:43.819622000 +0100
@@ -138,6 +138,9 @@
 #ifndef cpu_has_mips16
 #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
+#ifndef cpu_has_mips16e2
+#define cpu_has_mips16e2	(cpu_data[0].ases & MIPS_ASE_MIPS16E2)
+#endif
 #ifndef cpu_has_mdmx
 #define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
 #endif
Index: linux-sfr-test/arch/mips/include/asm/cpu.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/cpu.h	2017-05-22 22:42:15.905865000 +0100
+++ linux-sfr-test/arch/mips/include/asm/cpu.h	2017-05-22 22:48:43.827611000 +0100
@@ -430,5 +430,6 @@ enum cpu_type_enum {
 #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
 #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
 #define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/
+#define MIPS_ASE_MIPS16E2	0x00000400 /* MIPS16e2 */
 
 #endif /* _ASM_CPU_H */
Index: linux-sfr-test/arch/mips/include/asm/mipsregs.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mipsregs.h	2017-05-22 22:42:16.046860000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mipsregs.h	2017-05-22 22:48:43.766613000 +0100
@@ -652,6 +652,7 @@
 #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
 #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
 #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
+#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
 #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
 #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
 #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
Index: linux-sfr-test/arch/mips/kernel/cpu-probe.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/cpu-probe.c	2017-05-22 22:41:59.908735000 +0100
+++ linux-sfr-test/arch/mips/kernel/cpu-probe.c	2017-05-22 22:48:43.798611000 +0100
@@ -861,6 +861,8 @@ static inline unsigned int decode_config
 		c->options |= MIPS_CPU_MVH;
 	if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 		c->options |= MIPS_CPU_VP;
+	if (config5 & MIPS_CONF5_CA2)
+		c->ases |= MIPS_ASE_MIPS16E2;
 
 	return config5 & MIPS_CONF_M;
 }

Re: [PATCH 1/4] MIPS16e2: Identify ASE presence

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 3770 bytes --]

On Tue, May 23, 2017 at 01:37:05PM +0100, Maciej W. Rozycki wrote:
> Identify the presence of the MIPS16e2 ASE as per the architecture 
> specification[1], by checking for CP0 Config5.CA2 bit being 1[2].
> 
> References:
> 
> [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
>     Extension Technical Reference Manual", Imagination Technologies
>     Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
>     Section 1.2 "Software Detection of the ASE", p. 5
> 
> [2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
>     Imagination Technologies Ltd., Document Number: MD00904, Revision 
>     02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 -- 
>     Config5 (CP0 Register 16, Select 5)", pp. 71-72
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> ---
>  NB the designation of the CP0 Config5.CA2 bit has not yet made it to a 
> published release of the architecture specification, so the definition in 
> the interAptiv MR2 core manual will have to do for the time being.
> 
>   Maciej
> 
> linux-mips16e2-ase-ident.diff
> Index: linux-sfr-test/arch/mips/include/asm/cpu-features.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu-features.h	2017-05-22 22:42:15.904852000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu-features.h	2017-05-22 22:48:43.819622000 +0100
> @@ -138,6 +138,9 @@
>  #ifndef cpu_has_mips16
>  #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
>  #endif
> +#ifndef cpu_has_mips16e2
> +#define cpu_has_mips16e2	(cpu_data[0].ases & MIPS_ASE_MIPS16E2)
> +#endif
>  #ifndef cpu_has_mdmx
>  #define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
>  #endif
> Index: linux-sfr-test/arch/mips/include/asm/cpu.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu.h	2017-05-22 22:42:15.905865000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu.h	2017-05-22 22:48:43.827611000 +0100
> @@ -430,5 +430,6 @@ enum cpu_type_enum {
>  #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
>  #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
>  #define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/
> +#define MIPS_ASE_MIPS16E2	0x00000400 /* MIPS16e2 */
>  
>  #endif /* _ASM_CPU_H */
> Index: linux-sfr-test/arch/mips/include/asm/mipsregs.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mipsregs.h	2017-05-22 22:42:16.046860000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mipsregs.h	2017-05-22 22:48:43.766613000 +0100
> @@ -652,6 +652,7 @@
>  #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
>  #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
>  #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
> +#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
>  #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
>  #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
>  #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
> Index: linux-sfr-test/arch/mips/kernel/cpu-probe.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/cpu-probe.c	2017-05-22 22:41:59.908735000 +0100
> +++ linux-sfr-test/arch/mips/kernel/cpu-probe.c	2017-05-22 22:48:43.798611000 +0100
> @@ -861,6 +861,8 @@ static inline unsigned int decode_config
>  		c->options |= MIPS_CPU_MVH;
>  	if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
>  		c->options |= MIPS_CPU_VP;
> +	if (config5 & MIPS_CONF5_CA2)
> +		c->ases |= MIPS_ASE_MIPS16E2;
>  
>  	return config5 & MIPS_CONF_M;
>  }

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Re: [PATCH 1/4] MIPS16e2: Identify ASE presence

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 3770 bytes --]

On Tue, May 23, 2017 at 01:37:05PM +0100, Maciej W. Rozycki wrote:
> Identify the presence of the MIPS16e2 ASE as per the architecture 
> specification[1], by checking for CP0 Config5.CA2 bit being 1[2].
> 
> References:
> 
> [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
>     Extension Technical Reference Manual", Imagination Technologies
>     Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016,
>     Section 1.2 "Software Detection of the ASE", p. 5
> 
> [2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
>     Imagination Technologies Ltd., Document Number: MD00904, Revision 
>     02.01, June 15, 2016, Section 2.2.1.6 "Device Configuration 5 -- 
>     Config5 (CP0 Register 16, Select 5)", pp. 71-72
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> ---
>  NB the designation of the CP0 Config5.CA2 bit has not yet made it to a 
> published release of the architecture specification, so the definition in 
> the interAptiv MR2 core manual will have to do for the time being.
> 
>   Maciej
> 
> linux-mips16e2-ase-ident.diff
> Index: linux-sfr-test/arch/mips/include/asm/cpu-features.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu-features.h	2017-05-22 22:42:15.904852000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu-features.h	2017-05-22 22:48:43.819622000 +0100
> @@ -138,6 +138,9 @@
>  #ifndef cpu_has_mips16
>  #define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
>  #endif
> +#ifndef cpu_has_mips16e2
> +#define cpu_has_mips16e2	(cpu_data[0].ases & MIPS_ASE_MIPS16E2)
> +#endif
>  #ifndef cpu_has_mdmx
>  #define cpu_has_mdmx		(cpu_data[0].ases & MIPS_ASE_MDMX)
>  #endif
> Index: linux-sfr-test/arch/mips/include/asm/cpu.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/cpu.h	2017-05-22 22:42:15.905865000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/cpu.h	2017-05-22 22:48:43.827611000 +0100
> @@ -430,5 +430,6 @@ enum cpu_type_enum {
>  #define MIPS_ASE_VZ		0x00000080 /* Virtualization ASE */
>  #define MIPS_ASE_MSA		0x00000100 /* MIPS SIMD Architecture */
>  #define MIPS_ASE_DSP3		0x00000200 /* Signal Processing ASE Rev 3*/
> +#define MIPS_ASE_MIPS16E2	0x00000400 /* MIPS16e2 */
>  
>  #endif /* _ASM_CPU_H */
> Index: linux-sfr-test/arch/mips/include/asm/mipsregs.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mipsregs.h	2017-05-22 22:42:16.046860000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mipsregs.h	2017-05-22 22:48:43.766613000 +0100
> @@ -652,6 +652,7 @@
>  #define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
>  #define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
>  #define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
> +#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
>  #define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
>  #define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
>  #define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
> Index: linux-sfr-test/arch/mips/kernel/cpu-probe.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/cpu-probe.c	2017-05-22 22:41:59.908735000 +0100
> +++ linux-sfr-test/arch/mips/kernel/cpu-probe.c	2017-05-22 22:48:43.798611000 +0100
> @@ -861,6 +861,8 @@ static inline unsigned int decode_config
>  		c->options |= MIPS_CPU_MVH;
>  	if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
>  		c->options |= MIPS_CPU_VP;
> +	if (config5 & MIPS_CONF5_CA2)
> +		c->ases |= MIPS_ASE_MIPS16E2;
>  
>  	return config5 & MIPS_CONF_M;
>  }

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[PATCH 2/4] MIPS16e2: Subdecode extended LWSP/SWSP instructions

[Maciej W. Rozycki]

Implement extended LWSP/SWSP instruction subdecoding for the purpose of 
unaligned GP-relative memory access emulation.

With the introduction of the MIPS16e2 ASE[1] the previously must-be-zero 
3-bit field at bits 7..5 of the extended encodings of the instructions 
selected with the LWSP and SWSP major opcodes has become a `sel' field, 
acting as an opcode extension for additional operations.  In both cases 
the `sel' value of 0 has retained the original operation, that is:

	LW	rx, offset(sp)

and:

	SW	rx, offset(sp)

for LWSP and SWSP respectively.  In hardware predating the MIPS16e2 ASE 
other values may or may not have been decoded, architecturally yielding 
unpredictable results, and in our unaligned memory access emulation we 
have treated the 3-bit field as a don't-care, that is effectively making 
all the possible encodings of the field alias to the architecturally 
defined encoding of 0.

For the non-zero values of the `sel' field the MIPS16e2 ASE has in 
particular defined these GP-relative operations:

	LW	rx, offset(gp)		# sel = 1
	LH	rx, offset(gp)		# sel = 2
	LHU	rx, offset(gp)		# sel = 4

and

	SW	rx, offset(gp)		# sel = 1
	SH	rx, offset(gp)		# sel = 2

for LWSP and SWSP respectively, which will trap with an Address Error 
exception if the effective address calculated is not naturally-aligned 
for the operation requested.  These operations have been selected for 
unaligned access emulation, for consistency with the corresponding 
regular MIPS and microMIPS operations.

For other non-zero values of the `sel' field the MIPS16e2 ASE has 
defined further operations, which however either never trap with an 
Address Error exception, such as LWL or GP-relative SB, or are not 
supposed to be emulated, such as LL or SC.  These operations have been 
selected to exclude from unaligned access emulation, should an Address 
Error exception ever happen with them.

Subdecode the `sel' field in unaligned access emulation then for the 
extended encodings of the instructions selected with the LWSP and SWSP 
major opcodes, whenever support for the MIPS16e2 ASE has been detected 
in hardware, and either emulate the operation requested or send SIGBUS 
to the originating process, according to the selection described above.  
For hardware implementing the MIPS16 ASE, however lacking MIPS16e2 ASE 
support retain the original interpretation of the `sel' field.

The effects of this change are illustrated with the following user 
program:

$ cat mips16e2-test.c
#include <inttypes.h>
#include <stdio.h>

int main(void)
{
	int64_t scratch[16] = { 0 };
	int32_t *tmp0, *tmp1, *tmp2;
	int i;

	scratch[0] = 0xc8c7c6c5c4c3c2c1;
	scratch[1] = 0xd0cfcecdcccbcac9;

	asm volatile(
		"move	%0, $sp\n\t"
		"move	%1, $gp\n\t"
		"move	$sp, %4\n\t"
		"addiu	%2, %4, 8\n\t"
		"move	$gp, %2\n\t"

		"lw	%2, 2($sp)\n\t"
		"sw	%2, 16(%4)\n\t"
		"lw	%2, 2($gp)\n\t"
		"sw	%2, 24(%4)\n\t"

		"lw	%2, 1($sp)\n\t"
		"sw	%2, 32(%4)\n\t"
		"lh	%2, 1($gp)\n\t"
		"sw	%2, 40(%4)\n\t"

		"lw	%2, 3($sp)\n\t"
		"sw	%2, 48(%4)\n\t"
		"lhu	%2, 3($gp)\n\t"
		"sw	%2, 56(%4)\n\t"

		"lw	%2, 0(%4)\n\t"
		"sw	%2, 66($sp)\n\t"
		"lw	%2, 8(%4)\n\t"
		"sw	%2, 82($gp)\n\t"

		"lw	%2, 0(%4)\n\t"
		"sw	%2, 97($sp)\n\t"
		"lw	%2, 8(%4)\n\t"
		"sh	%2, 113($gp)\n\t"

		"move	$gp, %1\n\t"
		"move	$sp, %0"
		: "=&d" (tmp0), "=&d" (tmp1), "=&d" (tmp2), "=m" (scratch)
		: "d" (scratch));

	for (i = 0; i < sizeof(scratch) / sizeof(*scratch); i += 2)
		printf("%016" PRIx64 "\t%016" PRIx64 "\n",
		       scratch[i], scratch[i + 1]);

	return 0;
}
$

to be compiled with:

$ gcc -mips16 -mips32r2 -Wa,-mmips16e2 -o mips16e2-test mips16e2-test.c
$

With 74Kf hardware, which does not implement the MIPS16e2 ASE, this 
program produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000c6c5c4c3
00000000c5c4c3c2        00000000c5c4c3c2
00000000c7c6c5c4        00000000c7c6c5c4
0000c4c3c2c10000        0000000000000000
0000cccbcac90000        0000000000000000
000000c4c3c2c100        0000000000000000
000000cccbcac900        0000000000000000
$ 

regardless of whether the change has been applied or not.

With the change not applied and interAptive MR2 hardware[2], which does 
implement the MIPS16e2 ASE, it produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000cecdcccb
00000000c5c4c3c2        00000000cdcccbca
00000000c7c6c5c4        00000000cfcecdcc
0000c4c3c2c10000        0000000000000000
0000000000000000        0000cccbcac90000
000000c4c3c2c100        0000000000000000
0000000000000000        000000cccbcac900
$ 

which shows that for GP-relative operations the correct trapping address 
calculated from $gp has been obtained from the CP0 BadVAddr register and 
so has data from the source operand, however masking and extension has 
not been applied for halfword operations.

With the change applied and interAptive MR2 hardware the program 
produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000cecdcccb
00000000c5c4c3c2        00000000ffffcbca
00000000c7c6c5c4        000000000000cdcc
0000c4c3c2c10000        0000000000000000
0000000000000000        0000cccbcac90000
000000c4c3c2c100        0000000000000000
0000000000000000        0000000000cac900
$ 

as expected.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Chapter 24 "MIPS16e Application-Specific 
    Extension to the MIPS32 Instruction Set", pp. 871-883

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 NB a recent binutils version, as from commit 25499ac7ee92 ("MIPS16e2: 
Add MIPS16e2 ASE support"), is required to build the test program.

  Maciej

linux-mips16e2-ase-emul.diff
Index: linux-sfr-test/arch/mips/kernel/unaligned.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/unaligned.c	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/unaligned.c	2017-05-22 22:54:28.686096000 +0100
@@ -1984,6 +1984,8 @@ static void emulate_load_store_MIPS16e(s
 	u16 __user *pc16;
 	unsigned long origpc;
 	union mips16e_instruction mips16inst, oldinst;
+	unsigned int opcode;
+	int extended = 0;
 
 	origpc = regs->cp0_epc;
 	orig31 = regs->regs[31];
@@ -1996,6 +1998,7 @@ static void emulate_load_store_MIPS16e(s
 
 	/* skip EXTEND instruction */
 	if (mips16inst.ri.opcode == MIPS16e_extend_op) {
+		extended = 1;
 		pc16++;
 		__get_user(mips16inst.full, pc16);
 	} else if (delay_slot(regs)) {
@@ -2008,7 +2011,8 @@ static void emulate_load_store_MIPS16e(s
 			goto sigbus;
 	}
 
-	switch (mips16inst.ri.opcode) {
+	opcode = mips16inst.ri.opcode;
+	switch (opcode) {
 	case MIPS16e_i64_op:	/* I64 or RI64 instruction */
 		switch (mips16inst.i64.func) {	/* I64/RI64 func field check */
 		case MIPS16e_ldpc_func:
@@ -2028,9 +2032,40 @@ static void emulate_load_store_MIPS16e(s
 		goto sigbus;
 
 	case MIPS16e_swsp_op:
+		reg = reg16to32[mips16inst.ri.rx];
+		if (extended && cpu_has_mips16e2)
+			switch (mips16inst.ri.imm >> 5) {
+			case 0:		/* SWSP */
+			case 1:		/* SWGP */
+				break;
+			case 2:		/* SHGP */
+				opcode = MIPS16e_sh_op;
+				break;
+			default:
+				goto sigbus;
+			}
+		break;
+
 	case MIPS16e_lwpc_op:
+		reg = reg16to32[mips16inst.ri.rx];
+		break;
+
 	case MIPS16e_lwsp_op:
 		reg = reg16to32[mips16inst.ri.rx];
+		if (extended && cpu_has_mips16e2)
+			switch (mips16inst.ri.imm >> 5) {
+			case 0:		/* LWSP */
+			case 1:		/* LWGP */
+				break;
+			case 2:		/* LHGP */
+				opcode = MIPS16e_lh_op;
+				break;
+			case 4:		/* LHUGP */
+				opcode = MIPS16e_lhu_op;
+				break;
+			default:
+				goto sigbus;
+			}
 		break;
 
 	case MIPS16e_i8_op:
@@ -2044,7 +2079,7 @@ static void emulate_load_store_MIPS16e(s
 		break;
 	}
 
-	switch (mips16inst.ri.opcode) {
+	switch (opcode) {
 
 	case MIPS16e_lb_op:
 	case MIPS16e_lbu_op:

[PATCH 2/4] MIPS16e2: Subdecode extended LWSP/SWSP instructions

[Maciej W. Rozycki]

Implement extended LWSP/SWSP instruction subdecoding for the purpose of 
unaligned GP-relative memory access emulation.

With the introduction of the MIPS16e2 ASE[1] the previously must-be-zero 
3-bit field at bits 7..5 of the extended encodings of the instructions 
selected with the LWSP and SWSP major opcodes has become a `sel' field, 
acting as an opcode extension for additional operations.  In both cases 
the `sel' value of 0 has retained the original operation, that is:

	LW	rx, offset(sp)

and:

	SW	rx, offset(sp)

for LWSP and SWSP respectively.  In hardware predating the MIPS16e2 ASE 
other values may or may not have been decoded, architecturally yielding 
unpredictable results, and in our unaligned memory access emulation we 
have treated the 3-bit field as a don't-care, that is effectively making 
all the possible encodings of the field alias to the architecturally 
defined encoding of 0.

For the non-zero values of the `sel' field the MIPS16e2 ASE has in 
particular defined these GP-relative operations:

	LW	rx, offset(gp)		# sel = 1
	LH	rx, offset(gp)		# sel = 2
	LHU	rx, offset(gp)		# sel = 4

and

	SW	rx, offset(gp)		# sel = 1
	SH	rx, offset(gp)		# sel = 2

for LWSP and SWSP respectively, which will trap with an Address Error 
exception if the effective address calculated is not naturally-aligned 
for the operation requested.  These operations have been selected for 
unaligned access emulation, for consistency with the corresponding 
regular MIPS and microMIPS operations.

For other non-zero values of the `sel' field the MIPS16e2 ASE has 
defined further operations, which however either never trap with an 
Address Error exception, such as LWL or GP-relative SB, or are not 
supposed to be emulated, such as LL or SC.  These operations have been 
selected to exclude from unaligned access emulation, should an Address 
Error exception ever happen with them.

Subdecode the `sel' field in unaligned access emulation then for the 
extended encodings of the instructions selected with the LWSP and SWSP 
major opcodes, whenever support for the MIPS16e2 ASE has been detected 
in hardware, and either emulate the operation requested or send SIGBUS 
to the originating process, according to the selection described above.  
For hardware implementing the MIPS16 ASE, however lacking MIPS16e2 ASE 
support retain the original interpretation of the `sel' field.

The effects of this change are illustrated with the following user 
program:

$ cat mips16e2-test.c
#include <inttypes.h>
#include <stdio.h>

int main(void)
{
	int64_t scratch[16] = { 0 };
	int32_t *tmp0, *tmp1, *tmp2;
	int i;

	scratch[0] = 0xc8c7c6c5c4c3c2c1;
	scratch[1] = 0xd0cfcecdcccbcac9;

	asm volatile(
		"move	%0, $sp\n\t"
		"move	%1, $gp\n\t"
		"move	$sp, %4\n\t"
		"addiu	%2, %4, 8\n\t"
		"move	$gp, %2\n\t"

		"lw	%2, 2($sp)\n\t"
		"sw	%2, 16(%4)\n\t"
		"lw	%2, 2($gp)\n\t"
		"sw	%2, 24(%4)\n\t"

		"lw	%2, 1($sp)\n\t"
		"sw	%2, 32(%4)\n\t"
		"lh	%2, 1($gp)\n\t"
		"sw	%2, 40(%4)\n\t"

		"lw	%2, 3($sp)\n\t"
		"sw	%2, 48(%4)\n\t"
		"lhu	%2, 3($gp)\n\t"
		"sw	%2, 56(%4)\n\t"

		"lw	%2, 0(%4)\n\t"
		"sw	%2, 66($sp)\n\t"
		"lw	%2, 8(%4)\n\t"
		"sw	%2, 82($gp)\n\t"

		"lw	%2, 0(%4)\n\t"
		"sw	%2, 97($sp)\n\t"
		"lw	%2, 8(%4)\n\t"
		"sh	%2, 113($gp)\n\t"

		"move	$gp, %1\n\t"
		"move	$sp, %0"
		: "=&d" (tmp0), "=&d" (tmp1), "=&d" (tmp2), "=m" (scratch)
		: "d" (scratch));

	for (i = 0; i < sizeof(scratch) / sizeof(*scratch); i += 2)
		printf("%016" PRIx64 "\t%016" PRIx64 "\n",
		       scratch[i], scratch[i + 1]);

	return 0;
}
$

to be compiled with:

$ gcc -mips16 -mips32r2 -Wa,-mmips16e2 -o mips16e2-test mips16e2-test.c
$

With 74Kf hardware, which does not implement the MIPS16e2 ASE, this 
program produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000c6c5c4c3
00000000c5c4c3c2        00000000c5c4c3c2
00000000c7c6c5c4        00000000c7c6c5c4
0000c4c3c2c10000        0000000000000000
0000cccbcac90000        0000000000000000
000000c4c3c2c100        0000000000000000
000000cccbcac900        0000000000000000
$ 

regardless of whether the change has been applied or not.

With the change not applied and interAptive MR2 hardware[2], which does 
implement the MIPS16e2 ASE, it produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000cecdcccb
00000000c5c4c3c2        00000000cdcccbca
00000000c7c6c5c4        00000000cfcecdcc
0000c4c3c2c10000        0000000000000000
0000000000000000        0000cccbcac90000
000000c4c3c2c100        0000000000000000
0000000000000000        000000cccbcac900
$ 

which shows that for GP-relative operations the correct trapping address 
calculated from $gp has been obtained from the CP0 BadVAddr register and 
so has data from the source operand, however masking and extension has 
not been applied for halfword operations.

With the change applied and interAptive MR2 hardware the program 
produces the following output:

$ ./mips16e2-test
c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
00000000c6c5c4c3        00000000cecdcccb
00000000c5c4c3c2        00000000ffffcbca
00000000c7c6c5c4        000000000000cdcc
0000c4c3c2c10000        0000000000000000
0000000000000000        0000cccbcac90000
000000c4c3c2c100        0000000000000000
0000000000000000        0000000000cac900
$ 

as expected.

References:

[1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
    Extension Technical Reference Manual", Imagination Technologies
    Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016

[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
    Imagination Technologies Ltd., Document Number: MD00904, Revision
    02.01, June 15, 2016, Chapter 24 "MIPS16e Application-Specific 
    Extension to the MIPS32 Instruction Set", pp. 871-883

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 NB a recent binutils version, as from commit 25499ac7ee92 ("MIPS16e2: 
Add MIPS16e2 ASE support"), is required to build the test program.

  Maciej

linux-mips16e2-ase-emul.diff
Index: linux-sfr-test/arch/mips/kernel/unaligned.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/unaligned.c	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/unaligned.c	2017-05-22 22:54:28.686096000 +0100
@@ -1984,6 +1984,8 @@ static void emulate_load_store_MIPS16e(s
 	u16 __user *pc16;
 	unsigned long origpc;
 	union mips16e_instruction mips16inst, oldinst;
+	unsigned int opcode;
+	int extended = 0;
 
 	origpc = regs->cp0_epc;
 	orig31 = regs->regs[31];
@@ -1996,6 +1998,7 @@ static void emulate_load_store_MIPS16e(s
 
 	/* skip EXTEND instruction */
 	if (mips16inst.ri.opcode == MIPS16e_extend_op) {
+		extended = 1;
 		pc16++;
 		__get_user(mips16inst.full, pc16);
 	} else if (delay_slot(regs)) {
@@ -2008,7 +2011,8 @@ static void emulate_load_store_MIPS16e(s
 			goto sigbus;
 	}
 
-	switch (mips16inst.ri.opcode) {
+	opcode = mips16inst.ri.opcode;
+	switch (opcode) {
 	case MIPS16e_i64_op:	/* I64 or RI64 instruction */
 		switch (mips16inst.i64.func) {	/* I64/RI64 func field check */
 		case MIPS16e_ldpc_func:
@@ -2028,9 +2032,40 @@ static void emulate_load_store_MIPS16e(s
 		goto sigbus;
 
 	case MIPS16e_swsp_op:
+		reg = reg16to32[mips16inst.ri.rx];
+		if (extended && cpu_has_mips16e2)
+			switch (mips16inst.ri.imm >> 5) {
+			case 0:		/* SWSP */
+			case 1:		/* SWGP */
+				break;
+			case 2:		/* SHGP */
+				opcode = MIPS16e_sh_op;
+				break;
+			default:
+				goto sigbus;
+			}
+		break;
+
 	case MIPS16e_lwpc_op:
+		reg = reg16to32[mips16inst.ri.rx];
+		break;
+
 	case MIPS16e_lwsp_op:
 		reg = reg16to32[mips16inst.ri.rx];
+		if (extended && cpu_has_mips16e2)
+			switch (mips16inst.ri.imm >> 5) {
+			case 0:		/* LWSP */
+			case 1:		/* LWGP */
+				break;
+			case 2:		/* LHGP */
+				opcode = MIPS16e_lh_op;
+				break;
+			case 4:		/* LHUGP */
+				opcode = MIPS16e_lhu_op;
+				break;
+			default:
+				goto sigbus;
+			}
 		break;
 
 	case MIPS16e_i8_op:
@@ -2044,7 +2079,7 @@ static void emulate_load_store_MIPS16e(s
 		break;
 	}
 
-	switch (mips16inst.ri.opcode) {
+	switch (opcode) {
 
 	case MIPS16e_lb_op:
 	case MIPS16e_lbu_op:

Re: [PATCH 2/4] MIPS16e2: Subdecode extended LWSP/SWSP instructions

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 9340 bytes --]

On Tue, May 23, 2017 at 01:38:19PM +0100, Maciej W. Rozycki wrote:
> Implement extended LWSP/SWSP instruction subdecoding for the purpose of 
> unaligned GP-relative memory access emulation.
> 
> With the introduction of the MIPS16e2 ASE[1] the previously must-be-zero 
> 3-bit field at bits 7..5 of the extended encodings of the instructions 
> selected with the LWSP and SWSP major opcodes has become a `sel' field, 
> acting as an opcode extension for additional operations.  In both cases 
> the `sel' value of 0 has retained the original operation, that is:
> 
> 	LW	rx, offset(sp)
> 
> and:
> 
> 	SW	rx, offset(sp)
> 
> for LWSP and SWSP respectively.  In hardware predating the MIPS16e2 ASE 
> other values may or may not have been decoded, architecturally yielding 
> unpredictable results, and in our unaligned memory access emulation we 
> have treated the 3-bit field as a don't-care, that is effectively making 
> all the possible encodings of the field alias to the architecturally 
> defined encoding of 0.
> 
> For the non-zero values of the `sel' field the MIPS16e2 ASE has in 
> particular defined these GP-relative operations:
> 
> 	LW	rx, offset(gp)		# sel = 1
> 	LH	rx, offset(gp)		# sel = 2
> 	LHU	rx, offset(gp)		# sel = 4
> 
> and
> 
> 	SW	rx, offset(gp)		# sel = 1
> 	SH	rx, offset(gp)		# sel = 2
> 
> for LWSP and SWSP respectively, which will trap with an Address Error 
> exception if the effective address calculated is not naturally-aligned 
> for the operation requested.  These operations have been selected for 
> unaligned access emulation, for consistency with the corresponding 
> regular MIPS and microMIPS operations.
> 
> For other non-zero values of the `sel' field the MIPS16e2 ASE has 
> defined further operations, which however either never trap with an 
> Address Error exception, such as LWL or GP-relative SB, or are not 
> supposed to be emulated, such as LL or SC.  These operations have been 
> selected to exclude from unaligned access emulation, should an Address 
> Error exception ever happen with them.
> 
> Subdecode the `sel' field in unaligned access emulation then for the 
> extended encodings of the instructions selected with the LWSP and SWSP 
> major opcodes, whenever support for the MIPS16e2 ASE has been detected 
> in hardware, and either emulate the operation requested or send SIGBUS 
> to the originating process, according to the selection described above.  
> For hardware implementing the MIPS16 ASE, however lacking MIPS16e2 ASE 
> support retain the original interpretation of the `sel' field.
> 
> The effects of this change are illustrated with the following user 
> program:

Very descriptive, but I must admit a got a bit bored of reading and
skipped to the code at this point, which looks correct, so

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> 
> $ cat mips16e2-test.c
> #include <inttypes.h>
> #include <stdio.h>
> 
> int main(void)
> {
> 	int64_t scratch[16] = { 0 };
> 	int32_t *tmp0, *tmp1, *tmp2;
> 	int i;
> 
> 	scratch[0] = 0xc8c7c6c5c4c3c2c1;
> 	scratch[1] = 0xd0cfcecdcccbcac9;
> 
> 	asm volatile(
> 		"move	%0, $sp\n\t"
> 		"move	%1, $gp\n\t"
> 		"move	$sp, %4\n\t"
> 		"addiu	%2, %4, 8\n\t"
> 		"move	$gp, %2\n\t"
> 
> 		"lw	%2, 2($sp)\n\t"
> 		"sw	%2, 16(%4)\n\t"
> 		"lw	%2, 2($gp)\n\t"
> 		"sw	%2, 24(%4)\n\t"
> 
> 		"lw	%2, 1($sp)\n\t"
> 		"sw	%2, 32(%4)\n\t"
> 		"lh	%2, 1($gp)\n\t"
> 		"sw	%2, 40(%4)\n\t"
> 
> 		"lw	%2, 3($sp)\n\t"
> 		"sw	%2, 48(%4)\n\t"
> 		"lhu	%2, 3($gp)\n\t"
> 		"sw	%2, 56(%4)\n\t"
> 
> 		"lw	%2, 0(%4)\n\t"
> 		"sw	%2, 66($sp)\n\t"
> 		"lw	%2, 8(%4)\n\t"
> 		"sw	%2, 82($gp)\n\t"
> 
> 		"lw	%2, 0(%4)\n\t"
> 		"sw	%2, 97($sp)\n\t"
> 		"lw	%2, 8(%4)\n\t"
> 		"sh	%2, 113($gp)\n\t"
> 
> 		"move	$gp, %1\n\t"
> 		"move	$sp, %0"
> 		: "=&d" (tmp0), "=&d" (tmp1), "=&d" (tmp2), "=m" (scratch)
> 		: "d" (scratch));
> 
> 	for (i = 0; i < sizeof(scratch) / sizeof(*scratch); i += 2)
> 		printf("%016" PRIx64 "\t%016" PRIx64 "\n",
> 		       scratch[i], scratch[i + 1]);
> 
> 	return 0;
> }
> $
> 
> to be compiled with:
> 
> $ gcc -mips16 -mips32r2 -Wa,-mmips16e2 -o mips16e2-test mips16e2-test.c
> $
> 
> With 74Kf hardware, which does not implement the MIPS16e2 ASE, this 
> program produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000c6c5c4c3
> 00000000c5c4c3c2        00000000c5c4c3c2
> 00000000c7c6c5c4        00000000c7c6c5c4
> 0000c4c3c2c10000        0000000000000000
> 0000cccbcac90000        0000000000000000
> 000000c4c3c2c100        0000000000000000
> 000000cccbcac900        0000000000000000
> $ 
> 
> regardless of whether the change has been applied or not.
> 
> With the change not applied and interAptive MR2 hardware[2], which does 
> implement the MIPS16e2 ASE, it produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000cecdcccb
> 00000000c5c4c3c2        00000000cdcccbca
> 00000000c7c6c5c4        00000000cfcecdcc
> 0000c4c3c2c10000        0000000000000000
> 0000000000000000        0000cccbcac90000
> 000000c4c3c2c100        0000000000000000
> 0000000000000000        000000cccbcac900
> $ 
> 
> which shows that for GP-relative operations the correct trapping address 
> calculated from $gp has been obtained from the CP0 BadVAddr register and 
> so has data from the source operand, however masking and extension has 
> not been applied for halfword operations.
> 
> With the change applied and interAptive MR2 hardware the program 
> produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000cecdcccb
> 00000000c5c4c3c2        00000000ffffcbca
> 00000000c7c6c5c4        000000000000cdcc
> 0000c4c3c2c10000        0000000000000000
> 0000000000000000        0000cccbcac90000
> 000000c4c3c2c100        0000000000000000
> 0000000000000000        0000000000cac900
> $ 
> 
> as expected.
> 
> References:
> 
> [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
>     Extension Technical Reference Manual", Imagination Technologies
>     Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
> 
> [2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
>     Imagination Technologies Ltd., Document Number: MD00904, Revision
>     02.01, June 15, 2016, Chapter 24 "MIPS16e Application-Specific 
>     Extension to the MIPS32 Instruction Set", pp. 871-883
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
>  NB a recent binutils version, as from commit 25499ac7ee92 ("MIPS16e2: 
> Add MIPS16e2 ASE support"), is required to build the test program.
> 
>   Maciej
> 
> linux-mips16e2-ase-emul.diff
> Index: linux-sfr-test/arch/mips/kernel/unaligned.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/unaligned.c	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/kernel/unaligned.c	2017-05-22 22:54:28.686096000 +0100
> @@ -1984,6 +1984,8 @@ static void emulate_load_store_MIPS16e(s
>  	u16 __user *pc16;
>  	unsigned long origpc;
>  	union mips16e_instruction mips16inst, oldinst;
> +	unsigned int opcode;
> +	int extended = 0;
>  
>  	origpc = regs->cp0_epc;
>  	orig31 = regs->regs[31];
> @@ -1996,6 +1998,7 @@ static void emulate_load_store_MIPS16e(s
>  
>  	/* skip EXTEND instruction */
>  	if (mips16inst.ri.opcode == MIPS16e_extend_op) {
> +		extended = 1;
>  		pc16++;
>  		__get_user(mips16inst.full, pc16);
>  	} else if (delay_slot(regs)) {
> @@ -2008,7 +2011,8 @@ static void emulate_load_store_MIPS16e(s
>  			goto sigbus;
>  	}
>  
> -	switch (mips16inst.ri.opcode) {
> +	opcode = mips16inst.ri.opcode;
> +	switch (opcode) {
>  	case MIPS16e_i64_op:	/* I64 or RI64 instruction */
>  		switch (mips16inst.i64.func) {	/* I64/RI64 func field check */
>  		case MIPS16e_ldpc_func:
> @@ -2028,9 +2032,40 @@ static void emulate_load_store_MIPS16e(s
>  		goto sigbus;
>  
>  	case MIPS16e_swsp_op:
> +		reg = reg16to32[mips16inst.ri.rx];
> +		if (extended && cpu_has_mips16e2)
> +			switch (mips16inst.ri.imm >> 5) {
> +			case 0:		/* SWSP */
> +			case 1:		/* SWGP */
> +				break;
> +			case 2:		/* SHGP */
> +				opcode = MIPS16e_sh_op;
> +				break;
> +			default:
> +				goto sigbus;
> +			}
> +		break;
> +
>  	case MIPS16e_lwpc_op:
> +		reg = reg16to32[mips16inst.ri.rx];
> +		break;
> +
>  	case MIPS16e_lwsp_op:
>  		reg = reg16to32[mips16inst.ri.rx];
> +		if (extended && cpu_has_mips16e2)
> +			switch (mips16inst.ri.imm >> 5) {
> +			case 0:		/* LWSP */
> +			case 1:		/* LWGP */
> +				break;
> +			case 2:		/* LHGP */
> +				opcode = MIPS16e_lh_op;
> +				break;
> +			case 4:		/* LHUGP */
> +				opcode = MIPS16e_lhu_op;
> +				break;
> +			default:
> +				goto sigbus;
> +			}
>  		break;
>  
>  	case MIPS16e_i8_op:
> @@ -2044,7 +2079,7 @@ static void emulate_load_store_MIPS16e(s
>  		break;
>  	}
>  
> -	switch (mips16inst.ri.opcode) {
> +	switch (opcode) {
>  
>  	case MIPS16e_lb_op:
>  	case MIPS16e_lbu_op:

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Re: [PATCH 2/4] MIPS16e2: Subdecode extended LWSP/SWSP instructions

[James Hogan]

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On Tue, May 23, 2017 at 01:38:19PM +0100, Maciej W. Rozycki wrote:
> Implement extended LWSP/SWSP instruction subdecoding for the purpose of 
> unaligned GP-relative memory access emulation.
> 
> With the introduction of the MIPS16e2 ASE[1] the previously must-be-zero 
> 3-bit field at bits 7..5 of the extended encodings of the instructions 
> selected with the LWSP and SWSP major opcodes has become a `sel' field, 
> acting as an opcode extension for additional operations.  In both cases 
> the `sel' value of 0 has retained the original operation, that is:
> 
> 	LW	rx, offset(sp)
> 
> and:
> 
> 	SW	rx, offset(sp)
> 
> for LWSP and SWSP respectively.  In hardware predating the MIPS16e2 ASE 
> other values may or may not have been decoded, architecturally yielding 
> unpredictable results, and in our unaligned memory access emulation we 
> have treated the 3-bit field as a don't-care, that is effectively making 
> all the possible encodings of the field alias to the architecturally 
> defined encoding of 0.
> 
> For the non-zero values of the `sel' field the MIPS16e2 ASE has in 
> particular defined these GP-relative operations:
> 
> 	LW	rx, offset(gp)		# sel = 1
> 	LH	rx, offset(gp)		# sel = 2
> 	LHU	rx, offset(gp)		# sel = 4
> 
> and
> 
> 	SW	rx, offset(gp)		# sel = 1
> 	SH	rx, offset(gp)		# sel = 2
> 
> for LWSP and SWSP respectively, which will trap with an Address Error 
> exception if the effective address calculated is not naturally-aligned 
> for the operation requested.  These operations have been selected for 
> unaligned access emulation, for consistency with the corresponding 
> regular MIPS and microMIPS operations.
> 
> For other non-zero values of the `sel' field the MIPS16e2 ASE has 
> defined further operations, which however either never trap with an 
> Address Error exception, such as LWL or GP-relative SB, or are not 
> supposed to be emulated, such as LL or SC.  These operations have been 
> selected to exclude from unaligned access emulation, should an Address 
> Error exception ever happen with them.
> 
> Subdecode the `sel' field in unaligned access emulation then for the 
> extended encodings of the instructions selected with the LWSP and SWSP 
> major opcodes, whenever support for the MIPS16e2 ASE has been detected 
> in hardware, and either emulate the operation requested or send SIGBUS 
> to the originating process, according to the selection described above.  
> For hardware implementing the MIPS16 ASE, however lacking MIPS16e2 ASE 
> support retain the original interpretation of the `sel' field.
> 
> The effects of this change are illustrated with the following user 
> program:

Very descriptive, but I must admit a got a bit bored of reading and
skipped to the code at this point, which looks correct, so

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> 
> $ cat mips16e2-test.c
> #include <inttypes.h>
> #include <stdio.h>
> 
> int main(void)
> {
> 	int64_t scratch[16] = { 0 };
> 	int32_t *tmp0, *tmp1, *tmp2;
> 	int i;
> 
> 	scratch[0] = 0xc8c7c6c5c4c3c2c1;
> 	scratch[1] = 0xd0cfcecdcccbcac9;
> 
> 	asm volatile(
> 		"move	%0, $sp\n\t"
> 		"move	%1, $gp\n\t"
> 		"move	$sp, %4\n\t"
> 		"addiu	%2, %4, 8\n\t"
> 		"move	$gp, %2\n\t"
> 
> 		"lw	%2, 2($sp)\n\t"
> 		"sw	%2, 16(%4)\n\t"
> 		"lw	%2, 2($gp)\n\t"
> 		"sw	%2, 24(%4)\n\t"
> 
> 		"lw	%2, 1($sp)\n\t"
> 		"sw	%2, 32(%4)\n\t"
> 		"lh	%2, 1($gp)\n\t"
> 		"sw	%2, 40(%4)\n\t"
> 
> 		"lw	%2, 3($sp)\n\t"
> 		"sw	%2, 48(%4)\n\t"
> 		"lhu	%2, 3($gp)\n\t"
> 		"sw	%2, 56(%4)\n\t"
> 
> 		"lw	%2, 0(%4)\n\t"
> 		"sw	%2, 66($sp)\n\t"
> 		"lw	%2, 8(%4)\n\t"
> 		"sw	%2, 82($gp)\n\t"
> 
> 		"lw	%2, 0(%4)\n\t"
> 		"sw	%2, 97($sp)\n\t"
> 		"lw	%2, 8(%4)\n\t"
> 		"sh	%2, 113($gp)\n\t"
> 
> 		"move	$gp, %1\n\t"
> 		"move	$sp, %0"
> 		: "=&d" (tmp0), "=&d" (tmp1), "=&d" (tmp2), "=m" (scratch)
> 		: "d" (scratch));
> 
> 	for (i = 0; i < sizeof(scratch) / sizeof(*scratch); i += 2)
> 		printf("%016" PRIx64 "\t%016" PRIx64 "\n",
> 		       scratch[i], scratch[i + 1]);
> 
> 	return 0;
> }
> $
> 
> to be compiled with:
> 
> $ gcc -mips16 -mips32r2 -Wa,-mmips16e2 -o mips16e2-test mips16e2-test.c
> $
> 
> With 74Kf hardware, which does not implement the MIPS16e2 ASE, this 
> program produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000c6c5c4c3
> 00000000c5c4c3c2        00000000c5c4c3c2
> 00000000c7c6c5c4        00000000c7c6c5c4
> 0000c4c3c2c10000        0000000000000000
> 0000cccbcac90000        0000000000000000
> 000000c4c3c2c100        0000000000000000
> 000000cccbcac900        0000000000000000
> $ 
> 
> regardless of whether the change has been applied or not.
> 
> With the change not applied and interAptive MR2 hardware[2], which does 
> implement the MIPS16e2 ASE, it produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000cecdcccb
> 00000000c5c4c3c2        00000000cdcccbca
> 00000000c7c6c5c4        00000000cfcecdcc
> 0000c4c3c2c10000        0000000000000000
> 0000000000000000        0000cccbcac90000
> 000000c4c3c2c100        0000000000000000
> 0000000000000000        000000cccbcac900
> $ 
> 
> which shows that for GP-relative operations the correct trapping address 
> calculated from $gp has been obtained from the CP0 BadVAddr register and 
> so has data from the source operand, however masking and extension has 
> not been applied for halfword operations.
> 
> With the change applied and interAptive MR2 hardware the program 
> produces the following output:
> 
> $ ./mips16e2-test
> c8c7c6c5c4c3c2c1        d0cfcecdcccbcac9
> 00000000c6c5c4c3        00000000cecdcccb
> 00000000c5c4c3c2        00000000ffffcbca
> 00000000c7c6c5c4        000000000000cdcc
> 0000c4c3c2c10000        0000000000000000
> 0000000000000000        0000cccbcac90000
> 000000c4c3c2c100        0000000000000000
> 0000000000000000        0000000000cac900
> $ 
> 
> as expected.
> 
> References:
> 
> [1] "MIPS32 Architecture for Programmers: MIPS16e2 Application-Specific
>     Extension Technical Reference Manual", Imagination Technologies
>     Ltd., Document Number: MD01172, Revision 01.00, April 26, 2016
> 
> [2] "MIPS32 interAptiv Multiprocessing System Software User's Manual",
>     Imagination Technologies Ltd., Document Number: MD00904, Revision
>     02.01, June 15, 2016, Chapter 24 "MIPS16e Application-Specific 
>     Extension to the MIPS32 Instruction Set", pp. 871-883
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
>  NB a recent binutils version, as from commit 25499ac7ee92 ("MIPS16e2: 
> Add MIPS16e2 ASE support"), is required to build the test program.
> 
>   Maciej
> 
> linux-mips16e2-ase-emul.diff
> Index: linux-sfr-test/arch/mips/kernel/unaligned.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/unaligned.c	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/kernel/unaligned.c	2017-05-22 22:54:28.686096000 +0100
> @@ -1984,6 +1984,8 @@ static void emulate_load_store_MIPS16e(s
>  	u16 __user *pc16;
>  	unsigned long origpc;
>  	union mips16e_instruction mips16inst, oldinst;
> +	unsigned int opcode;
> +	int extended = 0;
>  
>  	origpc = regs->cp0_epc;
>  	orig31 = regs->regs[31];
> @@ -1996,6 +1998,7 @@ static void emulate_load_store_MIPS16e(s
>  
>  	/* skip EXTEND instruction */
>  	if (mips16inst.ri.opcode == MIPS16e_extend_op) {
> +		extended = 1;
>  		pc16++;
>  		__get_user(mips16inst.full, pc16);
>  	} else if (delay_slot(regs)) {
> @@ -2008,7 +2011,8 @@ static void emulate_load_store_MIPS16e(s
>  			goto sigbus;
>  	}
>  
> -	switch (mips16inst.ri.opcode) {
> +	opcode = mips16inst.ri.opcode;
> +	switch (opcode) {
>  	case MIPS16e_i64_op:	/* I64 or RI64 instruction */
>  		switch (mips16inst.i64.func) {	/* I64/RI64 func field check */
>  		case MIPS16e_ldpc_func:
> @@ -2028,9 +2032,40 @@ static void emulate_load_store_MIPS16e(s
>  		goto sigbus;
>  
>  	case MIPS16e_swsp_op:
> +		reg = reg16to32[mips16inst.ri.rx];
> +		if (extended && cpu_has_mips16e2)
> +			switch (mips16inst.ri.imm >> 5) {
> +			case 0:		/* SWSP */
> +			case 1:		/* SWGP */
> +				break;
> +			case 2:		/* SHGP */
> +				opcode = MIPS16e_sh_op;
> +				break;
> +			default:
> +				goto sigbus;
> +			}
> +		break;
> +
>  	case MIPS16e_lwpc_op:
> +		reg = reg16to32[mips16inst.ri.rx];
> +		break;
> +
>  	case MIPS16e_lwsp_op:
>  		reg = reg16to32[mips16inst.ri.rx];
> +		if (extended && cpu_has_mips16e2)
> +			switch (mips16inst.ri.imm >> 5) {
> +			case 0:		/* LWSP */
> +			case 1:		/* LWGP */
> +				break;
> +			case 2:		/* LHGP */
> +				opcode = MIPS16e_lh_op;
> +				break;
> +			case 4:		/* LHUGP */
> +				opcode = MIPS16e_lhu_op;
> +				break;
> +			default:
> +				goto sigbus;
> +			}
>  		break;
>  
>  	case MIPS16e_i8_op:
> @@ -2044,7 +2079,7 @@ static void emulate_load_store_MIPS16e(s
>  		break;
>  	}
>  
> -	switch (mips16inst.ri.opcode) {
> +	switch (opcode) {
>  
>  	case MIPS16e_lb_op:
>  	case MIPS16e_lbu_op:

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[PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[Maciej W. Rozycki]

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 Submitted third in the series so that the presence of "mips16e2" in 
/proc/cpuinfo not only indicates the hardware feature, but our correct 
unaligned emulation as well.

 There's a `checkpatch.pl' error reported for the unusual formatting, 
however it is consistent with surrounding code and I do not think we 
want to make this statement an oddball.

  Maciej

linux-mips16e2-ase-report.diff
Index: linux-sfr-test/arch/mips/kernel/proc.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/proc.c	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/proc.c	2017-05-22 22:56:31.000000000 +0100
@@ -109,6 +109,7 @@ static int show_cpuinfo(struct seq_file 
 
 	seq_printf(m, "ASEs implemented\t:");
 	if (cpu_has_mips16)	seq_printf(m, "%s", " mips16");
+	if (cpu_has_mips16e2)	seq_printf(m, "%s", " mips16e2");
 	if (cpu_has_mdmx)	seq_printf(m, "%s", " mdmx");
 	if (cpu_has_mips3d)	seq_printf(m, "%s", " mips3d");
 	if (cpu_has_smartmips)	seq_printf(m, "%s", " smartmips");

[PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[Maciej W. Rozycki]

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
 Submitted third in the series so that the presence of "mips16e2" in 
/proc/cpuinfo not only indicates the hardware feature, but our correct 
unaligned emulation as well.

 There's a `checkpatch.pl' error reported for the unusual formatting, 
however it is consistent with surrounding code and I do not think we 
want to make this statement an oddball.

  Maciej

linux-mips16e2-ase-report.diff
Index: linux-sfr-test/arch/mips/kernel/proc.c
===================================================================
--- linux-sfr-test.orig/arch/mips/kernel/proc.c	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/kernel/proc.c	2017-05-22 22:56:31.000000000 +0100
@@ -109,6 +109,7 @@ static int show_cpuinfo(struct seq_file 
 
 	seq_printf(m, "ASEs implemented\t:");
 	if (cpu_has_mips16)	seq_printf(m, "%s", " mips16");
+	if (cpu_has_mips16e2)	seq_printf(m, "%s", " mips16e2");
 	if (cpu_has_mdmx)	seq_printf(m, "%s", " mdmx");
 	if (cpu_has_mips3d)	seq_printf(m, "%s", " mips3d");
 	if (cpu_has_smartmips)	seq_printf(m, "%s", " smartmips");

Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[James Hogan]

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On Tue, May 23, 2017 at 01:39:23PM +0100, Maciej W. Rozycki wrote:
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
>  Submitted third in the series so that the presence of "mips16e2" in 
> /proc/cpuinfo not only indicates the hardware feature, but our correct 
> unaligned emulation as well.

This should be mentioned in the commit description (not the 3rd in the
series bit, the "it indicates both the hw feature and unaligned
emulation" bit).

Otherwise
Reivewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> 
>  There's a `checkpatch.pl' error reported for the unusual formatting, 
> however it is consistent with surrounding code and I do not think we 
> want to make this statement an oddball.
> 
>   Maciej
> 
> linux-mips16e2-ase-report.diff
> Index: linux-sfr-test/arch/mips/kernel/proc.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/proc.c	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/kernel/proc.c	2017-05-22 22:56:31.000000000 +0100
> @@ -109,6 +109,7 @@ static int show_cpuinfo(struct seq_file 
>  
>  	seq_printf(m, "ASEs implemented\t:");
>  	if (cpu_has_mips16)	seq_printf(m, "%s", " mips16");
> +	if (cpu_has_mips16e2)	seq_printf(m, "%s", " mips16e2");
>  	if (cpu_has_mdmx)	seq_printf(m, "%s", " mdmx");
>  	if (cpu_has_mips3d)	seq_printf(m, "%s", " mips3d");
>  	if (cpu_has_smartmips)	seq_printf(m, "%s", " smartmips");

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Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[James Hogan]

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On Tue, May 23, 2017 at 01:39:23PM +0100, Maciej W. Rozycki wrote:
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---
>  Submitted third in the series so that the presence of "mips16e2" in 
> /proc/cpuinfo not only indicates the hardware feature, but our correct 
> unaligned emulation as well.

This should be mentioned in the commit description (not the 3rd in the
series bit, the "it indicates both the hw feature and unaligned
emulation" bit).

Otherwise
Reivewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> 
>  There's a `checkpatch.pl' error reported for the unusual formatting, 
> however it is consistent with surrounding code and I do not think we 
> want to make this statement an oddball.
> 
>   Maciej
> 
> linux-mips16e2-ase-report.diff
> Index: linux-sfr-test/arch/mips/kernel/proc.c
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/kernel/proc.c	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/kernel/proc.c	2017-05-22 22:56:31.000000000 +0100
> @@ -109,6 +109,7 @@ static int show_cpuinfo(struct seq_file 
>  
>  	seq_printf(m, "ASEs implemented\t:");
>  	if (cpu_has_mips16)	seq_printf(m, "%s", " mips16");
> +	if (cpu_has_mips16e2)	seq_printf(m, "%s", " mips16e2");
>  	if (cpu_has_mdmx)	seq_printf(m, "%s", " mdmx");
>  	if (cpu_has_mips3d)	seq_printf(m, "%s", " mips3d");
>  	if (cpu_has_smartmips)	seq_printf(m, "%s", " smartmips");

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Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[Maciej W. Rozycki]

On Mon, 3 Jul 2017, James Hogan wrote:

> >  Submitted third in the series so that the presence of "mips16e2" in 
> > /proc/cpuinfo not only indicates the hardware feature, but our correct 
> > unaligned emulation as well.
> 
> This should be mentioned in the commit description (not the 3rd in the
> series bit, the "it indicates both the hw feature and unaligned
> emulation" bit).

 Shall I repost the series with this piece amended?  Or will just 3/4 do?

  Maciej

Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[Maciej W. Rozycki]

On Mon, 3 Jul 2017, James Hogan wrote:

> >  Submitted third in the series so that the presence of "mips16e2" in 
> > /proc/cpuinfo not only indicates the hardware feature, but our correct 
> > unaligned emulation as well.
> 
> This should be mentioned in the commit description (not the 3rd in the
> series bit, the "it indicates both the hw feature and unaligned
> emulation" bit).

 Shall I repost the series with this piece amended?  Or will just 3/4 do?

  Maciej

Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[James Hogan]

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On Tue, Jul 04, 2017 at 04:35:51PM +0100, Maciej W. Rozycki wrote:
> On Mon, 3 Jul 2017, James Hogan wrote:
> 
> > >  Submitted third in the series so that the presence of "mips16e2" in 
> > > /proc/cpuinfo not only indicates the hardware feature, but our correct 
> > > unaligned emulation as well.
> > 
> > This should be mentioned in the commit description (not the 3rd in the
> > series bit, the "it indicates both the hw feature and unaligned
> > emulation" bit).
> 
>  Shall I repost the series with this piece amended?  Or will just 3/4 do?

Just 3/4 should do I think.

Thanks
James

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Re: [PATCH 3/4] MIPS16e2: Report ASE presence in /proc/cpuinfo

[James Hogan]

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On Tue, Jul 04, 2017 at 04:35:51PM +0100, Maciej W. Rozycki wrote:
> On Mon, 3 Jul 2017, James Hogan wrote:
> 
> > >  Submitted third in the series so that the presence of "mips16e2" in 
> > > /proc/cpuinfo not only indicates the hardware feature, but our correct 
> > > unaligned emulation as well.
> > 
> > This should be mentioned in the commit description (not the 3rd in the
> > series bit, the "it indicates both the hw feature and unaligned
> > emulation" bit).
> 
>  Shall I repost the series with this piece amended?  Or will just 3/4 do?

Just 3/4 should do I think.

Thanks
James

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[PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
for the MIPS16 ASE already, providing for code to be optimized away.

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips16e2-ase-optim.diff
Index: linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:57:28.987400000 +0100
@@ -40,6 +40,7 @@
 #endif
 
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:57:28.991406000 +0100
@@ -31,6 +31,7 @@
 #define cpu_has_ejtag			1
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:57:28.995412000 +0100
@@ -19,6 +19,7 @@
 #define cpu_has_ejtag			1
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:57:29.001406000 +0100
@@ -37,6 +37,7 @@
 #endif
 
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx		0
 #define cpu_has_mips3d		0
 #define cpu_has_smartmips	0
Index: linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:57:29.006398000 +0100
@@ -27,6 +27,7 @@
 #define cpu_has_mcheck			0
 #define cpu_has_ejtag			0
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:57:29.010397000 +0100
@@ -19,6 +19,7 @@
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_cache_cdex_p	1
 #define cpu_has_prefetch	0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:57:29.020398000 +0100
@@ -43,6 +43,7 @@
 #define cpu_has_ejtag			0
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:57:29.024398000 +0100
@@ -16,6 +16,7 @@
  */
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_p	0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:57:29.028408000 +0100
@@ -29,6 +29,7 @@
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_s	0
 #define cpu_has_mcheck		0
Index: linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:57:29.032407000 +0100
@@ -23,6 +23,7 @@
 #define cpu_has_ejtag 1
 #define cpu_has_llsc		1
 #define cpu_has_mips16 0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx 0
 #define cpu_has_mips3d 0
 #define cpu_has_smartmips 0
Index: linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:57:29.043398000 +0100
@@ -32,6 +32,7 @@
 #define cpu_has_mcheck		0
 #define cpu_has_mdmx		0
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mips3d		0
 #define cpu_has_mipsmt		0
 #define cpu_has_smartmips	0
Index: linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:57:29.047397000 +0100
@@ -13,6 +13,7 @@
 #define cpu_has_4k_cache	1
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_counter		1
 #define cpu_has_divec		1
 #define cpu_has_vce		0
Index: linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:57:29.051411000 +0100
@@ -48,6 +48,7 @@
 #define cpu_has_llsc			1
 
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:57:29.066402000 +0100
@@ -17,6 +17,7 @@
 #define cpu_has_counter		1
 #define cpu_has_watch		0
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_cache_cdex_p	1
 #define cpu_has_prefetch	0
Index: linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:57:29.070404000 +0100
@@ -13,6 +13,7 @@
  */
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		1
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_p	0
Index: linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:57:29.074404000 +0100
@@ -6,6 +6,7 @@
 #define cpu_has_inclusive_pcaches	0
 
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx		0
 #define cpu_has_mips3d		0
 #define cpu_has_smartmips	0

[PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
for the MIPS16 ASE already, providing for code to be optimized away.

Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips16e2-ase-optim.diff
Index: linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:57:28.987400000 +0100
@@ -40,6 +40,7 @@
 #endif
 
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:57:28.991406000 +0100
@@ -31,6 +31,7 @@
 #define cpu_has_ejtag			1
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:57:28.995412000 +0100
@@ -19,6 +19,7 @@
 #define cpu_has_ejtag			1
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:57:29.001406000 +0100
@@ -37,6 +37,7 @@
 #endif
 
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx		0
 #define cpu_has_mips3d		0
 #define cpu_has_smartmips	0
Index: linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:57:29.006398000 +0100
@@ -27,6 +27,7 @@
 #define cpu_has_mcheck			0
 #define cpu_has_ejtag			0
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:57:29.010397000 +0100
@@ -19,6 +19,7 @@
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_cache_cdex_p	1
 #define cpu_has_prefetch	0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:57:29.020398000 +0100
@@ -43,6 +43,7 @@
 #define cpu_has_ejtag			0
 #define cpu_has_llsc			1
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:57:29.024398000 +0100
@@ -16,6 +16,7 @@
  */
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_p	0
Index: linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:57:29.028408000 +0100
@@ -29,6 +29,7 @@
 #define cpu_has_32fpr		1
 #define cpu_has_counter		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_s	0
 #define cpu_has_mcheck		0
Index: linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:57:29.032407000 +0100
@@ -23,6 +23,7 @@
 #define cpu_has_ejtag 1
 #define cpu_has_llsc		1
 #define cpu_has_mips16 0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx 0
 #define cpu_has_mips3d 0
 #define cpu_has_smartmips 0
Index: linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:57:29.043398000 +0100
@@ -32,6 +32,7 @@
 #define cpu_has_mcheck		0
 #define cpu_has_mdmx		0
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mips3d		0
 #define cpu_has_mipsmt		0
 #define cpu_has_smartmips	0
Index: linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:57:29.047397000 +0100
@@ -13,6 +13,7 @@
 #define cpu_has_4k_cache	1
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_counter		1
 #define cpu_has_divec		1
 #define cpu_has_vce		0
Index: linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:57:29.051411000 +0100
@@ -48,6 +48,7 @@
 #define cpu_has_llsc			1
 
 #define cpu_has_mips16			0
+#define cpu_has_mips16e2		0
 #define cpu_has_mdmx			0
 #define cpu_has_mips3d			0
 #define cpu_has_smartmips		0
Index: linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:57:29.066402000 +0100
@@ -17,6 +17,7 @@
 #define cpu_has_counter		1
 #define cpu_has_watch		0
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		0
 #define cpu_has_cache_cdex_p	1
 #define cpu_has_prefetch	0
Index: linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:57:29.070404000 +0100
@@ -13,6 +13,7 @@
  */
 #define cpu_has_watch		1
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_divec		1
 #define cpu_has_vce		0
 #define cpu_has_cache_cdex_p	0
Index: linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:57:29.074404000 +0100
@@ -6,6 +6,7 @@
 #define cpu_has_inclusive_pcaches	0
 
 #define cpu_has_mips16		0
+#define cpu_has_mips16e2	0
 #define cpu_has_mdmx		0
 #define cpu_has_mips3d		0
 #define cpu_has_smartmips	0

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Florian Fainelli]

On 05/23/2017 05:40 AM, Maciej W. Rozycki wrote:
> Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> for the MIPS16 ASE already, providing for code to be optimized away.
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> ---

Could you switch to using git format-patch such that we have a diffstat
at the beginning of the patch which helps the reviewer figure out which
files are being touched?

It just occurred to me that a bunch of other platforms are lacking a
cpu-feature-overrides.h file, but presumably would never be able to
support mips16e2, like ar7, emma2rh, pnx833x and so on.

> linux-mips16e2-ase-optim.diff
> Index: linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:57:28.987400000 +0100
> @@ -40,6 +40,7 @@
>  #endif
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:57:28.991406000 +0100
> @@ -31,6 +31,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:57:28.995412000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0

And why not mach-bmips/cpu-features-overrides.h?

> Index: linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:57:29.001406000 +0100
> @@ -37,6 +37,7 @@
>  #endif
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:57:29.006398000 +0100
> @@ -27,6 +27,7 @@
>  #define cpu_has_mcheck			0
>  #define cpu_has_ejtag			0
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:57:29.010397000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:57:29.020398000 +0100
> @@ -43,6 +43,7 @@
>  #define cpu_has_ejtag			0
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:57:29.024398000 +0100
> @@ -16,6 +16,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:57:29.028408000 +0100
> @@ -29,6 +29,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_s	0
>  #define cpu_has_mcheck		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:57:29.032407000 +0100
> @@ -23,6 +23,7 @@
>  #define cpu_has_ejtag 1
>  #define cpu_has_llsc		1
>  #define cpu_has_mips16 0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx 0
>  #define cpu_has_mips3d 0
>  #define cpu_has_smartmips 0
> Index: linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:57:29.043398000 +0100
> @@ -32,6 +32,7 @@
>  #define cpu_has_mcheck		0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mips3d		0
>  #define cpu_has_mipsmt		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:57:29.047397000 +0100
> @@ -13,6 +13,7 @@
>  #define cpu_has_4k_cache	1
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_counter		1
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:57:29.051411000 +0100
> @@ -48,6 +48,7 @@
>  #define cpu_has_llsc			1
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:57:29.066402000 +0100
> @@ -17,6 +17,7 @@
>  #define cpu_has_counter		1
>  #define cpu_has_watch		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:57:29.070404000 +0100
> @@ -13,6 +13,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:57:29.074404000 +0100
> @@ -6,6 +6,7 @@
>  #define cpu_has_inclusive_pcaches	0
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0
> 


-- 
Florian

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

On Tue, 23 May 2017, Florian Fainelli wrote:

> > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > for the MIPS16 ASE already, providing for code to be optimized away.
> > 
> > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> > ---
> 
> Could you switch to using git format-patch such that we have a diffstat
> at the beginning of the patch which helps the reviewer figure out which
> files are being touched?

 My workflow that I have found efficient and I have been using for years 
now does not involve using GIT for outstanding patch management, so I 
don't think I can adjust to your request easily, without losing that 
efficiency or introducing processing errors from the additional final GIT 
import step.

 However separate `diffstat' information is redundant in that it is 
already carried by the patch itself and can be easily recreated by piping 
the containing e-mail to `diffstat' from the MUA while reading the 
message.  Is that a solution that would work for you?

> It just occurred to me that a bunch of other platforms are lacking a
> cpu-feature-overrides.h file, but presumably would never be able to
> support mips16e2, like ar7, emma2rh, pnx833x and so on.

 I have explicitly noted in the change description that only platforms 
that already have an override for the base MIPS16 ASE have been changed 
(for consistency, anyway).  It's an optimisation only anyway, not a 
correctness issue.

 If there are platforms that may or may not have the MIPS16 ASE available, 
however are known to never have the MIPS16e2 ASE in the future, e.g. 
because they have been already obsoleted and no new CPU modules will ever 
be introduced, then the respective platform maintainers can add an 
override if desired.

  Maciej

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

On Tue, 23 May 2017, Florian Fainelli wrote:

> > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > for the MIPS16 ASE already, providing for code to be optimized away.
> > 
> > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> > ---
> 
> Could you switch to using git format-patch such that we have a diffstat
> at the beginning of the patch which helps the reviewer figure out which
> files are being touched?

 My workflow that I have found efficient and I have been using for years 
now does not involve using GIT for outstanding patch management, so I 
don't think I can adjust to your request easily, without losing that 
efficiency or introducing processing errors from the additional final GIT 
import step.

 However separate `diffstat' information is redundant in that it is 
already carried by the patch itself and can be easily recreated by piping 
the containing e-mail to `diffstat' from the MUA while reading the 
message.  Is that a solution that would work for you?

> It just occurred to me that a bunch of other platforms are lacking a
> cpu-feature-overrides.h file, but presumably would never be able to
> support mips16e2, like ar7, emma2rh, pnx833x and so on.

 I have explicitly noted in the change description that only platforms 
that already have an override for the base MIPS16 ASE have been changed 
(for consistency, anyway).  It's an optimisation only anyway, not a 
correctness issue.

 If there are platforms that may or may not have the MIPS16 ASE available, 
however are known to never have the MIPS16e2 ASE in the future, e.g. 
because they have been already obsoleted and no new CPU modules will ever 
be introduced, then the respective platform maintainers can add an 
override if desired.

  Maciej

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 10480 bytes --]

On Tue, May 23, 2017 at 01:40:23PM +0100, Maciej W. Rozycki wrote:
> Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> for the MIPS16 ASE already, providing for code to be optimized away.
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>

I'm inclined to agree with Florian, that git formatted patches are
slightly easier to review, perhaps they just subjectively look more
familiar. Out of interest, do you not use git for retrieving kernel
source already?

Anyway the actual changes look acceptable to me, so
Reviewed-by: James Hogan <james.hogan@imgtec.com>

Thanks for the series.
James

> ---
> linux-mips16e2-ase-optim.diff
> Index: linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:57:28.987400000 +0100
> @@ -40,6 +40,7 @@
>  #endif
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:57:28.991406000 +0100
> @@ -31,6 +31,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:57:28.995412000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:57:29.001406000 +0100
> @@ -37,6 +37,7 @@
>  #endif
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:57:29.006398000 +0100
> @@ -27,6 +27,7 @@
>  #define cpu_has_mcheck			0
>  #define cpu_has_ejtag			0
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:57:29.010397000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:57:29.020398000 +0100
> @@ -43,6 +43,7 @@
>  #define cpu_has_ejtag			0
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:57:29.024398000 +0100
> @@ -16,6 +16,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:57:29.028408000 +0100
> @@ -29,6 +29,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_s	0
>  #define cpu_has_mcheck		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:57:29.032407000 +0100
> @@ -23,6 +23,7 @@
>  #define cpu_has_ejtag 1
>  #define cpu_has_llsc		1
>  #define cpu_has_mips16 0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx 0
>  #define cpu_has_mips3d 0
>  #define cpu_has_smartmips 0
> Index: linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:57:29.043398000 +0100
> @@ -32,6 +32,7 @@
>  #define cpu_has_mcheck		0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mips3d		0
>  #define cpu_has_mipsmt		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:57:29.047397000 +0100
> @@ -13,6 +13,7 @@
>  #define cpu_has_4k_cache	1
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_counter		1
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:57:29.051411000 +0100
> @@ -48,6 +48,7 @@
>  #define cpu_has_llsc			1
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:57:29.066402000 +0100
> @@ -17,6 +17,7 @@
>  #define cpu_has_counter		1
>  #define cpu_has_watch		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:57:29.070404000 +0100
> @@ -13,6 +13,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:57:29.074404000 +0100
> @@ -6,6 +6,7 @@
>  #define cpu_has_inclusive_pcaches	0
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0

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Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[James Hogan]

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On Tue, May 23, 2017 at 01:40:23PM +0100, Maciej W. Rozycki wrote:
> Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> for the MIPS16 ASE already, providing for code to be optimized away.
> 
> Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>

I'm inclined to agree with Florian, that git formatted patches are
slightly easier to review, perhaps they just subjectively look more
familiar. Out of interest, do you not use git for retrieving kernel
source already?

Anyway the actual changes look acceptable to me, so
Reviewed-by: James Hogan <james.hogan@imgtec.com>

Thanks for the series.
James

> ---
> linux-mips16e2-ase-optim.diff
> Index: linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h	2017-05-22 22:57:28.987400000 +0100
> @@ -40,6 +40,7 @@
>  #endif
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h	2017-05-22 22:57:28.991406000 +0100
> @@ -31,6 +31,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h	2017-05-22 22:57:28.995412000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_ejtag			1
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h	2017-05-22 22:57:29.001406000 +0100
> @@ -37,6 +37,7 @@
>  #endif
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h	2017-05-22 22:57:29.006398000 +0100
> @@ -27,6 +27,7 @@
>  #define cpu_has_mcheck			0
>  #define cpu_has_ejtag			0
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h	2017-05-22 22:57:29.010397000 +0100
> @@ -19,6 +19,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h	2017-05-22 22:57:29.020398000 +0100
> @@ -43,6 +43,7 @@
>  #define cpu_has_ejtag			0
>  #define cpu_has_llsc			1
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h	2017-05-22 22:57:29.024398000 +0100
> @@ -16,6 +16,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-ip32/cpu-feature-overrides.h	2017-05-22 22:57:29.028408000 +0100
> @@ -29,6 +29,7 @@
>  #define cpu_has_32fpr		1
>  #define cpu_has_counter		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_s	0
>  #define cpu_has_mcheck		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:42:15.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-jz4740/cpu-feature-overrides.h	2017-05-22 22:57:29.032407000 +0100
> @@ -23,6 +23,7 @@
>  #define cpu_has_ejtag 1
>  #define cpu_has_llsc		1
>  #define cpu_has_mips16 0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx 0
>  #define cpu_has_mips3d 0
>  #define cpu_has_smartmips 0
> Index: linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h	2017-05-22 22:57:29.043398000 +0100
> @@ -32,6 +32,7 @@
>  #define cpu_has_mcheck		0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mips3d		0
>  #define cpu_has_mipsmt		0
>  #define cpu_has_smartmips	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h	2017-05-22 22:57:29.047397000 +0100
> @@ -13,6 +13,7 @@
>  #define cpu_has_4k_cache	1
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_counter		1
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h	2017-05-22 22:57:29.051411000 +0100
> @@ -48,6 +48,7 @@
>  #define cpu_has_llsc			1
>  
>  #define cpu_has_mips16			0
> +#define cpu_has_mips16e2		0
>  #define cpu_has_mdmx			0
>  #define cpu_has_mips3d			0
>  #define cpu_has_smartmips		0
> Index: linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-rm/cpu-feature-overrides.h	2017-05-22 22:57:29.066402000 +0100
> @@ -17,6 +17,7 @@
>  #define cpu_has_counter		1
>  #define cpu_has_watch		0
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		0
>  #define cpu_has_cache_cdex_p	1
>  #define cpu_has_prefetch	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-sibyte/cpu-feature-overrides.h	2017-05-22 22:57:29.070404000 +0100
> @@ -13,6 +13,7 @@
>   */
>  #define cpu_has_watch		1
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_divec		1
>  #define cpu_has_vce		0
>  #define cpu_has_cache_cdex_p	0
> Index: linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h
> ===================================================================
> --- linux-sfr-test.orig/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:42:16.000000000 +0100
> +++ linux-sfr-test/arch/mips/include/asm/mach-tx49xx/cpu-feature-overrides.h	2017-05-22 22:57:29.074404000 +0100
> @@ -6,6 +6,7 @@
>  #define cpu_has_inclusive_pcaches	0
>  
>  #define cpu_has_mips16		0
> +#define cpu_has_mips16e2	0
>  #define cpu_has_mdmx		0
>  #define cpu_has_mips3d		0
>  #define cpu_has_smartmips	0

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Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

On Mon, 3 Jul 2017, James Hogan wrote:

> > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > for the MIPS16 ASE already, providing for code to be optimized away.
> > 
> > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> 
> I'm inclined to agree with Florian, that git formatted patches are
> slightly easier to review, perhaps they just subjectively look more
> familiar. Out of interest, do you not use git for retrieving kernel
> source already?

 I do use GIT for managing the sources themselves of course, however I 
keep using `quilt' for patches for two main reasons:

1. It works efficiently for the work flow I've got used to, e.g. how do I 
   hand-edit 16th previous diff with GIT; how do I swap patches; how do I 
   move individual hunks between patches? -- these actions are trivial 
   with `quilt'.

2. I don't use the same system for development as I do for submissions, 
   also to make sure no unwanted bits leak by accident.

Maybe `quilt' can be taught to prepend `diffstat' automagically itself; 
I'll check.

> Thanks for the series.

 Thanks for your review!

  Maciej

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[Maciej W. Rozycki]

On Mon, 3 Jul 2017, James Hogan wrote:

> > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > for the MIPS16 ASE already, providing for code to be optimized away.
> > 
> > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> 
> I'm inclined to agree with Florian, that git formatted patches are
> slightly easier to review, perhaps they just subjectively look more
> familiar. Out of interest, do you not use git for retrieving kernel
> source already?

 I do use GIT for managing the sources themselves of course, however I 
keep using `quilt' for patches for two main reasons:

1. It works efficiently for the work flow I've got used to, e.g. how do I 
   hand-edit 16th previous diff with GIT; how do I swap patches; how do I 
   move individual hunks between patches? -- these actions are trivial 
   with `quilt'.

2. I don't use the same system for development as I do for submissions, 
   also to make sure no unwanted bits leak by accident.

Maybe `quilt' can be taught to prepend `diffstat' automagically itself; 
I'll check.

> Thanks for the series.

 Thanks for your review!

  Maciej

Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[James Hogan]

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On Tue, Jul 04, 2017 at 04:50:00PM +0100, Maciej W. Rozycki wrote:
> On Mon, 3 Jul 2017, James Hogan wrote:
> 
> > > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > > for the MIPS16 ASE already, providing for code to be optimized away.
> > > 
> > > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> > 
> > I'm inclined to agree with Florian, that git formatted patches are
> > slightly easier to review, perhaps they just subjectively look more
> > familiar. Out of interest, do you not use git for retrieving kernel
> > source already?
> 
>  I do use GIT for managing the sources themselves of course, however I 
> keep using `quilt' for patches for two main reasons:
> 
> 1. It works efficiently for the work flow I've got used to,

fair enough.

> e.g. how do I hand-edit 16th previous diff with GIT;

git rebase -i HEAD~17
You can change a commit from "pick" to "edit" to get the rebase to stop
and allow you to edit the tree at that point in the series, before
continuing with "git rebase --continue" (or --abort to cancel the
rebase).

> how do I swap patches;

git rebase -i $base
and reorder the lines

> how do I move individual hunks between patches? -- these actions are
> trivial with `quilt'.

git rebase -i is again the answer, though probably not as trivial as
quilt (though perhaps more robust than hand editing patches?).

I've found a few ways that generally revolve around using
git checkout -p,

Example 1:
To move a hunk from a later commit into an earlier commit, add

x git checkout -p $later_commit && git commit --amend $earlier_commit

before the later commit in the interactive rebase. Pick the hunks you
want to grab (you can edit them there too), and when rebase is done you
have a fixup commit before the later commit. Finally do another rebase
with --autosquash:

git rebase -i $base --autosquash

to automatically squash the fixup commit into the earlier commit

Example 2:
To move a hunk from an earlier commit into a later commit, you could
"git checkout -p" after both commits, e.g.

pick $earlier_commit
x git checkout -p HEAD~ && git commit --amend
pick $intermediate1
pick $later_commit
x git checkout -p $later_commit && git commit --amend

Interactively undo the change (first checkout -p), and interactively
reapply the change (second checkout -p).

Being git there's 100 variants of that, e.g. changing pick to edit and
doing the commands manually, or doing the same thing as Example 1 for
moving hunks later if you aren't expecting conflicts (but you'll have to
move the fixup yourself as --autosquash doesn't move fixups later).

Its obviously advisable to inspect and diff after rebase -i to double
check.

Cheers
James

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Re: [PATCH 4/4] MIPS16e2: Provide feature overrides for non-MIPS16 systems

[James Hogan]

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On Tue, Jul 04, 2017 at 04:50:00PM +0100, Maciej W. Rozycki wrote:
> On Mon, 3 Jul 2017, James Hogan wrote:
> 
> > > Hardcode the absence of the MIPS16e2 ASE for all the systems that do so 
> > > for the MIPS16 ASE already, providing for code to be optimized away.
> > > 
> > > Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
> > 
> > I'm inclined to agree with Florian, that git formatted patches are
> > slightly easier to review, perhaps they just subjectively look more
> > familiar. Out of interest, do you not use git for retrieving kernel
> > source already?
> 
>  I do use GIT for managing the sources themselves of course, however I 
> keep using `quilt' for patches for two main reasons:
> 
> 1. It works efficiently for the work flow I've got used to,

fair enough.

> e.g. how do I hand-edit 16th previous diff with GIT;

git rebase -i HEAD~17
You can change a commit from "pick" to "edit" to get the rebase to stop
and allow you to edit the tree at that point in the series, before
continuing with "git rebase --continue" (or --abort to cancel the
rebase).

> how do I swap patches;

git rebase -i $base
and reorder the lines

> how do I move individual hunks between patches? -- these actions are
> trivial with `quilt'.

git rebase -i is again the answer, though probably not as trivial as
quilt (though perhaps more robust than hand editing patches?).

I've found a few ways that generally revolve around using
git checkout -p,

Example 1:
To move a hunk from a later commit into an earlier commit, add

x git checkout -p $later_commit && git commit --amend $earlier_commit

before the later commit in the interactive rebase. Pick the hunks you
want to grab (you can edit them there too), and when rebase is done you
have a fixup commit before the later commit. Finally do another rebase
with --autosquash:

git rebase -i $base --autosquash

to automatically squash the fixup commit into the earlier commit

Example 2:
To move a hunk from an earlier commit into a later commit, you could
"git checkout -p" after both commits, e.g.

pick $earlier_commit
x git checkout -p HEAD~ && git commit --amend
pick $intermediate1
pick $later_commit
x git checkout -p $later_commit && git commit --amend

Interactively undo the change (first checkout -p), and interactively
reapply the change (second checkout -p).

Being git there's 100 variants of that, e.g. changing pick to edit and
doing the commands manually, or doing the same thing as Example 1 for
moving hunks later if you aren't expecting conflicts (but you'll have to
move the fixup yourself as --autosquash doesn't move fixups later).

Its obviously advisable to inspect and diff after rebase -i to double
check.

Cheers
James

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[PING][PATCH 0/4] MIPS16e2 ASE support

[Maciej W. Rozycki]

On Tue, 23 May 2017, Maciej W. Rozycki wrote:

>  This patch series adds MIPS16e2 ASE support as per the architecture 
> specification[1].  Included there's feature identification, reporting and 
> necessary instruction emulation.  These patches have been checked with 
> interAptiv MR2 hardware to verify that new MIPS16e2 functions operate 
> correctly and with 74Kf hardware to verify that no regression has been 
> casued with original MIPS16e support.  See individual descriptions for the 
> details of each change made.

 These patches:

<https://patchwork.linux-mips.org/patch/16094/>
<https://patchwork.linux-mips.org/patch/16095/>
<https://patchwork.linux-mips.org/patch/16096/>
<https://patchwork.linux-mips.org/patch/16097/>

are pending review, please help.

  Maciej

[PING][PATCH 0/4] MIPS16e2 ASE support

[Maciej W. Rozycki]

On Tue, 23 May 2017, Maciej W. Rozycki wrote:

>  This patch series adds MIPS16e2 ASE support as per the architecture 
> specification[1].  Included there's feature identification, reporting and 
> necessary instruction emulation.  These patches have been checked with 
> interAptiv MR2 hardware to verify that new MIPS16e2 functions operate 
> correctly and with 74Kf hardware to verify that no regression has been 
> casued with original MIPS16e support.  See individual descriptions for the 
> details of each change made.

 These patches:

<https://patchwork.linux-mips.org/patch/16094/>
<https://patchwork.linux-mips.org/patch/16095/>
<https://patchwork.linux-mips.org/patch/16096/>
<https://patchwork.linux-mips.org/patch/16097/>

are pending review, please help.

  Maciej