[PATCH 0/9] mips: dts: Split Realtek devicetrees

[PATCH 0/9] mips: dts: Split Realtek devicetrees

[Sander Vanheule]

This patch series intends to clean up the base includes, shared between
hardware devicetrees. To get rid of some dtbs_check warnings, some cpu
clock prorerties are also modified.

To indicate why the split-up is required, the series concludes with
adding some CPU peripherals to rtl838x.dtsi, which are then used to add
a gpio-restart for the Cisco SG220-26P.

Sander Vanheule (9):
  mips: dts: realtek: Decouple RTL930x base DTSI
  mips: dts: realtek: Clean up CPU clocks
  mips: dts: realtek: Add address to SoC node name
  mips: dts: realtek: Fold rtl83xx into rtl838x
  mips: dts: realtek: Add SoC IRQ node for RTL838x
  mips: dts: realtek: Correct uart interrupt-parent
  mips: dts: realtek: Replace uart clock property
  mips: dts: realtek: Add RTL838x SoC peripherals
  mips: dts: realtek: Add restart to Cisco SG220-26P

 arch/mips/boot/dts/realtek/cisco_sg220-26.dts |  10 +-
 arch/mips/boot/dts/realtek/rtl838x.dtsi       | 111 +++++++++++++-
 arch/mips/boot/dts/realtek/rtl83xx.dtsi       |  59 --------
 arch/mips/boot/dts/realtek/rtl930x.dtsi       | 136 +++++++++++-------
 4 files changed, 202 insertions(+), 114 deletions(-)
 delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi

-- 
2.48.1

[PATCH 1/9] mips: dts: realtek: Decouple RTL930x base DTSI

[Sander Vanheule]

The RTL930x SoC series is sufficiently different to warrant its own base
dtsi. This ensures no properties need to be deleted or overwritten, and
prevents accidental inclusions of updates from rtl83xx.dtsi.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl930x.dtsi | 133 +++++++++++++++---------
 1 file changed, 83 insertions(+), 50 deletions(-)

diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi
index 17577457d159..67261d6fcaa7 100644
--- a/arch/mips/boot/dts/realtek/rtl930x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi
@@ -1,10 +1,23 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
 
-#include "rtl83xx.dtsi"
-
 / {
 	compatible = "realtek,rtl9302-soc";
 
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
+	cpuintc: cpuintc {
+		compatible = "mti,cpu-interrupt-controller";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -58,64 +71,84 @@ i2c1: i2c@388 {
 			status = "disabled";
 		};
 	};
-};
 
-&soc {
-	ranges = <0x0 0x18000000 0x20000>;
+	soc: soc@18000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x18000000 0x20000>;
 
-	intc: interrupt-controller@3000 {
-		compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
-		reg = <0x3000 0x18>, <0x3018 0x18>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
+		intc: interrupt-controller@3000 {
+			compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
+			reg = <0x3000 0x18>, <0x3018 0x18>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
 
-		interrupt-parent = <&cpuintc>;
-		interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
-	};
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
+		};
 
-	spi0: spi@1200 {
-		compatible = "realtek,rtl8380-spi";
-		reg = <0x1200 0x100>;
+		spi0: spi@1200 {
+			compatible = "realtek,rtl8380-spi";
+			reg = <0x1200 0x100>;
 
-		#address-cells = <1>;
-		#size-cells = <0>;
-	};
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 
-	timer0: timer@3200 {
-		compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
-		reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
-		    <0x3230 0x10>, <0x3240 0x10>;
+		timer0: timer@3200 {
+			compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
+			reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
+			    <0x3230 0x10>, <0x3240 0x10>;
 
-		interrupt-parent = <&intc>;
-		interrupts = <7>, <8>, <9>, <10>, <11>;
-		clocks = <&lx_clk>;
-	};
+			interrupt-parent = <&intc>;
+			interrupts = <7>, <8>, <9>, <10>, <11>;
+			clocks = <&lx_clk>;
+		};
 
-	snand: spi@1a400 {
-		compatible = "realtek,rtl9301-snand";
-		reg = <0x1a400 0x44>;
-		interrupt-parent = <&intc>;
-		interrupts = <19>;
-		clocks = <&lx_clk>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-};
+		snand: spi@1a400 {
+			compatible = "realtek,rtl9301-snand";
+			reg = <0x1a400 0x44>;
+			interrupt-parent = <&intc>;
+			interrupts = <19>;
+			clocks = <&lx_clk>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 
-&uart0 {
-	/delete-property/ clock-frequency;
-	clocks = <&lx_clk>;
+		uart0: serial@2000 {
+			compatible = "ns16550a";
+			reg = <0x2000 0x100>;
 
-	interrupt-parent = <&intc>;
-	interrupts = <30>;
-};
+			clocks = <&lx_clk>;
 
-&uart1 {
-	/delete-property/ clock-frequency;
-	clocks = <&lx_clk>;
+			interrupt-parent = <&intc>;
+			interrupts = <30>;
 
-	interrupt-parent = <&intc>;
-	interrupts = <31>;
-};
+			reg-io-width = <1>;
+			reg-shift = <2>;
+			fifo-size = <1>;
+			no-loopback-test;
 
+			status = "disabled";
+		};
+
+		uart1: serial@2100 {
+			compatible = "ns16550a";
+			reg = <0x2100 0x100>;
+
+			clocks = <&lx_clk>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <31>;
+
+			reg-io-width = <1>;
+			reg-shift = <2>;
+			fifo-size = <1>;
+			no-loopback-test;
+
+			status = "disabled";
+		};
+	};
+};
-- 
2.48.1

[PATCH 2/9] mips: dts: realtek: Clean up CPU clocks

[Sander Vanheule]

The referenced CPU clock does not require any additional #clock-cells,
so drop the extraneous '0' in the referenced CPU clock.

The binding for MIPS cpus also does not allow for the clock-names
property, so just drop it.

This resolves some error message from 'dtbs_check':
    cpu@0: clocks: [[4], [0]] is too long
    'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 3 +--
 arch/mips/boot/dts/realtek/rtl930x.dtsi | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index 722106e39194..d2c6baabb38c 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -9,8 +9,7 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "mips,mips4KEc";
 			reg = <0>;
-			clocks = <&baseclk 0>;
-			clock-names = "cpu";
+			clocks = <&baseclk>;
 		};
 	};
 
diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi
index 67261d6fcaa7..f2e57ea3a60c 100644
--- a/arch/mips/boot/dts/realtek/rtl930x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi
@@ -26,8 +26,7 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "mips,mips34Kc";
 			reg = <0>;
-			clocks = <&baseclk 0>;
-			clock-names = "cpu";
+			clocks = <&baseclk>;
 		};
 	};
 
-- 
2.48.1

[PATCH 3/9] mips: dts: realtek: Add address to SoC node name

[Sander Vanheule]

Although not strictly required by the simple-bus binding, add the bus
offset to the node name to be consistent with other nodes. Also drop the
node label as it is not referenced anywhere.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl83xx.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
index 03ddc61f7c9e..1039cb50c7da 100644
--- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
@@ -16,7 +16,7 @@ cpuintc: cpuintc {
 		interrupt-controller;
 	};
 
-	soc: soc {
+	soc@18000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-- 
2.48.1

[PATCH 4/9] mips: dts: realtek: Fold rtl83xx into rtl838x

[Sander Vanheule]

rtl83xx.dtsi was once (presumably) created as a base for both RTL838x
and RTL839x SoCs. Both SoCs have a different CPU and the peripherals
require different compatibles. Fold rtl83xx.dtsi into rtl838x.dtsi,
currently only supporting RTL838x SoCs, and create the RTL839x base
include later when required.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/cisco_sg220-26.dts |  1 -
 arch/mips/boot/dts/realtek/rtl838x.dtsi       | 56 ++++++++++++++++++
 arch/mips/boot/dts/realtek/rtl83xx.dtsi       | 59 -------------------
 3 files changed, 56 insertions(+), 60 deletions(-)
 delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi

diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
index 1cdbb09297ef..cb85d172a1d3 100644
--- a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
+++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
@@ -2,7 +2,6 @@
 
 /dts-v1/;
 
-#include "rtl83xx.dtsi"
 #include "rtl838x.dtsi"
 
 / {
diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index d2c6baabb38c..907449094536 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -1,6 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
 
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -18,4 +26,52 @@ baseclk: baseclk {
 		#clock-cells = <0>;
 		clock-frequency = <500000000>;
 	};
+
+	cpuintc: cpuintc {
+		compatible = "mti,cpu-interrupt-controller";
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	soc@18000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x18000000 0x10000>;
+
+		uart0: serial@2000 {
+			compatible = "ns16550a";
+			reg = <0x2000 0x100>;
+
+			clock-frequency = <200000000>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <31>;
+
+			reg-io-width = <1>;
+			reg-shift = <2>;
+			fifo-size = <1>;
+			no-loopback-test;
+
+			status = "disabled";
+		};
+
+		uart1: serial@2100 {
+			compatible = "ns16550a";
+			reg = <0x2100 0x100>;
+
+			clock-frequency = <200000000>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <30>;
+
+			reg-io-width = <1>;
+			reg-shift = <2>;
+			fifo-size = <1>;
+			no-loopback-test;
+
+			status = "disabled";
+		};
+	};
 };
diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
deleted file mode 100644
index 1039cb50c7da..000000000000
--- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-	};
-
-	cpuintc: cpuintc {
-		compatible = "mti,cpu-interrupt-controller";
-		#address-cells = <0>;
-		#interrupt-cells = <1>;
-		interrupt-controller;
-	};
-
-	soc@18000000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x0 0x18000000 0x10000>;
-
-		uart0: serial@2000 {
-			compatible = "ns16550a";
-			reg = <0x2000 0x100>;
-
-			clock-frequency = <200000000>;
-
-			interrupt-parent = <&cpuintc>;
-			interrupts = <31>;
-
-			reg-io-width = <1>;
-			reg-shift = <2>;
-			fifo-size = <1>;
-			no-loopback-test;
-
-			status = "disabled";
-		};
-
-		uart1: serial@2100 {
-			compatible = "ns16550a";
-			reg = <0x2100 0x100>;
-
-			clock-frequency = <200000000>;
-
-			interrupt-parent = <&cpuintc>;
-			interrupts = <30>;
-
-			reg-io-width = <1>;
-			reg-shift = <2>;
-			fifo-size = <1>;
-			no-loopback-test;
-
-			status = "disabled";
-		};
-	};
-};
-- 
2.48.1

[PATCH 5/9] mips: dts: realtek: Add SoC IRQ node for RTL838x

[Sander Vanheule]

Add the SoC interrupt controller so other components can link to it.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index 907449094536..21fb584e6383 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -73,5 +73,15 @@ uart1: serial@2100 {
 
 			status = "disabled";
 		};
+
+		intc: interrupt-controller@3000 {
+			compatible = "realtek,rtl8380-intc", "realtek,rtl-intc";
+			reg = <0x3000 0x20>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>, <3>, <4>, <5>, <6>;
+		};
 	};
 };
-- 
2.48.1

[PATCH 6/9] mips: dts: realtek: Correct uart interrupt-parent

[Sander Vanheule]

The uart interrupts on RTL838x chips do not lead to the CPU's interrupt
controller directly, but passes via the SoC interrupt controller. Update
the interrupt-parent property to fix this.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index 21fb584e6383..e3183a71765e 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -46,7 +46,7 @@ uart0: serial@2000 {
 
 			clock-frequency = <200000000>;
 
-			interrupt-parent = <&cpuintc>;
+			interrupt-parent = <&intc>;
 			interrupts = <31>;
 
 			reg-io-width = <1>;
@@ -63,7 +63,7 @@ uart1: serial@2100 {
 
 			clock-frequency = <200000000>;
 
-			interrupt-parent = <&cpuintc>;
+			interrupt-parent = <&intc>;
 			interrupts = <30>;
 
 			reg-io-width = <1>;
-- 
2.48.1

[PATCH 7/9] mips: dts: realtek: Replace uart clock property

[Sander Vanheule]

Add a fixed clock to define the clock frequency of the Lexra bus and use
this for the two uart nodes instead of a separate clock-frequency
property.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index e3183a71765e..246f4f607128 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -34,6 +34,12 @@ cpuintc: cpuintc {
 		interrupt-controller;
 	};
 
+	lx_clk: clock-lexra {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
 	soc@18000000 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -44,7 +50,7 @@ uart0: serial@2000 {
 			compatible = "ns16550a";
 			reg = <0x2000 0x100>;
 
-			clock-frequency = <200000000>;
+			clocks = <&lx_clk>;
 
 			interrupt-parent = <&intc>;
 			interrupts = <31>;
@@ -61,7 +67,7 @@ uart1: serial@2100 {
 			compatible = "ns16550a";
 			reg = <0x2100 0x100>;
 
-			clock-frequency = <200000000>;
+			clocks = <&lx_clk>;
 
 			interrupt-parent = <&intc>;
 			interrupts = <30>;
-- 
2.48.1

[PATCH 8/9] mips: dts: realtek: Add RTL838x SoC peripherals

[Sander Vanheule]

Add some of the SoC's CPU peripherals currently supported:
  - GPIO controller with support for 24 GPIO lines, although not all
    lines are brought out to pads on the SoC package. These lines can
    generate interrupts from external sources.
  - Watchdog which can be used to restart the SoC if no external restart
    logic is present.
  - SPI controller, primarily used to access NOR flash

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/rtl838x.dtsi | 36 +++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
index 246f4f607128..ce522a6af262 100644
--- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
+++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
@@ -46,6 +46,14 @@ soc@18000000 {
 		#size-cells = <1>;
 		ranges = <0x0 0x18000000 0x10000>;
 
+		spi0: spi@1200 {
+			compatible = "realtek,rtl8380-spi";
+			reg = <0x1200 0x100>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		uart0: serial@2000 {
 			compatible = "ns16550a";
 			reg = <0x2000 0x100>;
@@ -89,5 +97,33 @@ intc: interrupt-controller@3000 {
 			interrupt-parent = <&cpuintc>;
 			interrupts = <2>, <3>, <4>, <5>, <6>;
 		};
+
+		watchdog: watchdog@3150 {
+			compatible = "realtek,rtl8380-wdt";
+			reg = <0x3150 0xc>;
+
+			realtek,reset-mode = "soc";
+
+			clocks = <&lx_clk>;
+			timeout-sec = <20>;
+
+			interrupt-parent = <&intc>;
+			interrupt-names = "phase1", "phase2";
+			interrupts = <19>, <18>;
+		};
+
+		gpio0: gpio@3500 {
+			compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
+			reg = <0x3500 0x1c>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupts = <23>;
+		};
 	};
 };
-- 
2.48.1

[PATCH 9/9] mips: dts: realtek: Add restart to Cisco SG220-26P

[Sander Vanheule]

Define a gpio-restart node to the Cisco SG220-26P so the device can be
rebooted using the SoC's hard reset pin. Set the priority to 192 so the
gpio-restart method takes priority over the watchdog restart.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
 arch/mips/boot/dts/realtek/cisco_sg220-26.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
index cb85d172a1d3..fab3d552404d 100644
--- a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
+++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
@@ -4,6 +4,8 @@
 
 #include "rtl838x.dtsi"
 
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	model = "Cisco SG220-26";
 	compatible = "cisco,sg220-26", "realtek,rtl8382-soc";
@@ -17,6 +19,13 @@ memory@0 {
 		device_type = "memory";
 		reg = <0x0 0x8000000>;
 	};
+
+	gpio-restart {
+		compatible = "gpio-restart";
+		gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		priority = <192>;
+		open-source;
+	};
 };
 
 &uart0 {
-- 
2.48.1

Re: [PATCH 1/9] mips: dts: realtek: Decouple RTL930x base DTSI

[Chris Packham]

Hi Sander

On 20/01/2025 07:34, Sander Vanheule wrote:
> The RTL930x SoC series is sufficiently different to warrant its own base
> dtsi. This ensures no properties need to be deleted or overwritten, and
> prevents accidental inclusions of updates from rtl83xx.dtsi.
>
> Signed-off-by: Sander Vanheule <sander@svanheule.net>

Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # For RTL9302C

> ---
>   arch/mips/boot/dts/realtek/rtl930x.dtsi | 133 +++++++++++++++---------
>   1 file changed, 83 insertions(+), 50 deletions(-)
>
> diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi
> index 17577457d159..67261d6fcaa7 100644
> --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi
> +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi
> @@ -1,10 +1,23 @@
>   // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
>   
> -#include "rtl83xx.dtsi"
> -
>   / {
>   	compatible = "realtek,rtl9302-soc";
>   
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
> +	cpuintc: cpuintc {
> +		compatible = "mti,cpu-interrupt-controller";
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -58,64 +71,84 @@ i2c1: i2c@388 {
>   			status = "disabled";
>   		};
>   	};
> -};
>   
> -&soc {
> -	ranges = <0x0 0x18000000 0x20000>;
> +	soc: soc@18000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x18000000 0x20000>;
>   
> -	intc: interrupt-controller@3000 {
> -		compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
> -		reg = <0x3000 0x18>, <0x3018 0x18>;
> -		interrupt-controller;
> -		#interrupt-cells = <1>;
> +		intc: interrupt-controller@3000 {
> +			compatible = "realtek,rtl9300-intc", "realtek,rtl-intc";
> +			reg = <0x3000 0x18>, <0x3018 0x18>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
>   
> -		interrupt-parent = <&cpuintc>;
> -		interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
> -	};
> +			interrupt-parent = <&cpuintc>;
> +			interrupts = <2>, <3>, <4>, <5>, <6>, <7>;
> +		};
>   
> -	spi0: spi@1200 {
> -		compatible = "realtek,rtl8380-spi";
> -		reg = <0x1200 0x100>;
> +		spi0: spi@1200 {
> +			compatible = "realtek,rtl8380-spi";
> +			reg = <0x1200 0x100>;
>   
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -	};
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
>   
> -	timer0: timer@3200 {
> -		compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
> -		reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
> -		    <0x3230 0x10>, <0x3240 0x10>;
> +		timer0: timer@3200 {
> +			compatible = "realtek,rtl9302-timer", "realtek,otto-timer";
> +			reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
> +			    <0x3230 0x10>, <0x3240 0x10>;
>   
> -		interrupt-parent = <&intc>;
> -		interrupts = <7>, <8>, <9>, <10>, <11>;
> -		clocks = <&lx_clk>;
> -	};
> +			interrupt-parent = <&intc>;
> +			interrupts = <7>, <8>, <9>, <10>, <11>;
> +			clocks = <&lx_clk>;
> +		};
>   
> -	snand: spi@1a400 {
> -		compatible = "realtek,rtl9301-snand";
> -		reg = <0x1a400 0x44>;
> -		interrupt-parent = <&intc>;
> -		interrupts = <19>;
> -		clocks = <&lx_clk>;
> -		#address-cells = <1>;
> -		#size-cells = <0>;
> -		status = "disabled";
> -	};
> -};
> +		snand: spi@1a400 {
> +			compatible = "realtek,rtl9301-snand";
> +			reg = <0x1a400 0x44>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <19>;
> +			clocks = <&lx_clk>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			status = "disabled";
> +		};
>   
> -&uart0 {
> -	/delete-property/ clock-frequency;
> -	clocks = <&lx_clk>;
> +		uart0: serial@2000 {
> +			compatible = "ns16550a";
> +			reg = <0x2000 0x100>;
>   
> -	interrupt-parent = <&intc>;
> -	interrupts = <30>;
> -};
> +			clocks = <&lx_clk>;
>   
> -&uart1 {
> -	/delete-property/ clock-frequency;
> -	clocks = <&lx_clk>;
> +			interrupt-parent = <&intc>;
> +			interrupts = <30>;
>   
> -	interrupt-parent = <&intc>;
> -	interrupts = <31>;
> -};
> +			reg-io-width = <1>;
> +			reg-shift = <2>;
> +			fifo-size = <1>;
> +			no-loopback-test;
>   
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@2100 {
> +			compatible = "ns16550a";
> +			reg = <0x2100 0x100>;
> +
> +			clocks = <&lx_clk>;
> +
> +			interrupt-parent = <&intc>;
> +			interrupts = <31>;
> +
> +			reg-io-width = <1>;
> +			reg-shift = <2>;
> +			fifo-size = <1>;
> +			no-loopback-test;
> +
> +			status = "disabled";
> +		};
> +	};
> +};

Re: [PATCH 2/9] mips: dts: realtek: Clean up CPU clocks

[Chris Packham]

Hi Sander,

On 20/01/2025 07:34, Sander Vanheule wrote:
> The referenced CPU clock does not require any additional #clock-cells,
> so drop the extraneous '0' in the referenced CPU clock.
>
> The binding for MIPS cpus also does not allow for the clock-names
> property, so just drop it.
>
> This resolves some error message from 'dtbs_check':
>      cpu@0: clocks: [[4], [0]] is too long
>      'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Signed-off-by: Sander Vanheule <sander@svanheule.net>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz> # For RTL9302C
> ---
>   arch/mips/boot/dts/realtek/rtl838x.dtsi | 3 +--
>   arch/mips/boot/dts/realtek/rtl930x.dtsi | 3 +--
>   2 files changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
> index 722106e39194..d2c6baabb38c 100644
> --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
> +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
> @@ -9,8 +9,7 @@ cpu@0 {
>   			device_type = "cpu";
>   			compatible = "mips,mips4KEc";
>   			reg = <0>;
> -			clocks = <&baseclk 0>;
> -			clock-names = "cpu";
> +			clocks = <&baseclk>;
>   		};
>   	};
>   
> diff --git a/arch/mips/boot/dts/realtek/rtl930x.dtsi b/arch/mips/boot/dts/realtek/rtl930x.dtsi
> index 67261d6fcaa7..f2e57ea3a60c 100644
> --- a/arch/mips/boot/dts/realtek/rtl930x.dtsi
> +++ b/arch/mips/boot/dts/realtek/rtl930x.dtsi
> @@ -26,8 +26,7 @@ cpu@0 {
>   			device_type = "cpu";
>   			compatible = "mips,mips34Kc";
>   			reg = <0>;
> -			clocks = <&baseclk 0>;
> -			clock-names = "cpu";
> +			clocks = <&baseclk>;
>   		};
>   	};
>   

Re: [PATCH 3/9] mips: dts: realtek: Add address to SoC node name

[Chris Packham]

On 20/01/2025 07:34, Sander Vanheule wrote:
> Although not strictly required by the simple-bus binding, add the bus
> offset to the node name to be consistent with other nodes. Also drop the
> node label as it is not referenced anywhere.
>
> Signed-off-by: Sander Vanheule <sander@svanheule.net>

Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

> ---
>   arch/mips/boot/dts/realtek/rtl83xx.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
> index 03ddc61f7c9e..1039cb50c7da 100644
> --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi
> +++ b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
> @@ -16,7 +16,7 @@ cpuintc: cpuintc {
>   		interrupt-controller;
>   	};
>   
> -	soc: soc {
> +	soc@18000000 {
>   		compatible = "simple-bus";
>   		#address-cells = <1>;
>   		#size-cells = <1>;

Re: [PATCH 4/9] mips: dts: realtek: Fold rtl83xx into rtl838x

[Chris Packham]

On 20/01/2025 07:34, Sander Vanheule wrote:
> rtl83xx.dtsi was once (presumably) created as a base for both RTL838x
> and RTL839x SoCs. Both SoCs have a different CPU and the peripherals
> require different compatibles. Fold rtl83xx.dtsi into rtl838x.dtsi,
> currently only supporting RTL838x SoCs, and create the RTL839x base
> include later when required.
>
> Signed-off-by: Sander Vanheule <sander@svanheule.net>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>   arch/mips/boot/dts/realtek/cisco_sg220-26.dts |  1 -
>   arch/mips/boot/dts/realtek/rtl838x.dtsi       | 56 ++++++++++++++++++
>   arch/mips/boot/dts/realtek/rtl83xx.dtsi       | 59 -------------------
>   3 files changed, 56 insertions(+), 60 deletions(-)
>   delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi
>
> diff --git a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
> index 1cdbb09297ef..cb85d172a1d3 100644
> --- a/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
> +++ b/arch/mips/boot/dts/realtek/cisco_sg220-26.dts
> @@ -2,7 +2,6 @@
>   
>   /dts-v1/;
>   
> -#include "rtl83xx.dtsi"
>   #include "rtl838x.dtsi"
>   
>   / {
> diff --git a/arch/mips/boot/dts/realtek/rtl838x.dtsi b/arch/mips/boot/dts/realtek/rtl838x.dtsi
> index d2c6baabb38c..907449094536 100644
> --- a/arch/mips/boot/dts/realtek/rtl838x.dtsi
> +++ b/arch/mips/boot/dts/realtek/rtl838x.dtsi
> @@ -1,6 +1,14 @@
>   // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
>   
>   / {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +	};
> +
>   	cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
> @@ -18,4 +26,52 @@ baseclk: baseclk {
>   		#clock-cells = <0>;
>   		clock-frequency = <500000000>;
>   	};
> +
> +	cpuintc: cpuintc {
> +		compatible = "mti,cpu-interrupt-controller";
> +		#address-cells = <0>;
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +	};
> +
> +	soc@18000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x18000000 0x10000>;
> +
> +		uart0: serial@2000 {
> +			compatible = "ns16550a";
> +			reg = <0x2000 0x100>;
> +
> +			clock-frequency = <200000000>;
> +
> +			interrupt-parent = <&cpuintc>;
> +			interrupts = <31>;
> +
> +			reg-io-width = <1>;
> +			reg-shift = <2>;
> +			fifo-size = <1>;
> +			no-loopback-test;
> +
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@2100 {
> +			compatible = "ns16550a";
> +			reg = <0x2100 0x100>;
> +
> +			clock-frequency = <200000000>;
> +
> +			interrupt-parent = <&cpuintc>;
> +			interrupts = <30>;
> +
> +			reg-io-width = <1>;
> +			reg-shift = <2>;
> +			fifo-size = <1>;
> +			no-loopback-test;
> +
> +			status = "disabled";
> +		};
> +	};
>   };
> diff --git a/arch/mips/boot/dts/realtek/rtl83xx.dtsi b/arch/mips/boot/dts/realtek/rtl83xx.dtsi
> deleted file mode 100644
> index 1039cb50c7da..000000000000
> --- a/arch/mips/boot/dts/realtek/rtl83xx.dtsi
> +++ /dev/null
> @@ -1,59 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
> -
> -/ {
> -	#address-cells = <1>;
> -	#size-cells = <1>;
> -
> -	aliases {
> -		serial0 = &uart0;
> -		serial1 = &uart1;
> -	};
> -
> -	cpuintc: cpuintc {
> -		compatible = "mti,cpu-interrupt-controller";
> -		#address-cells = <0>;
> -		#interrupt-cells = <1>;
> -		interrupt-controller;
> -	};
> -
> -	soc@18000000 {
> -		compatible = "simple-bus";
> -		#address-cells = <1>;
> -		#size-cells = <1>;
> -		ranges = <0x0 0x18000000 0x10000>;
> -
> -		uart0: serial@2000 {
> -			compatible = "ns16550a";
> -			reg = <0x2000 0x100>;
> -
> -			clock-frequency = <200000000>;
> -
> -			interrupt-parent = <&cpuintc>;
> -			interrupts = <31>;
> -
> -			reg-io-width = <1>;
> -			reg-shift = <2>;
> -			fifo-size = <1>;
> -			no-loopback-test;
> -
> -			status = "disabled";
> -		};
> -
> -		uart1: serial@2100 {
> -			compatible = "ns16550a";
> -			reg = <0x2100 0x100>;
> -
> -			clock-frequency = <200000000>;
> -
> -			interrupt-parent = <&cpuintc>;
> -			interrupts = <30>;
> -
> -			reg-io-width = <1>;
> -			reg-shift = <2>;
> -			fifo-size = <1>;
> -			no-loopback-test;
> -
> -			status = "disabled";
> -		};
> -	};
> -};

Re: [PATCH 0/9] mips: dts: Split Realtek devicetrees

[Thomas Bogendoerfer]

On Sun, Jan 19, 2025 at 07:34:15PM +0100, Sander Vanheule wrote:
> This patch series intends to clean up the base includes, shared between
> hardware devicetrees. To get rid of some dtbs_check warnings, some cpu
> clock prorerties are also modified.
> 
> To indicate why the split-up is required, the series concludes with
> adding some CPU peripherals to rtl838x.dtsi, which are then used to add
> a gpio-restart for the Cisco SG220-26P.
> 
> Sander Vanheule (9):
>   mips: dts: realtek: Decouple RTL930x base DTSI
>   mips: dts: realtek: Clean up CPU clocks
>   mips: dts: realtek: Add address to SoC node name
>   mips: dts: realtek: Fold rtl83xx into rtl838x
>   mips: dts: realtek: Add SoC IRQ node for RTL838x
>   mips: dts: realtek: Correct uart interrupt-parent
>   mips: dts: realtek: Replace uart clock property
>   mips: dts: realtek: Add RTL838x SoC peripherals
>   mips: dts: realtek: Add restart to Cisco SG220-26P
> 
>  arch/mips/boot/dts/realtek/cisco_sg220-26.dts |  10 +-
>  arch/mips/boot/dts/realtek/rtl838x.dtsi       | 111 +++++++++++++-
>  arch/mips/boot/dts/realtek/rtl83xx.dtsi       |  59 --------
>  arch/mips/boot/dts/realtek/rtl930x.dtsi       | 136 +++++++++++-------
>  4 files changed, 202 insertions(+), 114 deletions(-)
>  delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi

series applied to mips-next

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH 0/9] mips: dts: Split Realtek devicetrees

[Sander Vanheule]

Hi Thomas,

On Fri, 2025-02-21 at 16:27 +0100, Thomas Bogendoerfer wrote:
> On Sun, Jan 19, 2025 at 07:34:15PM +0100, Sander Vanheule wrote:
> > This patch series intends to clean up the base includes, shared between
> > hardware devicetrees. To get rid of some dtbs_check warnings, some cpu
> > clock prorerties are also modified.
> > 
> > To indicate why the split-up is required, the series concludes with
> > adding some CPU peripherals to rtl838x.dtsi, which are then used to add
> > a gpio-restart for the Cisco SG220-26P.
> > 
> > Sander Vanheule (9):
> >   mips: dts: realtek: Decouple RTL930x base DTSI
> >   mips: dts: realtek: Clean up CPU clocks
> >   mips: dts: realtek: Add address to SoC node name
> >   mips: dts: realtek: Fold rtl83xx into rtl838x
> >   mips: dts: realtek: Add SoC IRQ node for RTL838x
> >   mips: dts: realtek: Correct uart interrupt-parent
> >   mips: dts: realtek: Replace uart clock property
> >   mips: dts: realtek: Add RTL838x SoC peripherals
> >   mips: dts: realtek: Add restart to Cisco SG220-26P
> > 
> >  arch/mips/boot/dts/realtek/cisco_sg220-26.dts |  10 +-
> >  arch/mips/boot/dts/realtek/rtl838x.dtsi       | 111 +++++++++++++-
> >  arch/mips/boot/dts/realtek/rtl83xx.dtsi       |  59 --------
> >  arch/mips/boot/dts/realtek/rtl930x.dtsi       | 136 +++++++++++-------
> >  4 files changed, 202 insertions(+), 114 deletions(-)
> >  delete mode 100644 arch/mips/boot/dts/realtek/rtl83xx.dtsi
> 
> series applied to mips-next

Thanks!

Best,
Sander