[PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller

[Shawn Lin <shawn.lin@rock-chips.com>]

Currently, when pcie-dw-rockchip uses the Synopsys PHY, it relies on
the phy_init() callback of the phy-rockchip-snps-pcie3 driver to
perform calibration. This is incorrect because the controller is
still held in reset at that time, preventing the PHY from accurately
reflecting the actual PLL lock and calibration status.

To fix this, this series:
1. Calls phy_calibrate() in the pcie-dw-rockchip driver (if supported)
   after the controller is out of reset, ensuring the PHY can
   properly synchronize with the controller state.
2. Adds the necessary calibration support in the Synopsys PHY driver
   to implement this callback.

Please review and test.



Shawn Lin (5):
  PCI: dw-rockchip: Add phy_calibrate() to check PHY lock status
  phy: rockchip-snps-pcie3: Add phy_calibrate() support
  phy: rockchip-snps-pcie3: Increase sram init timeout
  phy: rockchip-snps-pcie3: Check more sram init status for RK3588
  phy: rockchip-snps-pcie3: Only check PHY1 status when using it

 drivers/pci/controller/dwc/pcie-dw-rockchip.c  |  9 +++-
 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 61 +++++++++++++++++++++-----
 2 files changed, 57 insertions(+), 13 deletions(-)

-- 
2.7.4