From: Shawn Lin <shawn.lin@rock-chips.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Vinod Koul <vkoul@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>,
Neil Armstrong <neil.armstrong@linaro.org>,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH 4/5] phy: rockchip-snps-pcie3: Check more sram init status for RK3588
Date: Wed, 24 Dec 2025 15:10:09 +0800 [thread overview]
Message-ID: <1766560210-100883-5-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1766560210-100883-1-git-send-email-shawn.lin@rock-chips.com>
All the lower 4 bits should be checked which shows the mpllx_state.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index f5a5d0af..6cc38e3 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -43,7 +43,7 @@
#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
-#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
+#define RK3588_SRAM_INIT_DONE(reg) ((reg & 0xf) == 0xf)
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
--
2.7.4
next prev parent reply other threads:[~2025-12-24 7:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-24 7:10 [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Shawn Lin
2025-12-24 7:10 ` [PATCH 1/5] PCI: dw-rockchip: Add phy_calibrate() to check PHY lock status Shawn Lin
2026-01-13 14:34 ` Manivannan Sadhasivam
2025-12-24 7:10 ` [PATCH 2/5] phy: rockchip-snps-pcie3: Add phy_calibrate() support Shawn Lin
2025-12-24 7:10 ` [PATCH 3/5] phy: rockchip-snps-pcie3: Increase sram init timeout Shawn Lin
2026-01-14 13:29 ` Vinod Koul
2026-01-15 0:30 ` Shawn Lin
2025-12-24 7:10 ` Shawn Lin [this message]
2025-12-24 7:10 ` [PATCH 5/5] phy: rockchip-snps-pcie3: Only check PHY1 status when using it Shawn Lin
2026-01-14 15:43 ` [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Niklas Cassel
2026-01-15 0:41 ` Shawn Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1766560210-100883-5-git-send-email-shawn.lin@rock-chips.com \
--to=shawn.lin@rock-chips.com \
--cc=bhelgaas@google.com \
--cc=heiko@sntech.de \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=mani@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=sebastian.reichel@collabora.com \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox