Linux PCI subsystem development
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From: Shawn Lin <shawn.lin@rock-chips.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Vinod Koul <vkoul@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-phy@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Sebastian Reichel <sebastian.reichel@collabora.com>,
	Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH 5/5] phy: rockchip-snps-pcie3: Only check PHY1 status when using it
Date: Wed, 24 Dec 2025 15:10:10 +0800	[thread overview]
Message-ID: <1766560210-100883-6-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1766560210-100883-1-git-send-email-shawn.lin@rock-chips.com>

RK3588_LANE_AGGREGATION and RK3588_BIFURCATION_LANE_2_3 should be
used to check if it need to check PHY1 status. Because in other
cases, only PHY0 could show locked status.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 6cc38e3..36b2142 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -183,6 +183,7 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
 	}
 
 	reg = mode;
+	priv->pcie30_phymode = mode;
 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
 		     RK3588_PCIE30_PHY_MODE_EN | reg);
 
@@ -208,10 +209,13 @@ static int rockchip_p3phy_rk3588_calibrate(struct rockchip_p3phy_priv *priv)
 				       RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
 				       reg, RK3588_SRAM_INIT_DONE(reg),
 				       0, RK_SRAM_INIT_TIMEOUT_US);
-	ret |= regmap_read_poll_timeout(priv->phy_grf,
-					RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
-					reg, RK3588_SRAM_INIT_DONE(reg),
-					0, RK_SRAM_INIT_TIMEOUT_US);
+	if (priv->pcie30_phymode & (RK3588_LANE_AGGREGATION | RK3588_BIFURCATION_LANE_2_3)) {
+		ret |= regmap_read_poll_timeout(priv->phy_grf,
+						RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
+						reg, RK3588_SRAM_INIT_DONE(reg),
+						0, RK_SRAM_INIT_TIMEOUT_US);
+	}
+
 	if (ret)
 		dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
 			reg);
-- 
2.7.4


  parent reply	other threads:[~2025-12-24  7:17 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-24  7:10 [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Shawn Lin
2025-12-24  7:10 ` [PATCH 1/5] PCI: dw-rockchip: Add phy_calibrate() to check PHY lock status Shawn Lin
2026-01-13 14:34   ` Manivannan Sadhasivam
2025-12-24  7:10 ` [PATCH 2/5] phy: rockchip-snps-pcie3: Add phy_calibrate() support Shawn Lin
2025-12-24  7:10 ` [PATCH 3/5] phy: rockchip-snps-pcie3: Increase sram init timeout Shawn Lin
2026-01-14 13:29   ` Vinod Koul
2026-01-15  0:30     ` Shawn Lin
2025-12-24  7:10 ` [PATCH 4/5] phy: rockchip-snps-pcie3: Check more sram init status for RK3588 Shawn Lin
2025-12-24  7:10 ` Shawn Lin [this message]
2026-01-14 15:43 ` [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Niklas Cassel
2026-01-15  0:41   ` Shawn Lin

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