Re: [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller

[Shawn Lin <shawn.lin@rock-chips.com>]

在 2026/01/14 星期三 23:43, Niklas Cassel 写道:
> On Wed, Dec 24, 2025 at 03:10:05PM +0800, Shawn Lin wrote:
>>
>> Currently, when pcie-dw-rockchip uses the Synopsys PHY, it relies on
>> the phy_init() callback of the phy-rockchip-snps-pcie3 driver to
>> perform calibration. This is incorrect because the controller is
>> still held in reset at that time, preventing the PHY from accurately
>> reflecting the actual PLL lock and calibration status.
> 
> Hello Shawn,
> 
> I can see that you move the calibration code from .phy_init() to
> .phy_calibrate().
> 
> And I understandthat the controller is still held in reset.
> 
> I understand that the the PHY calibration is supposed to be done
> when the controller is not held in reset, and that alone is
> enough to warrant a fix.

Sure.

> 
> The Synopsys Gen3 PHY is used in e.g. Rock5b, and link training
> currently works fine with this PHY, so what is the actual

It just happended to work as in most cases, the calibration finished
very quickly after controller is not held in reset.

> implications of performing the PHY calibration when the controller
> is held in reset?
> 
> Will it somehow it improve signal integrity?
> 

Performing the PHY calibration when the controller is held
in reset is the wrong way. If the refclk or PHY power supply isn't
ready, the bogus calibration still passes, then the system will get
stuck when accessing DBI. So performing the PHY calibration must be done
after controller quit the reset state.

> 
> Kind regards,
> Niklas
> 
>>
>> To fix this, this series:
>> 1. Calls phy_calibrate() in the pcie-dw-rockchip driver (if supported)
>>     after the controller is out of reset, ensuring the PHY can
>>     properly synchronize with the controller state.
>> 2. Adds the necessary calibration support in the Synopsys PHY driver
>>     to implement this callback.
>