From: Shawn Lin <shawn.lin@rock-chips.com>
To: Manivannan Sadhasivam <mani@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Vinod Koul <vkoul@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-phy@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>,
Neil Armstrong <neil.armstrong@linaro.org>,
Sebastian Reichel <sebastian.reichel@collabora.com>,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH 3/5] phy: rockchip-snps-pcie3: Increase sram init timeout
Date: Wed, 24 Dec 2025 15:10:08 +0800 [thread overview]
Message-ID: <1766560210-100883-4-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1766560210-100883-1-git-send-email-shawn.lin@rock-chips.com>
Per massive test, 500us is not enough for all chips, increase it
to 20000us for worse case recommended.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 9933cda..f5a5d0af 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -19,6 +19,9 @@
#include <linux/regmap.h>
#include <linux/reset.h>
+/* Common definition */
+#define RK_SRAM_INIT_TIMEOUT_US 20000
+
/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1 0x4
#define GRF_PCIE30PHY_CON6 0x18
@@ -28,6 +31,7 @@
#define GRF_PCIE30PHY_WR_EN (0xf << 16)
#define SRAM_INIT_DONE(reg) (reg & BIT(14))
+
#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
/* Register for RK3588 */
@@ -134,7 +138,7 @@ static int rockchip_p3phy_rk3568_calibrate(struct rockchip_p3phy_priv *priv)
ret = regmap_read_poll_timeout(priv->phy_grf,
GRF_PCIE30PHY_STATUS0,
reg, SRAM_INIT_DONE(reg),
- 0, 500);
+ 0, RK_SRAM_INIT_TIMEOUT_US);
if (ret)
dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
reg);
@@ -203,11 +207,11 @@ static int rockchip_p3phy_rk3588_calibrate(struct rockchip_p3phy_priv *priv)
ret = regmap_read_poll_timeout(priv->phy_grf,
RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
reg, RK3588_SRAM_INIT_DONE(reg),
- 0, 500);
+ 0, RK_SRAM_INIT_TIMEOUT_US);
ret |= regmap_read_poll_timeout(priv->phy_grf,
RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
reg, RK3588_SRAM_INIT_DONE(reg),
- 0, 500);
+ 0, RK_SRAM_INIT_TIMEOUT_US);
if (ret)
dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
reg);
--
2.7.4
next prev parent reply other threads:[~2025-12-24 7:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-24 7:10 [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Shawn Lin
2025-12-24 7:10 ` [PATCH 1/5] PCI: dw-rockchip: Add phy_calibrate() to check PHY lock status Shawn Lin
2026-01-13 14:34 ` Manivannan Sadhasivam
2025-12-24 7:10 ` [PATCH 2/5] phy: rockchip-snps-pcie3: Add phy_calibrate() support Shawn Lin
2025-12-24 7:10 ` Shawn Lin [this message]
2026-01-14 13:29 ` [PATCH 3/5] phy: rockchip-snps-pcie3: Increase sram init timeout Vinod Koul
2026-01-15 0:30 ` Shawn Lin
2025-12-24 7:10 ` [PATCH 4/5] phy: rockchip-snps-pcie3: Check more sram init status for RK3588 Shawn Lin
2025-12-24 7:10 ` [PATCH 5/5] phy: rockchip-snps-pcie3: Only check PHY1 status when using it Shawn Lin
2026-01-14 15:43 ` [PATCH 0/5] Add calibration for Synopsys PCIe PHY and Controller Niklas Cassel
2026-01-15 0:41 ` Shawn Lin
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