Re: [PATCH v6 03/13] PCI: tegra194: Don't force the device into the D0 state before L2

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:11, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device
> should be in D3 state to assert wake# pin. This takes precedence over PCI
> Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
> which states that the device can be put into D0 state before taking the
> link to L2 state. So, to enable the wake functionality for endpoints, do
> not force the devices to D0 state before taking the link to L2 state.
> There is no functional issue with the endpoints where the link doesn't go
> into L2 state (the reason why the earlier change was made in the first
> place) as the root port proceeds with the usual flow post PME timeout.
> 
> Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 41 ----------------------
>  1 file changed, 41 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4ac6b1cea13f..808a1e213b79 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1261,44 +1261,6 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
>  	return 0;
>  }
>  
> -static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
> -{
> -	struct dw_pcie_rp *pp = &pcie->pci.pp;
> -	struct pci_bus *child, *root_port_bus = NULL;
> -	struct pci_dev *pdev;
> -
> -	/*
> -	 * link doesn't go into L2 state with some of the endpoints with Tegra
> -	 * if they are not in D0 state. So, need to make sure that immediate
> -	 * downstream devices are in D0 state before sending PME_TurnOff to put
> -	 * link into L2 state.
> -	 * This is as per PCI Express Base r4.0 v1.0 September 27-2017,
> -	 * 5.2 Link State Power Management (Page #428).
> -	 */
> -
> -	list_for_each_entry(child, &pp->bridge->bus->children, node) {
> -		if (child->parent == pp->bridge->bus) {
> -			root_port_bus = child;
> -			break;
> -		}
> -	}
> -
> -	if (!root_port_bus) {
> -		dev_err(pcie->dev, "Failed to find downstream bus of Root Port\n");
> -		return;
> -	}
> -
> -	/* Bring downstream devices to D0 if they are not already in */
> -	list_for_each_entry(pdev, &root_port_bus->devices, bus_list) {
> -		if (PCI_SLOT(pdev->devfn) == 0) {
> -			if (pci_set_power_state(pdev, PCI_D0))
> -				dev_err(pcie->dev,
> -					"Failed to transition %s to D0 state\n",
> -					dev_name(&pdev->dev));
> -		}
> -	}
> -}
> -
>  static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
>  {
>  	pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
> @@ -1627,7 +1589,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>  
>  static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>  {
> -	tegra_pcie_downstream_dev_to_D0(pcie);
>  	dw_pcie_host_deinit(&pcie->pci.pp);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
> @@ -2337,7 +2298,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>  	if (!pcie->link_state)
>  		return 0;
>  
> -	tegra_pcie_downstream_dev_to_D0(pcie);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
>  
> @@ -2411,7 +2371,6 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
>  			return;
>  
>  		debugfs_remove_recursive(pcie->debugfs);
> -		tegra_pcie_downstream_dev_to_D0(pcie);
>  
>  		disable_irq(pcie->pci.pp.irq);
>  		if (IS_ENABLED(CONFIG_PCI_MSI))

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>