Re: [PATCH v6 07/13] PCI: tegra194: Set LTR message request before PCIe link up

[Vidya Sagar <vidyas@nvidia.com>]

On 24/02/26 00:11, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@nvidia.com>
> 
> LTR message should be sent as soon as the root port enables LTR in the
> endpoint. Set snoop & no snoop LTR timing and LTR message request before
> PCIe links up. This ensures that LTR message is sent upstream as soon as
> LTR is enabled.
> 
> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> Changes V1 -> V6: None
> 
>  drivers/pci/controller/dwc/pcie-tegra194.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index a6868b77e3b7..ad1056d68d6d 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -124,6 +124,7 @@
>  
>  #define APPL_LTR_MSG_1				0xC4
>  #define LTR_MSG_REQ				BIT(15)
> +#define LTR_MST_NO_SNOOP_SHIFT			16
>  #define LTR_NOSNOOP_MSG_REQ			BIT(31)
>  
>  #define APPL_LTR_MSG_2				0xC8
> @@ -488,15 +489,6 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
>  	if (val & PCI_COMMAND_MASTER) {
>  		ktime_t timeout;
>  
> -		/* 110us for both snoop and no-snoop */
> -		val = FIELD_PREP(PCI_LTR_VALUE_MASK, 110) |
> -		      FIELD_PREP(PCI_LTR_SCALE_MASK, 2) |
> -		      LTR_MSG_REQ |
> -		      FIELD_PREP(PCI_LTR_NOSNOOP_VALUE, 110) |
> -		      FIELD_PREP(PCI_LTR_NOSNOOP_SCALE, 2) |
> -		      LTR_NOSNOOP_MSG_REQ;
> -		appl_writel(pcie, val, APPL_LTR_MSG_1);
> -
>  		/* Send LTR upstream */
>  		val = appl_readl(pcie, APPL_LTR_MSG_2);
>  		val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
> @@ -1805,6 +1797,11 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
>  	val |= APPL_INTR_EN_L1_0_0_RDLH_LINK_UP_INT_EN;
>  	appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>  
> +	/* 110us for both snoop and no-snoop */
> +	val = 110 | (2 << PCI_LTR_SCALE_SHIFT) | LTR_MSG_REQ;
> +	val |= (val << LTR_MST_NO_SNOOP_SHIFT);
> +	appl_writel(pcie, val, APPL_LTR_MSG_1);
> +
>  	reset_control_deassert(pcie->core_rst);
>  
>  	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);

Reviewed-by: Vidya Sagar <vidyas@nvidia.com>