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* [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi
@ 2025-11-12  2:58 Shawn Lin
  2025-11-13  0:59 ` Bjorn Helgaas
  0 siblings, 1 reply; 4+ messages in thread
From: Shawn Lin @ 2025-11-12  2:58 UTC (permalink / raw)
  To: Bjorn Helgaas; +Cc: linux-pci, Shawn Lin

This Wi-Fi advertises the L0s and L1 capabilities but actually
it doesn't support them. This's comfirmed by Hisilicon team in
actual productization.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v2:
- rebase on linux-next
- use DECLARE_PCI_FIXUP_HEADER(Bjorn)

 drivers/pci/quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 44e7807..24c2788 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2536,6 +2536,7 @@ static void quirk_disable_aspm_l0s_l1_cap(struct pci_dev *dev)
 	pci_info(dev, "ASPM: L0s L1 removed from Link Capabilities to work around device defect\n");
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1_cap);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1_cap);
 
 /*
  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi
  2025-11-12  2:58 [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi Shawn Lin
@ 2025-11-13  0:59 ` Bjorn Helgaas
  2025-11-13  1:47   ` Shawn Lin
  0 siblings, 1 reply; 4+ messages in thread
From: Bjorn Helgaas @ 2025-11-13  0:59 UTC (permalink / raw)
  To: Shawn Lin; +Cc: Bjorn Helgaas, linux-pci

On Wed, Nov 12, 2025 at 10:58:39AM +0800, Shawn Lin wrote:
> This Wi-Fi advertises the L0s and L1 capabilities but actually
> it doesn't support them. This's comfirmed by Hisilicon team in
> actual productization.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

Applied to pci/for-linus, planning for v6.18.

> ---
> 
> Changes in v2:
> - rebase on linux-next
> - use DECLARE_PCI_FIXUP_HEADER(Bjorn)
> 
>  drivers/pci/quirks.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 44e7807..24c2788 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2536,6 +2536,7 @@ static void quirk_disable_aspm_l0s_l1_cap(struct pci_dev *dev)
>  	pci_info(dev, "ASPM: L0s L1 removed from Link Capabilities to work around device defect\n");
>  }
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1_cap);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1_cap);
>  
>  /*
>   * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
> -- 
> 2.7.4
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi
  2025-11-13  0:59 ` Bjorn Helgaas
@ 2025-11-13  1:47   ` Shawn Lin
  2025-11-13 12:19     ` Bjorn Helgaas
  0 siblings, 1 reply; 4+ messages in thread
From: Shawn Lin @ 2025-11-13  1:47 UTC (permalink / raw)
  To: Bjorn Helgaas; +Cc: shawn.lin, Bjorn Helgaas, linux-pci

在 2025/11/13 星期四 8:59, Bjorn Helgaas 写道:
> On Wed, Nov 12, 2025 at 10:58:39AM +0800, Shawn Lin wrote:
>> This Wi-Fi advertises the L0s and L1 capabilities but actually
>> it doesn't support them. This's comfirmed by Hisilicon team in
>> actual productization.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> 
> Applied to pci/for-linus, planning for v6.18.


Thanks Bjorn. By checking the for-linus branch, I found an error.

This patch is based on linux-next, but if it's for v6.18, I think we
need to use quirk_disable_aspm_l0s_l1 instead of 
quirk_disable_aspm_l0s_l1_cap.

> 
>> ---
>>
>> Changes in v2:
>> - rebase on linux-next
>> - use DECLARE_PCI_FIXUP_HEADER(Bjorn)
>>
>>   drivers/pci/quirks.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>> index 44e7807..24c2788 100644
>> --- a/drivers/pci/quirks.c
>> +++ b/drivers/pci/quirks.c
>> @@ -2536,6 +2536,7 @@ static void quirk_disable_aspm_l0s_l1_cap(struct pci_dev *dev)
>>   	pci_info(dev, "ASPM: L0s L1 removed from Link Capabilities to work around device defect\n");
>>   }
>>   DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1_cap);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1_cap);
>>   
>>   /*
>>    * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
>> -- 
>> 2.7.4
>>
> 


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi
  2025-11-13  1:47   ` Shawn Lin
@ 2025-11-13 12:19     ` Bjorn Helgaas
  0 siblings, 0 replies; 4+ messages in thread
From: Bjorn Helgaas @ 2025-11-13 12:19 UTC (permalink / raw)
  To: Shawn Lin; +Cc: Bjorn Helgaas, linux-pci

On Thu, Nov 13, 2025 at 09:47:30AM +0800, Shawn Lin wrote:
> 在 2025/11/13 星期四 8:59, Bjorn Helgaas 写道:
> > On Wed, Nov 12, 2025 at 10:58:39AM +0800, Shawn Lin wrote:
> > > This Wi-Fi advertises the L0s and L1 capabilities but actually
> > > it doesn't support them. This's comfirmed by Hisilicon team in
> > > actual productization.
> > > 
> > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> > 
> > Applied to pci/for-linus, planning for v6.18.
> 
> Thanks Bjorn. By checking the for-linus branch, I found an error.
> 
> This patch is based on linux-next, but if it's for v6.18, I think we
> need to use quirk_disable_aspm_l0s_l1 instead of
> quirk_disable_aspm_l0s_l1_cap.

Sigh, yep, sorry about that.  Fixed.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2025-11-13 12:19 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-12  2:58 [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi Shawn Lin
2025-11-13  0:59 ` Bjorn Helgaas
2025-11-13  1:47   ` Shawn Lin
2025-11-13 12:19     ` Bjorn Helgaas

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