Re: [PATCH] PCI: Fix PCIe SBR dev/link wait error

[Bjorn Helgaas <helgaas@kernel.org>]

On Mon, Nov 24, 2025 at 06:45:02PM +0800, Guanghui Feng wrote:
> When executing a PCIe secondary bus reset, all downstream switches and
> endpoints will generate reset events. Simultaneously, all PCIe links
> will undergo retraining, and each link will independently re-execute the
> LTSSM state machine training. Therefore, after executing the SBR, it is
> necessary to wait for all downstream links and devices to complete
> recovery. Otherwise, after the SBR returns, accessing devices with some
> links or endpoints not yet fully recovered may result in driver errors,
> or even trigger device offline issues.

I guess this solves a problem you have observed?

Are there any specific details you can share that would help
illustrate the problem?  E.g., cases where we do a Secondary Bus
Reset, then access a downstream device too early, and an error
happens?

Bjorn