Re: [PATCH] PCI: Fix PCIe SBR dev/link wait error

["guanghuifeng@linux.alibaba.com" <guanghuifeng@linux.alibaba.com>]

在 2025/12/1 18:03, Lukas Wunner 写道:
> On Tue, Nov 25, 2025 at 02:20:10PM +0800, guanghui.fgh wrote:
>> After __pci_reset_slot/__pci_reset_bus calls
>> pci_bridge_wait_for_secondary_bus, the device will be restored via
>> pci_dev_restore. However, when a multifunction PCIe device is connected,
>> executing pci_bridge_wait_for_secondary_bus only guarantees the restoration
>> of a random device. For other devices that are still restoring, executing
>> pci_dev_restore cannot restore the device state normally, resulting in
>> errors or even device offline.
> PCIe is point-to-point, i.e. at the two ends of a link there's only a
> single physical device.  So if there are multiple pci_dev's on a bus,
> they're additional functions or VFs of the same physical device.
>
> The expectation is that if the first device on the bus is accessible,
> all other functions of the same physical device are accessible as well.
> That's why we only wait for the first device to become accessible.
>
> It seems highly unusual that the different functions of the same physical
> device require different delays until they're accessible.  I don't think
> we can accept such a sweeping change wholesale without more details,
> so please share what the topology looks like (lspci -tv), what devices are
> involved (lspci -vvv) and which device requires extra wait time for some
> of its functions.
>
> Thanks,
>
> Lukas

1. For PCIe end-to-end/point-to-point connections, PCIe multifunctions 
do indeed share the same PCIe links/lanes.
2. However, the functions within a PCIe multifunction device have 
different functionalities and complexities.

    During the hot reset process, each function requires a different 
recovery time. Therefore, after confirming

    that the PCIe links are functioning correctly, it is necessary to 
further check to ensure that each function has completed its recovery.