Re: [PATCH v3] PCI: Fix PCIe SBR dev/link wait error

["guanghuifeng@linux.alibaba.com" <guanghuifeng@linux.alibaba.com>]

在 2025/12/1 17:24, Ilpo Järvinen 写道:
> On Sun, 30 Nov 2025, Guanghui Feng wrote:
>
>> When executing a PCIe secondary bus reset, all downstream switches and
>> endpoints will generate reset events. Simultaneously, all PCIe links
>> will undergo retraining, and each link will independently re-execute the
>> LTSSM state machine training. Therefore, after executing the SBR, it is
>> necessary to wait for all downstream links and devices to complete
>> recovery. Otherwise, after the SBR returns, accessing devices with some
>> links or endpoints not yet fully recovered may result in driver errors,
>> or even trigger device offline issues.
>>
>> Signed-off-by: Guanghui Feng <guanghuifeng@linux.alibaba.com>
>> Reviewed-by: Guixin Liu <kanie@linux.alibaba.com>
>> ---
> The review comment I gave to v2 still stands to this v3 as well.
>
> Please don't send new versions too rapidly but give people time to comment
> on the previous version. And please remember to explain what you changed
> in each version (below the -- line).

Thanks.

Compared to v2, patch v3 only modifies the implementation of

pci_bridge_wait_for_secondary_bus.

Patch v2 directly used a longer msleep timer, while v3 modifies

it to use a sequentially amplified msleep timer, allowing for more

timely detection of switch, link, and device recovery completion,

thus reducing the overall SBR waiting time.