Re: [PATCH v4 v4 1/1] PCI: Fix PCIe SBR dev/link wait error

[Bjorn Helgaas <helgaas@kernel.org>]

[+cc Lukas (please always cc people who have commented on previous
iterations of your patch)]

On Tue, Dec 02, 2025 at 10:49:01AM -0600, Bjorn Helgaas wrote:
> On Tue, Dec 02, 2025 at 12:32:07PM +0800, Guanghui Feng wrote:
> > When executing a PCIe secondary bus reset, all downstream switches and
> > endpoints will generate reset events. Simultaneously, all PCIe links
> > will undergo retraining, and each link will independently re-execute the
> > LTSSM state machine training. Therefore, after executing the SBR, it is
> > necessary to wait for all downstream links and devices to complete
> > recovery. Otherwise, after the SBR returns, accessing devices with some
> > links or endpoints not yet fully recovered may result in driver errors,
> > or even trigger device offline issues.
> > 
> > Signed-off-by: Guanghui Feng <guanghuifeng@linux.alibaba.com>
> > Reviewed-by: Guixin Liu <kanie@linux.alibaba.com>
> 
> Can you please supply the lspci information Lukas requested here?
> https://lore.kernel.org/r/aS1oArFHeo9FAuv-@wunner.de
> 
> Also, if there is language in the PCIe spec you can cite here about
> the need to independently wait for each device, that would be useful.
> 
> Bjorn