Re: [PATCH v9 11/11] PCI/CXL: Restore HDM state after CXL bus reset

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] HDM decoder restoration is performed before the PCI device's BARs are restored, causing MMIO writes to be dropped by the hardware or triggering Unsupported Requests.
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--- Patch [11]: [PATCH v9 11/11] PCI/CXL: Restore HDM state after CXL bus reset ---
commit 4e02f0f18a7abbebc3cc9b8384269906531ad726
Author: Srirangan Madhavan <smadhavan@nvidia.com>

PCI/CXL: Restore HDM state after CXL bus reset

This commit restores cached HDM state after a successful CXL bus reset while
the IOMMU reset block remains active. It introduces a helper to restore the
state and calls it directly from the PCI reset path.

> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index ef25ba5f7fe95..b394704950a5f 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5004,6 +5004,9 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
>  		pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL,
>  				      reg);
>  
> +	if (!rc)
> +		rc = cxl_restore_hdm_after_pci_reset(dev);
> +

[Severity: High]
Is it safe to restore the HDM decoders here before the PCI state (including
BARs) has been restored?

When pci_reset_bus_function() is called earlier in this function, the
hardware reset clears the device's BARs to 0. The caller of the reset
function typically restores the saved PCI state after this returns.

However, cxl_restore_hdm_after_pci_reset() calls cxl_restore_hdm(), which
enables memory decoding and writes to the cached BAR address:

drivers/cxl/core/reset.c:cxl_restore_hdm() {
    ...
    rc = cxl_hdm_enable_mem(pdev, &command, &restore_command);
    ...
    writel(global_ctrl, hdm + CXL_HDM_DECODER_CTRL_OFFSET);
    ...
}

Because the hardware BARs are still 0 at this point, will enabling
PCI_COMMAND_MEMORY cause the device to incorrectly claim physical address 0?

Furthermore, will the MMIO writes to the cached BAR address result in PCIe
Unsupported Requests (Master Aborts) since the hardware isn't actually
decoding the cached address yet?

>  	pci_dev_reset_iommu_done(dev);
>  	return rc;
>  }

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Sashiko AI review · https://sashiko.dev/#/patchset/20260709010304.680422-1-smadhavan@nvidia.com?part=11