Linux PCI subsystem development
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-pci@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v9 07/11] PCI/CXL: Discover the CXL reset scope
Date: Thu, 09 Jul 2026 01:24:07 +0000	[thread overview]
Message-ID: <20260709012408.0B5401F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260709010304.680422-8-smadhavan@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] CXL Reset scope validation is conditionally bypassed during actual reset execution, creating a TOCTOU vulnerability that fails to protect siblings.
--

--- Patch [7]: [PATCH v9 07/11] PCI/CXL: Discover the CXL reset scope ---
commit 363800e2ebd7dad78179683be8d0a027b5bd8a7e
Author: Srirangan Madhavan <smadhavan@nvidia.com>

PCI/CXL: Discover the CXL reset scope

This commit adds reset context support to validate that a CXL Reset is
function-scoped before advertising it as a PCI reset method. It uses the
Non-CXL Function Map, ARI/devfn rules, and CXL capability bits to reject
the reset if another same-scope function would be affected.

> diff --git a/drivers/cxl/core/reset.c b/drivers/cxl/core/reset.c
> index fb741b66e5022..cdfaa699583d2 100644
> --- a/drivers/cxl/core/reset.c
> +++ b/drivers/cxl/core/reset.c
[ ... ]
> @@ -890,6 +1037,7 @@ static int cxl_reset_execute(struct pci_dev *pdev, int dvsec)
>  int cxl_reset_function(struct pci_dev *pdev, bool probe)
>  {
>  	struct cxl_hdm_range_context range_ctx;
> +	struct cxl_reset_context ctx;
>  	int dvsec;
>  	int rc;
>  
> @@ -897,8 +1045,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
>  	if (dvsec < 0)
>  		return dvsec;
>  
> +	cxl_reset_context_init(&ctx, pdev);
>  	if (probe)
> -		return 0;
> +		return cxl_reset_validate_function_scoped(&ctx);

[Severity: High]
Is it safe to conditionally bypass scope validation when probe is false?

During the early probe phase, when this is called from pci_init_capabilities()
for Function 0, higher-numbered sibling functions might not have been
enumerated and added to the bus list yet. As a result,
cxl_reset_validate_function_scoped() could find no siblings and incorrectly
report the reset as safe.

Later, when a user or driver actually triggers the reset and this function
is called with probe=0, it skips validation and executes the reset directly.
Could this inadvertently reset and destroy the state of active sibling
functions that were enumerated after the initial probe?

>  
>  	cxl_hdm_range_context_init(&range_ctx);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260709010304.680422-1-smadhavan@nvidia.com?part=7

  reply	other threads:[~2026-07-09  1:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-09  1:02 [PATCH v9 00/11] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-07-09  1:02 ` [PATCH v9 01/11] cxl: Split decoder programming into a reusable helper Srirangan Madhavan
2026-07-09  1:14   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 02/11] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-07-09  1:16   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 03/11] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-07-09  1:18   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 04/11] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-07-09  1:17   ` sashiko-bot
2026-07-09  3:30   ` Alison Schofield
2026-07-10  0:48   ` Dan Williams (nvidia)
2026-07-09  1:02 ` [PATCH v9 05/11] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-07-09  1:15   ` sashiko-bot
2026-07-09  1:02 ` [PATCH v9 06/11] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-07-09  1:28   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 07/11] PCI/CXL: Discover the CXL reset scope Srirangan Madhavan
2026-07-09  1:24   ` sashiko-bot [this message]
2026-07-10  1:00   ` Dan Williams (nvidia)
2026-07-09  1:03 ` [PATCH v9 08/11] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-07-09  1:17   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 09/11] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-07-09  1:27   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 10/11] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-07-09  1:05   ` sashiko-bot
2026-07-09  1:03 ` [PATCH v9 11/11] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-07-09  1:20   ` sashiko-bot

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260709012408.0B5401F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    --cc=smadhavan@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox