Re: [PATCH 1/2] PCI/DPC: Clear Interrupt Status in dpc_reset_link()

[Keith Busch <kbusch@kernel.org>]

On Thu, Feb 12, 2026 at 10:36:12PM +0100, Lukas Wunner wrote:
> On Thu, Feb 12, 2026 at 11:18:17AM -0800, Danielle Costantino wrote:
> > Clear PCI_EXP_DPC_STATUS_INTERRUPT alongside PCI_EXP_DPC_STATUS_TRIGGER
> > in dpc_reset_link().  Both bits are RW1C in the DPC Status register per
> > PCIe r6.1, sec 7.9.14.5, so writing them together is safe.  The native
> > path is unaffected because dpc_irq() has already cleared the Interrupt
> > Status bit before dpc_reset_link() runs.
> 
> Hm, doesn't this create a risk that in the native case, an interrupt may
> be lost (i.e. cleared without acting on it) if it occurs between clearing
> the bit in dpc_irq() and clearing it in dpc_reset_link()?
> 
> Maybe I'm missing something and this isn't a problem, but in that case
> an explanation in the commit message would be good *why* it's not a
> problem.

The Trigger Status remains set, so the containment is latched for entire
processing. You can't get a 2nd containment event while the port is
already in containment. It's just important to clear the interrupt
status bit in the top-half mainly for level-triggered interrupts. I
think it would be harmless if the OS deferred the clearing to the
bottom-half when using edge triggered interrupts, though.