Re: [PATCH 1/2] PCI/DPC: Clear Interrupt Status in dpc_reset_link()

[Keith Busch <kbusch@kernel.org>]

On Thu, Feb 12, 2026 at 08:28:15PM -0800, Sathyanarayanan Kuppuswamy wrote:
> Hi Keith,
> 
> On 2/12/26 5:22 PM, Keith Busch wrote:
> > On Thu, Feb 12, 2026 at 02:51:46PM -0800, Kuppuswamy Sathyanarayanan wrote:
> > > On 2/12/2026 2:12 PM, Keith Busch wrote:
> > > 
> > > As per EDR flow, firmware waits for _OST reply from OS to complete the
> > > current interrupt handling. After receiving _OST, firmware decides whether
> > > recovery should continue or if the link should be disabled. When/how firmware
> > > handles subsequent DPC events depends on firmware's implementation.
> > You at least agree the OS controls the "Trigger Status". That controls
> > whether the link stays contained or not, but now you're saying the
> > firmware gets to yank the link after the OS returns _OST success?
> > There's no flow in the spec suggesting any such behavior.
> 
> I was referring to the flow chart and notes on page 85, in PCI firmware spec,
> v3.3, which mention firmware can choose to disable the link in certain
> cases (notes 3,5).
 
Err, what? No, there is no path for firmware to disable the link if OS
returns _OST  0x80 (success). The path says firmware is supposed to
"Clear ...  Disable Link", not to disable the link.

If the firmware wants to disable the link permanently, it does so before
considering DPC and makes it a hotplug event instead.  

But in all honesty, that diagram is a complete mess and very poorly
captures what an OS is supposed to do for a DPC. You don't unbind the
drivers when you're trying to recover the devices they're driving.