From: Alison Schofield <alison.schofield@intel.com>
To: Koichiro Den <den@valinux.co.jp>
Cc: Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
Dan Williams <djbw@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
"Ira Weiny" <iweiny@kernel.org>, Li Ming <ming.li@zohomail.com>,
Richard Cheng <icheng@nvidia.com>,
Terry Bowman <terry.bowman@amd.com>,
Alejandro Lucero <alucerop@amd.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH 2/3] cxl: Account for link width in latency calculation
Date: Fri, 9 Oct 2026 11:26:09 -0700 [thread overview]
Message-ID: <askxwXq0chgJepD_@aschofie-mobl2.lan> (raw)
In-Reply-To: <20261009045452.1107921-3-den@valinux.co.jp>
On Fri, Oct 09, 2026 at 01:54:51PM +0900, Koichiro Den wrote:
> cxl_pci_get_latency() derives bandwidth from the per-lane speed returned
> by pcie_link_speed_mbps(), ignoring the negotiated link width. This
> overestimates the FlitLatency contribution for multi-lane links.
> Sections 2.11.3 and 2.11.4 of the Intel CXL Memory Device Software Guide
> describe the link bandwidth as the product of the negotiated speed and
> width.
>
> Replace pcie_link_speed_mbps() with pcie_link_bandwidth_mbps() and
> migrate both CXL callers (the only users of the API). The new helper
> obtains speed and width from a single Link Status read. The CXL
> bandwidth calculation no longer needs a separate width read and
> multiplication.
>
> While at it, make error handling more robust by converting PCI config
> read errors to negative errno values and checking for zero bandwidth
> before calculating latency.
It would be nice to include the link here to the mentioned guide:
[1] https://www.intel.com/content/www/us/en/content-details/643805/cxl-memory-device-software-guide.html
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
next prev parent reply other threads:[~2026-10-09 18:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
2026-10-09 4:54 ` [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot
2026-10-09 18:22 ` Alison Schofield
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
2026-10-09 5:01 ` sashiko-bot
2026-10-09 15:09 ` Bjorn Helgaas
2026-10-09 18:26 ` Alison Schofield [this message]
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
2026-10-09 5:02 ` sashiko-bot
2026-10-09 18:27 ` Alison Schofield
2026-10-09 17:15 ` [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Dave Jiang
2026-10-09 21:49 ` Dave Jiang
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