Re: [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units

[Dave Jiang <dave.jiang@intel.com>]

On 10/8/26 9:54 PM, Koichiro Den wrote:
> Hi,
> 
> This small series intends to correct the FlitLatency portion of the link
> latency calculation, as per Intel CXL Type 3 Memory Device Software
> Guide 1.1, and restore picosecond latency units for the QTG _DSM input.
> 
> The first two issues were found while debugging a QEMU guest. The third
> issue was spotted while looking through the code that uses the coord
> values. I haven't tested it on real hardware.
> 
> Best regards,
> Koichiro Den
> 
> 
> Koichiro Den (3):
>   cxl/port: Convert PCIe link latency to nanoseconds
>   cxl: Account for link width in latency calculation
>   cxl/acpi: Convert QTG _DSM latencies to picoseconds
> 
>  drivers/cxl/acpi.c      | 10 ++++++++--
>  drivers/cxl/core/pci.c  | 22 ++++++++--------------
>  drivers/cxl/core/port.c |  3 +++
>  drivers/pci/pci.c       | 23 ++++++++++++++++++-----
>  include/linux/pci.h     |  2 +-
>  5 files changed, 38 insertions(+), 22 deletions(-)
> 
> 
> base-commit: 71392a644e88c6bb921cdf12cb2b00adec070fe4

Thanks for the fix!
For the series:
Reviewed-by: Dave Jiang <dave.jiang@intel.com>