* [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
@ 2026-10-09 4:54 ` Koichiro Den
2026-10-09 5:02 ` sashiko-bot
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
2 siblings, 1 reply; 8+ messages in thread
From: Koichiro Den @ 2026-10-09 4:54 UTC (permalink / raw)
To: Dave Jiang, Davidlohr Bueso, Jonathan Cameron, Alison Schofield,
Vishal Verma, Dan Williams, Bjorn Helgaas
Cc: Ira Weiny, Li Ming, Richard Cheng, Terry Bowman, Alejandro Lucero,
linux-cxl, linux-kernel, linux-pci
Commit 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
converted CDAT latencies to nanoseconds and removed the conversion in
cxl_region_perf_data_calculate(), but left PCIe link latencies in
picoseconds.
This inflates the FlitLatency contribution to region and node latencies
by a factor of 1000, exposing incorrect values in sysfs. The resulting
abstract distances can incorrectly reverse the memory tier ordering of
nodes.
Convert the FlitLatency contribution to nanoseconds before adding it to
the access coordinates, rounding up as cdat_normalize() does.
Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
Cc: stable@vger.kernel.org
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/cxl/core/port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 6024bc9c1376..08d9a7b8855c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2339,6 +2339,9 @@ EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, "CXL");
static void add_latency(struct access_coordinate *c, long latency)
{
+ /* Convert link latency from picoseconds to nanoseconds. */
+ latency = DIV_ROUND_UP(latency, 1000);
+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
c[i].write_latency += latency;
c[i].read_latency += latency;
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/3] cxl: Account for link width in latency calculation
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
2026-10-09 4:54 ` [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds Koichiro Den
@ 2026-10-09 4:54 ` Koichiro Den
2026-10-09 5:01 ` sashiko-bot
2026-10-09 15:09 ` Bjorn Helgaas
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
2 siblings, 2 replies; 8+ messages in thread
From: Koichiro Den @ 2026-10-09 4:54 UTC (permalink / raw)
To: Dave Jiang, Davidlohr Bueso, Jonathan Cameron, Alison Schofield,
Vishal Verma, Dan Williams, Bjorn Helgaas
Cc: Ira Weiny, Li Ming, Richard Cheng, Terry Bowman, Alejandro Lucero,
linux-cxl, linux-kernel, linux-pci
cxl_pci_get_latency() derives bandwidth from the per-lane speed returned
by pcie_link_speed_mbps(), ignoring the negotiated link width. This
overestimates the FlitLatency contribution for multi-lane links.
Sections 2.11.3 and 2.11.4 of the Intel CXL Memory Device Software Guide
describe the link bandwidth as the product of the negotiated speed and
width.
Replace pcie_link_speed_mbps() with pcie_link_bandwidth_mbps() and
migrate both CXL callers (the only users of the API). The new helper
obtains speed and width from a single Link Status read. The CXL
bandwidth calculation no longer needs a separate width read and
multiplication.
While at it, make error handling more robust by converting PCI config
read errors to negative errno values and checking for zero bandwidth
before calculating latency.
Fixes: 4d07a05397c8 ("cxl: Calculate and store PCI link latency for the downstream ports")
Cc: stable@vger.kernel.org
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/cxl/core/pci.c | 22 ++++++++--------------
drivers/pci/pci.c | 23 ++++++++++++++++++-----
include/linux/pci.h | 2 +-
3 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 43b9b7afff29..8b52621ffea1 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -660,8 +660,8 @@ long cxl_pci_get_latency(struct pci_dev *pdev)
{
long bw;
- bw = pcie_link_speed_mbps(pdev);
- if (bw < 0)
+ bw = pcie_link_bandwidth_mbps(pdev);
+ if (bw <= 0)
return 0;
bw /= BITS_PER_BYTE;
@@ -765,18 +765,12 @@ EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");
int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c)
{
- int speed, bw;
- u16 lnksta;
- u32 width;
-
- speed = pcie_link_speed_mbps(pdev);
- if (speed < 0)
- return speed;
- speed /= BITS_PER_BYTE;
-
- pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
- width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
- bw = speed * width;
+ int bw;
+
+ bw = pcie_link_bandwidth_mbps(pdev);
+ if (bw < 0)
+ return bw;
+ bw /= BITS_PER_BYTE;
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
c[i].read_bandwidth = bw;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b2879a6be5f8..aa3d180de56e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -5980,18 +5980,31 @@ static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
}
-int pcie_link_speed_mbps(struct pci_dev *pdev)
+/**
+ * pcie_link_bandwidth_mbps - get the current bandwidth of a single PCIe link
+ * @pdev: PCI device to query
+ *
+ * The bandwidth includes all negotiated lanes and does not account for
+ * encoding overhead. A negotiated width of zero gives zero bandwidth.
+ *
+ * Return: Bandwidth in Mb/s, or a negative errno on failure.
+ */
+int pcie_link_bandwidth_mbps(struct pci_dev *pdev)
{
u16 lnksta;
- int err;
+ int speed, err;
err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
if (err)
- return err;
+ return pcibios_err_to_errno(err);
+
+ speed = pcie_dev_speed_mbps(to_pcie_link_speed(lnksta));
+ if (speed < 0)
+ return speed;
- return pcie_dev_speed_mbps(to_pcie_link_speed(lnksta));
+ return speed * FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
}
-EXPORT_SYMBOL(pcie_link_speed_mbps);
+EXPORT_SYMBOL(pcie_link_bandwidth_mbps);
/**
* pcie_bandwidth_available - determine minimum link settings of a PCIe
diff --git a/include/linux/pci.h b/include/linux/pci.h
index d31a8d107b1e..bbfb0b98ff46 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1477,7 +1477,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps);
u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
enum pci_bus_speed *speed,
enum pcie_link_width *width);
-int pcie_link_speed_mbps(struct pci_dev *pdev);
+int pcie_link_bandwidth_mbps(struct pci_dev *pdev);
void pcie_print_link_status(struct pci_dev *dev);
int pcie_reset_flr(struct pci_dev *dev, bool probe);
int pcie_flr(struct pci_dev *dev);
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] cxl: Account for link width in latency calculation
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
@ 2026-10-09 5:01 ` sashiko-bot
2026-10-09 15:09 ` Bjorn Helgaas
1 sibling, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-10-09 5:01 UTC (permalink / raw)
To: Koichiro Den; +Cc: linux-pci, linux-cxl
> cxl_pci_get_latency() derives bandwidth from the per-lane speed returned
> by pcie_link_speed_mbps(), ignoring the negotiated link width. This
> overestimates the FlitLatency contribution for multi-lane links.
> Sections 2.11.3 and 2.11.4 of the Intel CXL Memory Device Software Guide
> describe the link bandwidth as the product of the negotiated speed and
> width.
>
> Replace pcie_link_speed_mbps() with pcie_link_bandwidth_mbps() and
> migrate both CXL callers (the only users of the API). The new helper
> obtains speed and width from a single Link Status read. The CXL
> bandwidth calculation no longer needs a separate width read and
> multiplication.
>
> While at it, make error handling more robust by converting PCI config
> read errors to negative errno values and checking for zero bandwidth
> before calculating latency.
>
> Fixes: 4d07a05397c8 ("cxl: Calculate and store PCI link latency for the downstream ports")
> Cc: stable@vger.kernel.org
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009045452.1107921-1-den@valinux.co.jp?part=2
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 2/3] cxl: Account for link width in latency calculation
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
2026-10-09 5:01 ` sashiko-bot
@ 2026-10-09 15:09 ` Bjorn Helgaas
1 sibling, 0 replies; 8+ messages in thread
From: Bjorn Helgaas @ 2026-10-09 15:09 UTC (permalink / raw)
To: Koichiro Den
Cc: Dave Jiang, Davidlohr Bueso, Jonathan Cameron, Alison Schofield,
Vishal Verma, Dan Williams, Bjorn Helgaas, Ira Weiny, Li Ming,
Richard Cheng, Terry Bowman, Alejandro Lucero, linux-cxl,
linux-kernel, linux-pci
On Fri, Oct 09, 2026 at 01:54:51PM +0900, Koichiro Den wrote:
> cxl_pci_get_latency() derives bandwidth from the per-lane speed returned
> by pcie_link_speed_mbps(), ignoring the negotiated link width. This
> overestimates the FlitLatency contribution for multi-lane links.
> Sections 2.11.3 and 2.11.4 of the Intel CXL Memory Device Software Guide
> describe the link bandwidth as the product of the negotiated speed and
> width.
>
> Replace pcie_link_speed_mbps() with pcie_link_bandwidth_mbps() and
> migrate both CXL callers (the only users of the API). The new helper
> obtains speed and width from a single Link Status read. The CXL
> bandwidth calculation no longer needs a separate width read and
> multiplication.
>
> While at it, make error handling more robust by converting PCI config
> read errors to negative errno values and checking for zero bandwidth
> before calculating latency.
>
> Fixes: 4d07a05397c8 ("cxl: Calculate and store PCI link latency for the downstream ports")
> Cc: stable@vger.kernel.org
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci/pci.c
> ---
> drivers/cxl/core/pci.c | 22 ++++++++--------------
> drivers/pci/pci.c | 23 ++++++++++++++++++-----
> include/linux/pci.h | 2 +-
> 3 files changed, 27 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 43b9b7afff29..8b52621ffea1 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -660,8 +660,8 @@ long cxl_pci_get_latency(struct pci_dev *pdev)
> {
> long bw;
>
> - bw = pcie_link_speed_mbps(pdev);
> - if (bw < 0)
> + bw = pcie_link_bandwidth_mbps(pdev);
> + if (bw <= 0)
> return 0;
> bw /= BITS_PER_BYTE;
>
> @@ -765,18 +765,12 @@ EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL");
>
> int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c)
> {
> - int speed, bw;
> - u16 lnksta;
> - u32 width;
> -
> - speed = pcie_link_speed_mbps(pdev);
> - if (speed < 0)
> - return speed;
> - speed /= BITS_PER_BYTE;
> -
> - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
> - width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
> - bw = speed * width;
> + int bw;
> +
> + bw = pcie_link_bandwidth_mbps(pdev);
> + if (bw < 0)
> + return bw;
> + bw /= BITS_PER_BYTE;
>
> for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
> c[i].read_bandwidth = bw;
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b2879a6be5f8..aa3d180de56e 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -5980,18 +5980,31 @@ static enum pci_bus_speed to_pcie_link_speed(u16 lnksta)
> return pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)];
> }
>
> -int pcie_link_speed_mbps(struct pci_dev *pdev)
> +/**
> + * pcie_link_bandwidth_mbps - get the current bandwidth of a single PCIe link
> + * @pdev: PCI device to query
> + *
> + * The bandwidth includes all negotiated lanes and does not account for
> + * encoding overhead. A negotiated width of zero gives zero bandwidth.
> + *
> + * Return: Bandwidth in Mb/s, or a negative errno on failure.
> + */
> +int pcie_link_bandwidth_mbps(struct pci_dev *pdev)
> {
> u16 lnksta;
> - int err;
> + int speed, err;
>
> err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta);
> if (err)
> - return err;
> + return pcibios_err_to_errno(err);
> +
> + speed = pcie_dev_speed_mbps(to_pcie_link_speed(lnksta));
> + if (speed < 0)
> + return speed;
>
> - return pcie_dev_speed_mbps(to_pcie_link_speed(lnksta));
> + return speed * FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
> }
> -EXPORT_SYMBOL(pcie_link_speed_mbps);
> +EXPORT_SYMBOL(pcie_link_bandwidth_mbps);
>
> /**
> * pcie_bandwidth_available - determine minimum link settings of a PCIe
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index d31a8d107b1e..bbfb0b98ff46 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -1477,7 +1477,7 @@ int pcie_set_mps(struct pci_dev *dev, int mps);
> u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
> enum pci_bus_speed *speed,
> enum pcie_link_width *width);
> -int pcie_link_speed_mbps(struct pci_dev *pdev);
> +int pcie_link_bandwidth_mbps(struct pci_dev *pdev);
> void pcie_print_link_status(struct pci_dev *dev);
> int pcie_reset_flr(struct pci_dev *dev, bool probe);
> int pcie_flr(struct pci_dev *dev);
> --
> 2.51.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds
2026-10-09 4:54 [PATCH 0/3] cxl: Fix link latency calculations and QTG latency units Koichiro Den
2026-10-09 4:54 ` [PATCH 1/3] cxl/port: Convert PCIe link latency to nanoseconds Koichiro Den
2026-10-09 4:54 ` [PATCH 2/3] cxl: Account for link width in latency calculation Koichiro Den
@ 2026-10-09 4:54 ` Koichiro Den
2026-10-09 5:02 ` sashiko-bot
2 siblings, 1 reply; 8+ messages in thread
From: Koichiro Den @ 2026-10-09 4:54 UTC (permalink / raw)
To: Dave Jiang, Davidlohr Bueso, Jonathan Cameron, Alison Schofield,
Vishal Verma, Dan Williams, Bjorn Helgaas
Cc: Ira Weiny, Li Ming, Richard Cheng, Terry Bowman, Alejandro Lucero,
linux-cxl, linux-kernel, linux-pci
The QTG _DSM expects read and write latencies in picoseconds, as
specified in CXL 3.0, Table 9-30.
The code base originally kept the latencies passed to the QTG _DSM in
picoseconds in effect. Commit 51293c565cf4 ("cxl: Fix incorrect region
perf data calculation") normalized CDAT and host bridge latencies to
nanoseconds, but did not add a conversion back to picoseconds when
constructing the _DSM input. Firmware can therefore select QTG IDs using
understated latencies.
Convert the latencies to picoseconds when constructing the _DSM input
package. Multiply in 64 bits and reject latencies that cannot fit in the
DWORD inputs defined by the specification.
Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
Cc: stable@vger.kernel.org
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
drivers/cxl/acpi.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fb09a5ff48c1..b7ce6b59c680 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -231,9 +231,10 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
int entries, int *qos_class)
{
union acpi_object *out_obj, *out_buf, *obj;
+ /* QTG _DSM expects latencies in picoseconds. */
union acpi_object in_array[4] = {
- [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
- [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
+ [0].integer = { ACPI_TYPE_INTEGER, coord->read_latency * 1000ULL },
+ [1].integer = { ACPI_TYPE_INTEGER, coord->write_latency * 1000ULL },
[2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
[3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
};
@@ -251,6 +252,11 @@ cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
if (!entries)
return -EINVAL;
+ /* Latency inputs must fit in the DWORD fields defined by the spec. */
+ if (coord->read_latency > U32_MAX / 1000 ||
+ coord->write_latency > U32_MAX / 1000)
+ return -ERANGE;
+
out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
if (!out_obj)
return -ENXIO;
--
2.51.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds
2026-10-09 4:54 ` [PATCH 3/3] cxl/acpi: Convert QTG _DSM latencies to picoseconds Koichiro Den
@ 2026-10-09 5:02 ` sashiko-bot
0 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-10-09 5:02 UTC (permalink / raw)
To: Koichiro Den; +Cc: linux-pci, linux-cxl
> The QTG _DSM expects read and write latencies in picoseconds, as
> specified in CXL 3.0, Table 9-30.
>
> The code base originally kept the latencies passed to the QTG _DSM in
> picoseconds in effect. Commit 51293c565cf4 ("cxl: Fix incorrect region
> perf data calculation") normalized CDAT and host bridge latencies to
> nanoseconds, but did not add a conversion back to picoseconds when
> constructing the _DSM input. Firmware can therefore select QTG IDs using
> understated latencies.
>
> Convert the latencies to picoseconds when constructing the _DSM input
> package. Multiply in 64 bits and reject latencies that cannot fit in the
> DWORD inputs defined by the specification.
>
> Fixes: 51293c565cf4 ("cxl: Fix incorrect region perf data calculation")
> Cc: stable@vger.kernel.org
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261009045452.1107921-1-den@valinux.co.jp?part=3
^ permalink raw reply [flat|nested] 8+ messages in thread