Re: [PATCH v10 04/18] perf capstone: Determine architecture from e_machine

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] RISC-V Capstone initialization omits the CS_MODE_RISCVC flag, breaking disassembly of compressed instructions.
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commit 18a82eb3adc97143851fdd5ceee9d79bbd3d188d
Author: Ian Rogers <irogers@google.com>

perf capstone: Determine architecture from e_machine

This patch updates Capstone initialization to use the ELF e_machine header
for architecture detection instead of relying on less precise architecture
strings. It also adds new e_machine translations for MIPS and RISC-V.

> diff --git a/tools/perf/util/capstone.c b/tools/perf/util/capstone.c
> index 25cf6e15ec272..065b5d4d448a3 100644
> --- a/tools/perf/util/capstone.c
> +++ b/tools/perf/util/capstone.c
[ ... ]
> @@ -137,37 +142,70 @@ static enum cs_err perf_cs_close(csh *handle)
[ ... ]
> +static bool e_machine_to_capstone(uint16_t e_machine, bool is64, bool is_big_endian,
> +				  enum cs_arch *arch, enum cs_mode *mode)
> +{
> +	*mode = is_big_endian ? CS_MODE_BIG_ENDIAN : CS_MODE_LITTLE_ENDIAN;
> +
> +	switch (e_machine) {
[ ... ]
> +	case EM_RISCV:
> +		*arch = CS_ARCH_RISCV;
> +		*mode |= is64 ? CS_MODE_RISCV64 : CS_MODE_RISCV32;

[Severity: Medium]
Does this initialization need the CS_MODE_RISCVC flag included in the mode
bitmask to decode RISC-V 16-bit compressed instructions?

Since almost all RISC-V Linux code uses the C extension (RV64GC), omitting
this flag could cause Capstone to encounter invalid opcodes on the first
compressed instruction.

Would this abort disassembly prematurely and force a fallback to objdump?

> +		return true;
> +	default:
> +		return false;
> +	}
> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260601065407.1597927-1-irogers@google.com?part=4