From: Peter Zijlstra <peterz@infradead.org>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
Falcon Thomas <thomas.falcon@intel.com>,
Xudong Hao <xudong.hao@intel.com>, Yi Lai <yi1.lai@intel.com>
Subject: Re: [Patch v2 7/9] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS
Date: Wed, 10 Jun 2026 10:23:25 +0200 [thread overview]
Message-ID: <20260610082325.GA49529@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20260610082051.GF49951@noisy.programming.kicks-ass.net>
On Wed, Jun 10, 2026 at 10:20:51AM +0200, Peter Zijlstra wrote:
> On Tue, Jun 09, 2026 at 01:02:20PM +0800, Dapeng Mi wrote:
> > On SPR guests where pebs_baseline is not advertised, running:
> >
> > $ ./perf record -e cpu/event=0x00,umask=0x01,i\
> > name=INST_RETIRED.PREC_DIST/p -c 10000 sleep 1
> >
> > can trigger:
> >
> > unchecked MSR access error: WRMSR to 0x3f1 ... in\
> > intel_pmu_pebs_enable_all()
> >
> > Root cause:
> > SPR-specific PEBS constraints allow fixed-counter scheduling,
> > for example INST_RETIRED.PREC_DIST on fixed counter 0. In guests without
> > pebs_baseline, KVM does not support PEBS sampling on fixed counters,
> > so enabling such events reaches an invalid MSR programming path.
> >
> > Fix:
> > Drop fixed-counter entries from the PEBS constraint table. Without
> > pebs_baseline, those fixed-counter PEBS events now resolve to empty
> > constraints and are not scheduled/enabled, avoiding the warning and the
> > broken guest PEBS path.
> >
> > This is safe because, in pebs_baseline-capable cases, PEBS constraint
> > lookup already falls back to non-PEBS constraints when needed, and
> > fixed-counter constraints are effectively shared there.
>
> I am confused, this works outside of KVM? (It appears to work fine on my
> spr).. so removing this to fix some guest only issue seems wrong.
>
Also, perf tools guys:
[ perf record: Woken up 1 times to write data ]
ERROR: Trying to write bpf_prog_info without libbpf support.
ERROR: Trying to write btf data without libbpf support.
[ perf record: Captured and wrote 0.041 MB perf.data (92 samples) ]
I explicitly build perf like:
make NO_LIBBPF=1 NO_LIBPYTHON=1 NO_LIBLLVM=1 NO_RUST=1
W.T.F does it even attempt to use libbpf and report and error about it
?!?!
(Also, I needed that NO_RUST because the build was full on crashing
without it)
next prev parent reply other threads:[~2026-06-10 8:23 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 5:02 [Patch v2 0/9] perf/x86: Miscellaneous PMU bug fixes Dapeng Mi
2026-06-09 5:02 ` [Patch v2 1/9] perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities Dapeng Mi
2026-06-09 5:02 ` [Patch v2 2/9] perf/x86: Introduce is_x86_pmu() helper Dapeng Mi
2026-06-09 5:02 ` [Patch v2 3/9] perf/x86: Update cap_user_rdpmc base on rdpmc user disable state Dapeng Mi
2026-06-09 14:48 ` Peter Zijlstra
2026-06-10 1:47 ` Mi, Dapeng
2026-06-09 5:02 ` [Patch v2 4/9] perf/x86/intel: Fallback to sw branch type decoding if no hw decoding Dapeng Mi
2026-06-09 5:24 ` sashiko-bot
2026-06-09 10:04 ` Mi, Dapeng
2026-06-09 14:49 ` Peter Zijlstra
2026-06-10 1:53 ` Mi, Dapeng
2026-06-09 5:02 ` [Patch v2 5/9] perf/x86/intel: Drop LBR entries whose privilege level mismatches br_sel Dapeng Mi
2026-06-09 5:21 ` sashiko-bot
2026-06-09 9:40 ` Mi, Dapeng
2026-06-09 14:52 ` Peter Zijlstra
2026-06-10 1:57 ` Mi, Dapeng
2026-06-09 5:02 ` [Patch v2 6/9] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Dapeng Mi
2026-06-09 5:25 ` sashiko-bot
2026-06-09 9:44 ` Mi, Dapeng
2026-06-10 8:16 ` Peter Zijlstra
2026-06-10 8:34 ` Mi, Dapeng
2026-06-09 5:02 ` [Patch v2 7/9] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS Dapeng Mi
2026-06-10 8:20 ` Peter Zijlstra
2026-06-10 8:23 ` Peter Zijlstra [this message]
2026-06-10 8:50 ` Mi, Dapeng
2026-06-10 11:21 ` Peter Zijlstra
2026-06-10 11:42 ` Mi, Dapeng
2026-06-10 22:22 ` Peter Zijlstra
2026-06-09 5:02 ` [Patch v2 8/9] perf/core: Fix kernel register info leak via hardware skid Dapeng Mi
2026-06-10 9:16 ` Peter Zijlstra
2026-06-09 5:02 ` [Patch v2 9/9] perf/core: Check kernel access when kernel callchains are requested Dapeng Mi
2026-06-09 5:24 ` sashiko-bot
2026-06-09 9:49 ` Mi, Dapeng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260610082325.GA49529@noisy.programming.kicks-ass.net \
--to=peterz@infradead.org \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=dapeng1.mi@intel.com \
--cc=dapeng1.mi@linux.intel.com \
--cc=eranian@google.com \
--cc=irogers@google.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=thomas.falcon@intel.com \
--cc=xudong.hao@intel.com \
--cc=yi1.lai@intel.com \
--cc=zide.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox