[PATCH 0/8] Power domains support for Exynos5433 SoCs

[PATCH 0/8] Power domains support for Exynos5433 SoCs

[Marek Szyprowski]

Hello,

This patchset is a final step to add support for all power domains
on Exynos5433 SoCs. This patchset contains patches for adding Exynos5433
support to Exynos power domain driver and definitions of all power
domains found in Exynos5433 SoCs.

Patches have been generated on top of linux-next from 25th January 2017.

This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd

To get everything working following patches/patchsets are needed on top
of the linux-next tree:
1. "Add support for the S6E3HA2 panel on TM2 board" v8 patchset:
   http://www.spinics.net/lists/devicetree/msg157859.html
2. "drm/exynos/decon5433: configure sysreg in case of hardware trigger" v2:
   https://patchwork.kernel.org/patch/9493177/
3. "Move pad retention control to Exynos pin controller driver" v3 patchset:
   https://www.spinics.net/lists/arm-kernel/msg556074.html
4. "Pad retentions support for Exynos5433" patchset
   (posted a few minutes ago, no link yet available)
5. "Exynos5433/TM2: add clocks configuration for display subsystem" patchset
   (posted a few minutes ago, no link yet available)
6. "clk: samsung: pll: Add enable/disable support for PLL35XX" patch
   (posted a few minutes ago, no link yet available)
7. "IOMMU probe deferral support" v7 patchset:
   https://www.spinics.net/lists/arm-kernel/msg557110.html
8. "Add runtime PM support for clocks (on Exynos SoC example)" v5 patchset
   (posted a few minutes ago, no link yet available)
9. "Power domains support for Exynos5433 SoCs" patchset
   (this patchset)

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Patch summary:

Chanwoo Choi (1):
  soc: samsung: pm_domains: Add new exynos5433 compatible

Marek Szyprowski (7):
  arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
  arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC
  arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

 .../devicetree/bindings/power/pd-samsung.txt       |   1 +
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         | 118 +++++++++++++++++++++
 drivers/soc/samsung/pm_domains.c                   |   7 ++
 3 files changed, 126 insertions(+)

-- 
1.9.1

[PATCH 1/8] soc: samsung: pm_domains: Add new exynos5433 compatible

[Marek Szyprowski]

From: Chanwoo Choi <cw00.choi@samsung.com>

This patch adds the new compatible string for exynos5433 because the exynos5433
use the '0xf' value to turn on and off instead of '0x7'.

Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 Documentation/devicetree/bindings/power/pd-samsung.txt | 1 +
 drivers/soc/samsung/pm_domains.c                       | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/pd-samsung.txt b/Documentation/devicetree/bindings/power/pd-samsung.txt
index 76df656be618..fb08c8d62733 100644
--- a/Documentation/devicetree/bindings/power/pd-samsung.txt
+++ b/Documentation/devicetree/bindings/power/pd-samsung.txt
@@ -6,6 +6,7 @@ to gate power to one or more peripherals on the processor.
 Required Properties:
 - compatible: should be one of the following.
     * samsung,exynos4210-pd - for exynos4210 type power domain.
+    * samsung,exynos5433-pd - for exynos5433 type power domain.
 - reg: physical base address of the controller and length of memory mapped
     region.
 - #power-domain-cells: number of cells in power domain specifier;
diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c
index 7112004b8032..15bad1543409 100644
--- a/drivers/soc/samsung/pm_domains.c
+++ b/drivers/soc/samsung/pm_domains.c
@@ -128,10 +128,17 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
 	.local_pwr_cfg		= 0x7,
 };
 
+static const struct exynos_pm_domain_config exynos5433_cfg __initconst = {
+	.local_pwr_cfg		= 0xf,
+};
+
 static const struct of_device_id exynos_pm_domain_of_match[] __initconst = {
 	{
 		.compatible = "samsung,exynos4210-pd",
 		.data = &exynos4210_cfg,
+	}, {
+		.compatible = "samsung,exynos5433-pd",
+		.data = &exynos5433_cfg,
 	},
 	{ },
 };
-- 
1.9.1

[PATCH 2/8] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, three GSCL video scalers and
their SYSMMUs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 16072c1c3ed3..74c767d756ac 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -425,6 +425,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_GSCL_111>,
 				<&cmu_top CLK_ACLK_GSCL_333>;
+			power-domains = <&pd_gscl>;
 		};
 
 		cmu_apollo: clock-controller@11900000 {
@@ -525,6 +526,12 @@
 				<&cmu_top CLK_ACLK_CAM1_552>;
 		};
 
+		pd_gscl: gscl-power-domain@105c4000 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4000 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -892,6 +899,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		gsc_1: video-scaler@13C10000 {
@@ -905,6 +913,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl1>;
+			power-domains = <&pd_gscl>;
 		};
 
 		gsc_2: video-scaler@13C20000 {
@@ -918,6 +927,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl2>;
+			power-domains = <&pd_gscl>;
 		};
 
 		jpeg: codec@15020000 {
@@ -992,6 +1002,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_gscl1: sysmmu@13c90000 {
@@ -1002,6 +1013,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_gscl2: sysmmu@13ca0000 {
@@ -1012,6 +1024,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_jpeg: sysmmu@15060000 {
-- 
1.9.1

[PATCH 3/8] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for DISP power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, two display controllers
(DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices.

OCSigned-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 74c767d756ac..a84b44cea2a8 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -368,6 +368,7 @@
 				<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 				<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 				<&cmu_mif CLK_ACLK_DISP_333>;
+			power-domains = <&pd_disp>;
 		};
 
 		cmu_aud: clock-controller@114c0000 {
@@ -532,6 +533,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_disp: disp-power-domain@105c4080 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4080 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -735,6 +742,7 @@
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				"aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				"sclk_decon_vclk", "sclk_decon_eclk";
+			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
@@ -772,6 +780,7 @@
 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				      "sclk_decon_vclk", "sclk_decon_eclk";
 			samsung,disp-sysreg = <&syscon_disp>;
+			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
@@ -797,6 +806,7 @@
 					"phyclk_mipidphy0_rxclkesc0",
 					"sclk_rgb_vclk_to_dsim0",
 					"sclk_mipi";
+			power-domains = <&pd_disp>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -820,6 +830,7 @@
 			clocks = <&cmu_disp CLK_PCLK_MIC0>,
 				<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 			clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
+			power-domains = <&pd_disp>;
 			samsung,disp-syscon = <&syscon_disp>;
 			status = "disabled";
 
@@ -961,6 +972,7 @@
 			clock-names = "pclk", "aclk";
 			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 				<&cmu_disp CLK_ACLK_SMMU_DECON0X>;
+			power-domains = <&pd_disp>;
 			#iommu-cells = <0>;
 		};
 
@@ -972,6 +984,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 				<&cmu_disp CLK_ACLK_SMMU_DECON1X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_tv0x: sysmmu@13a20000 {
@@ -982,6 +995,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
 				<&cmu_disp CLK_ACLK_SMMU_TV0X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_tv1x: sysmmu@13a30000 {
@@ -992,6 +1006,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
 				<&cmu_disp CLK_ACLK_SMMU_TV1X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_gscl0: sysmmu@13c80000 {
-- 
1.9.1

[PATCH 4/8] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, JPEG codec device and its
SYSMMU.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index a84b44cea2a8..5778fdbd5763 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -458,6 +458,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_SCLK_JPEG_MSCL>,
 				<&cmu_top CLK_ACLK_MSCL_400>;
+			power-domains = <&pd_mscl>;
 		};
 
 		cmu_mfc: clock-controller@15280000 {
@@ -533,6 +534,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_mscl: mscl-power-domain@105c4040 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4040 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		pd_disp: disp-power-domain@105c4080 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4080 0x20>;
@@ -951,6 +958,7 @@
 				 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
 				 <&cmu_mscl CLK_SCLK_JPEG>;
 			iommus = <&sysmmu_jpeg>;
+			power-domains = <&pd_mscl>;
 		};
 
 		mfc: codec@152E0000 {
@@ -1050,6 +1058,7 @@
 			clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
 				 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mscl>;
 		};
 
 		sysmmu_mfc_0: sysmmu@15200000 {
-- 
1.9.1

[PATCH 5/8] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for MFC power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, MFC codec device and its
SYSMMUs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 5778fdbd5763..3487981726d9 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -468,6 +468,7 @@
 
 			clock-names = "oscclk", "aclk_mfc_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+			power-domains = <&pd_mfc>;
 		};
 
 		cmu_hevc: clock-controller@14f80000 {
@@ -546,6 +547,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_mfc: mfc-power-domain@105c4180 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4180 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -971,6 +978,7 @@
 				 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
 			iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
 			iommu-names = "left", "right";
+			power-domains = <&pd_mfc>;
 		};
 
 		sysmmu_decon0x: sysmmu@13a00000 {
@@ -1069,6 +1077,7 @@
 			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
 				 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mfc>;
 		};
 
 		sysmmu_mfc_1: sysmmu@15210000 {
@@ -1079,6 +1088,7 @@
 			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
 				 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mfc>;
 		};
 
 		serial_0: serial@14c10000 {
-- 
1.9.1

[PATCH 6/8] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC

[Marek Szyprowski]

This patch adds support for AUD power domain to Exynos5433 SoCs, which
contains following devices: a clock controller, a pin controller, LPASS
module, I2S controller, ADMA PL330 engine and UART #3 device.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 3487981726d9..24fc3b46cc40 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -377,6 +377,7 @@
 			#clock-cells = <1>;
 			clock-names = "oscclk", "fout_aud_pll";
 			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
+			power-domains = <&pd_aud>;
 		};
 
 		cmu_bus0: clock-controller@13600000 {
@@ -553,6 +554,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_aud: aud-power-domain@105c40c0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40c0 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -665,6 +672,7 @@
 			compatible = "samsung,exynos5433-pinctrl";
 			reg = <0x114b0000 0x1000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_aud>;
 		};
 
 		pinctrl_cpif: pinctrl@10fe0000 {
@@ -1544,6 +1552,7 @@
 			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
 			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
+			power-domains = <&pd_aud>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1557,6 +1566,7 @@
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				power-domains = <&pd_aud>;
 			};
 
 			i2s0: i2s0@11440000 {
@@ -1573,6 +1583,7 @@
 				clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2s0_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 
@@ -1585,6 +1596,7 @@
 				clock-names = "uart", "clk_uart_baud0";
 				pinctrl-names = "default";
 				pinctrl-0 = <&uart_aud_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 		};
-- 
1.9.1

[PATCH 7/8] arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC

[Marek Szyprowski]

This patch adds support for FSYS power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, a pin controller, three MSHC
controllers, two DWC USB 3.0 controllers and their PHYs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 24fc3b46cc40..0e18e9aeb4ce 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -330,6 +330,7 @@
 				<&cmu_top CLK_SCLK_MMC0_FSYS>,
 				<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 				<&cmu_top CLK_SCLK_USBDRD30_FSYS>;
+			power-domains = <&pd_fsys>;
 		};
 
 		cmu_g2d: clock-controller@12460000 {
@@ -560,6 +561,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_fsys: fsys-power-domain@105c40e0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40e0 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -697,6 +704,7 @@
 			compatible = "samsung,exynos5433-pinctrl";
 			reg = <0x15690000 0x1000>;
 			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_fsys>;
 		};
 
 		pinctrl_imem: pinctrl@11090000 {
@@ -1417,6 +1425,7 @@
 			clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
 				<&cmu_fsys CLK_SCLK_USBDRD30>;
 			clock-names = "usbdrd30", "usbdrd30_susp_clk";
+			power-domains = <&pd_fsys>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1442,6 +1451,7 @@
 					"itp";
 			#phy-cells = <1>;
 			samsung,pmu-syscon = <&pmu_system_controller>;
+			power-domains = <&pd_fsys>;
 			status = "disabled";
 		};
 
@@ -1456,6 +1466,7 @@
 					"itp";
 			#phy-cells = <1>;
 			samsung,pmu-syscon = <&pmu_system_controller>;
+			power-domains = <&pd_fsys>;
 			status = "disabled";
 		};
 
@@ -1464,6 +1475,7 @@
 			clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
 				<&cmu_fsys CLK_SCLK_USBHOST30>;
 			clock-names = "usbdrd30", "usbdrd30_susp_clk";
+			power-domains = <&pd_fsys>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1488,6 +1500,7 @@
 				<&cmu_fsys CLK_SCLK_MMC0>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&pd_fsys>;
 			status = "disabled";
 		};
 
@@ -1501,6 +1514,7 @@
 				<&cmu_fsys CLK_SCLK_MMC1>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&pd_fsys>;
 			status = "disabled";
 		};
 
@@ -1514,6 +1528,7 @@
 				<&cmu_fsys CLK_SCLK_MMC2>;
 			clock-names = "biu", "ciu";
 			fifo-depth = <0x40>;
+			power-domains = <&pd_fsys>;
 			status = "disabled";
 		};
 
-- 
1.9.1

[PATCH 8/8] arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

[Marek Szyprowski]

This patch adds support for G2D, G3D, CAM0, CAM1, ISP, HVEC power domains
to Exynos5433 SoCs. Currently only clock controllers for those domains are
defined. CAM1 is a parent of CAM0 power domain and CAM0 is a parent of ISP
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 44 ++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0e18e9aeb4ce..e45f6e4683b3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -344,6 +344,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_G2D_266>,
 				<&cmu_top CLK_ACLK_G2D_400>;
+			power-domains = <&pd_g2d>;
 		};
 
 		cmu_disp: clock-controller@13b90000 {
@@ -415,6 +416,7 @@
 
 			clock-names = "oscclk", "aclk_g3d_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
+			power-domains = <&pd_g3d>;
 		};
 
 		cmu_gscl: clock-controller@13cf0000 {
@@ -480,6 +482,7 @@
 
 			clock-names = "oscclk", "aclk_hevc_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
+			power-domains = <&pd_hevc>;
 		};
 
 		cmu_isp: clock-controller@146d0000 {
@@ -493,6 +496,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_ISP_DIS_400>,
 				<&cmu_top CLK_ACLK_ISP_400>;
+			power-domains = <&pd_isp>;
 		};
 
 		cmu_cam0: clock-controller@120d0000 {
@@ -508,6 +512,7 @@
 				<&cmu_top CLK_ACLK_CAM0_333>,
 				<&cmu_top CLK_ACLK_CAM0_400>,
 				<&cmu_top CLK_ACLK_CAM0_552>;
+			power-domains = <&pd_cam0>;
 		};
 
 		cmu_cam1: clock-controller@145d0000 {
@@ -529,6 +534,7 @@
 				<&cmu_top CLK_ACLK_CAM1_333>,
 				<&cmu_top CLK_ACLK_CAM1_400>,
 				<&cmu_top CLK_ACLK_CAM1_552>;
+			power-domains = <&pd_cam1>;
 		};
 
 		pd_gscl: gscl-power-domain@105c4000 {
@@ -555,6 +561,38 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_cam0: cam0-power-domain@105c4020 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4020 0x20>;
+			#power-domain-cells = <0>;
+			power-domains = <&pd_cam1>;
+		};
+
+		pd_cam1: cam1-power-domain@105c40a0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40a0 0x20>;
+			#power-domain-cells = <0>;
+		};
+
+		pd_isp: isp-power-domain@105c4140 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4140 0x20>;
+			#power-domain-cells = <0>;
+			power-domains = <&pd_cam0>;
+		};
+
+		pd_g2d: g2d-power-domain@105c4120 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4120 0x20>;
+			#power-domain-cells = <0>;
+		};
+
+		pd_g3d: g3d-power-domain@105c4060 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4060 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		pd_aud: aud-power-domain@105c40c0 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c40c0 0x20>;
@@ -567,6 +605,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_hevc: hevc-power-domain@105c41c0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c41c0 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
-- 
1.9.1

Re: [PATCH 1/8] soc: samsung: pm_domains: Add new exynos5433 compatible

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:55:35PM +0100, Marek Szyprowski wrote:
> From: Chanwoo Choi <cw00.choi@samsung.com>
> 
> This patch adds the new compatible string for exynos5433 because the exynos5433
> use the '0xf' value to turn on and off instead of '0x7'.
> 
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  Documentation/devicetree/bindings/power/pd-samsung.txt | 1 +
>  drivers/soc/samsung/pm_domains.c                       | 7 +++++++
>  2 files changed, 8 insertions(+)
>

Applied with commit msg changes.

Best regards,
Krzysztof

Re: [PATCH 0/8] Power domains support for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:55:34PM +0100, Marek Szyprowski wrote:
> Hello,
> 
> This patchset is a final step to add support for all power domains
> on Exynos5433 SoCs. This patchset contains patches for adding Exynos5433
> support to Exynos power domain driver and definitions of all power
> domains found in Exynos5433 SoCs.
> 
> Patches have been generated on top of linux-next from 25th January 2017.
> 
> This is a part of a larger task, which goal is to add support for power
> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
> working have been pushed to the following git repo:
> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
> 
> To get everything working following patches/patchsets are needed on top
> of the linux-next tree:

By "get everything working" you also mean that there is a runtime
dependency? In other words, can I apply DTS patches here?

Best regards,
Krzysztof


> 1. "Add support for the S6E3HA2 panel on TM2 board" v8 patchset:
>    http://www.spinics.net/lists/devicetree/msg157859.html
> 2. "drm/exynos/decon5433: configure sysreg in case of hardware trigger" v2:
>    https://patchwork.kernel.org/patch/9493177/
> 3. "Move pad retention control to Exynos pin controller driver" v3 patchset:
>    https://www.spinics.net/lists/arm-kernel/msg556074.html
> 4. "Pad retentions support for Exynos5433" patchset
>    (posted a few minutes ago, no link yet available)
> 5. "Exynos5433/TM2: add clocks configuration for display subsystem" patchset
>    (posted a few minutes ago, no link yet available)
> 6. "clk: samsung: pll: Add enable/disable support for PLL35XX" patch
>    (posted a few minutes ago, no link yet available)
> 7. "IOMMU probe deferral support" v7 patchset:
>    https://www.spinics.net/lists/arm-kernel/msg557110.html
> 8. "Add runtime PM support for clocks (on Exynos SoC example)" v5 patchset
>    (posted a few minutes ago, no link yet available)
> 9. "Power domains support for Exynos5433 SoCs" patchset
>    (this patchset)
> 
> Best regards
> Marek Szyprowski
> Samsung R&D Institute Poland
> 
> 
> Patch summary:
> 
> Chanwoo Choi (1):
>   soc: samsung: pm_domains: Add new exynos5433 compatible
> 
> Marek Szyprowski (7):
>   arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
>   arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
>   arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
>   arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
>   arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
>   arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC
>   arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC
> 
>  .../devicetree/bindings/power/pd-samsung.txt       |   1 +
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi         | 118 +++++++++++++++++++++
>  drivers/soc/samsung/pm_domains.c                   |   7 ++
>  3 files changed, 126 insertions(+)
> 
> -- 
> 1.9.1
> 

Re: [PATCH 2/8] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:55:36PM +0100, Marek Szyprowski wrote:
> This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, three GSCL video scalers and
> their SYSMMUs.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 16072c1c3ed3..74c767d756ac 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -425,6 +425,7 @@
>  			clocks = <&xxti>,
>  				<&cmu_top CLK_ACLK_GSCL_111>,
>  				<&cmu_top CLK_ACLK_GSCL_333>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		cmu_apollo: clock-controller@11900000 {
> @@ -525,6 +526,12 @@
>  				<&cmu_top CLK_ACLK_CAM1_552>;
>  		};
>  
> +		pd_gscl: gscl-power-domain@105c4000 {

The name of node: just "power-domain". This should be generic class of
device (following ePAPR).

The same applies to other patches.

Best regards,
Krzysztof

Re: [PATCH 0/8] Power domains support for Exynos5433 SoCs

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 08:43, Krzysztof Kozlowski wrote:
> On Wed, Jan 25, 2017 at 12:55:34PM +0100, Marek Szyprowski wrote:
>> Hello,
>>
>> This patchset is a final step to add support for all power domains
>> on Exynos5433 SoCs. This patchset contains patches for adding Exynos5433
>> support to Exynos power domain driver and definitions of all power
>> domains found in Exynos5433 SoCs.
>>
>> Patches have been generated on top of linux-next from 25th January 2017.
>>
>> This is a part of a larger task, which goal is to add support for power
>> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
>> working have been pushed to the following git repo:
>> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>>
>> To get everything working following patches/patchsets are needed on top
>> of the linux-next tree:
> By "get everything working" you also mean that there is a runtime
> dependency? In other words, can I apply DTS patches here?

IMHO we should wait with applying pm domains DTS patches. Without ALL 
other patches
kernel will sooner or later panic with "(a)synchronous external abort" 
or deadlock
in a different way.

>
> Best regards,
> Krzysztof
>
>
>> 1. "Add support for the S6E3HA2 panel on TM2 board" v8 patchset:
>>     http://www.spinics.net/lists/devicetree/msg157859.html
>> 2. "drm/exynos/decon5433: configure sysreg in case of hardware trigger" v2:
>>     https://patchwork.kernel.org/patch/9493177/
>> 3. "Move pad retention control to Exynos pin controller driver" v3 patchset:
>>     https://www.spinics.net/lists/arm-kernel/msg556074.html
>> 4. "Pad retentions support for Exynos5433" patchset
>>     (posted a few minutes ago, no link yet available)
>> 5. "Exynos5433/TM2: add clocks configuration for display subsystem" patchset
>>     (posted a few minutes ago, no link yet available)
>> 6. "clk: samsung: pll: Add enable/disable support for PLL35XX" patch
>>     (posted a few minutes ago, no link yet available)
>> 7. "IOMMU probe deferral support" v7 patchset:
>>     https://www.spinics.net/lists/arm-kernel/msg557110.html
>> 8. "Add runtime PM support for clocks (on Exynos SoC example)" v5 patchset
>>     (posted a few minutes ago, no link yet available)
>> 9. "Power domains support for Exynos5433 SoCs" patchset
>>     (this patchset)
>>
>> Best regards
>> Marek Szyprowski
>> Samsung R&D Institute Poland
>>
>>
>> Patch summary:
>>
>> Chanwoo Choi (1):
>>    soc: samsung: pm_domains: Add new exynos5433 compatible
>>
>> Marek Szyprowski (7):
>>    arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
>>    arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
>>    arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
>>    arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
>>    arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
>>    arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC
>>    arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC
>>
>>   .../devicetree/bindings/power/pd-samsung.txt       |   1 +
>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi         | 118 +++++++++++++++++++++
>>   drivers/soc/samsung/pm_domains.c                   |   7 ++
>>   3 files changed, 126 insertions(+)
>>
>> -- 
>> 1.9.1
>>
>

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH 0/8] Power domains support for Exynos5433 SoCs

[Krzysztof Kozlowski]

On Fri, Jan 27, 2017 at 08:47:44AM +0100, Marek Szyprowski wrote:
> Hi Krzysztof,
> 
> On 2017-01-27 08:43, Krzysztof Kozlowski wrote:
> > On Wed, Jan 25, 2017 at 12:55:34PM +0100, Marek Szyprowski wrote:
> > > Hello,
> > > 
> > > This patchset is a final step to add support for all power domains
> > > on Exynos5433 SoCs. This patchset contains patches for adding Exynos5433
> > > support to Exynos power domain driver and definitions of all power
> > > domains found in Exynos5433 SoCs.
> > > 
> > > Patches have been generated on top of linux-next from 25th January 2017.
> > > 
> > > This is a part of a larger task, which goal is to add support for power
> > > domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
> > > working have been pushed to the following git repo:
> > > https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
> > > 
> > > To get everything working following patches/patchsets are needed on top
> > > of the linux-next tree:
> > By "get everything working" you also mean that there is a runtime
> > dependency? In other words, can I apply DTS patches here?
> 
> IMHO we should wait with applying pm domains DTS patches. Without ALL other
> patches
> kernel will sooner or later panic with "(a)synchronous external abort" or
> deadlock
> in a different way.

Okay, makes sense. A partial solution would be to apply them with
status=disabled. After all it is still a valid description of a
hardware. However this would not bring much benefits anyway...

Beside the name of node I mentioned, please put all the power domains
sorted to each other by address. I see the big picture here:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git/tree/arch/arm64/boot/dts/exynos/exynos5433.dtsi?h=v4.10-next-tm2-pd
and it does not looks ordered.

Best regards,
Krzysztof

Re: [PATCH 0/8] Power domains support for Exynos5433 SoCs

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 08:52, Krzysztof Kozlowski wrote:
> On Fri, Jan 27, 2017 at 08:47:44AM +0100, Marek Szyprowski wrote:
>> On 2017-01-27 08:43, Krzysztof Kozlowski wrote:
>>> On Wed, Jan 25, 2017 at 12:55:34PM +0100, Marek Szyprowski wrote:
>>>> This patchset is a final step to add support for all power domains
>>>> on Exynos5433 SoCs. This patchset contains patches for adding Exynos5433
>>>> support to Exynos power domain driver and definitions of all power
>>>> domains found in Exynos5433 SoCs.
>>>>
>>>> Patches have been generated on top of linux-next from 25th January 2017.
>>>>
>>>> This is a part of a larger task, which goal is to add support for power
>>>> domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
>>>> working have been pushed to the following git repo:
>>>> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd
>>>>
>>>> To get everything working following patches/patchsets are needed on top
>>>> of the linux-next tree:
>>> By "get everything working" you also mean that there is a runtime
>>> dependency? In other words, can I apply DTS patches here?
>> IMHO we should wait with applying pm domains DTS patches. Without ALL other
>> patches
>> kernel will sooner or later panic with "(a)synchronous external abort" or
>> deadlock
>> in a different way.
> Okay, makes sense. A partial solution would be to apply them with
> status=disabled. After all it is still a valid description of a
> hardware. However this would not bring much benefits anyway...

First we would need to learn the Exynos power domain driver to honor
"status=disabled" property, because right now it instantiate all domains
regardless the provided status ;) Feel free to prepare a patch for that.

I'm also not sure if driver core will handle such case properly. I remember
that it deferred probing of all devices when no power domain driver was
available, but this might be a bit different case than skipping domain
registration.

> Beside the name of node I mentioned, please put all the power domains
> sorted to each other by address. I see the big picture here:
> https://git.linaro.org/people/marek.szyprowski/linux-srpol.git/tree/arch/arm64/boot/dts/exynos/exynos5433.dtsi?h=v4.10-next-tm2-pd
> and it does not looks ordered.

I think I've already tried to keep them sorted by address, but maybe while
rebasing/updating/fixing something went wrong.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH 2/8] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

Hi Krzysztof,

On 2017-01-27 08:46, Krzysztof Kozlowski wrote:
> On Wed, Jan 25, 2017 at 12:55:36PM +0100, Marek Szyprowski wrote:
>> This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
>> contains following devices: a clock controller, three GSCL video scalers and
>> their SYSMMUs.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 16072c1c3ed3..74c767d756ac 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -425,6 +425,7 @@
>>   			clocks = <&xxti>,
>>   				<&cmu_top CLK_ACLK_GSCL_111>,
>>   				<&cmu_top CLK_ACLK_GSCL_333>;
>> +			power-domains = <&pd_gscl>;
>>   		};
>>   
>>   		cmu_apollo: clock-controller@11900000 {
>> @@ -525,6 +526,12 @@
>>   				<&cmu_top CLK_ACLK_CAM1_552>;
>>   		};
>>   
>> +		pd_gscl: gscl-power-domain@105c4000 {
> The name of node: just "power-domain". This should be generic class of
> device (following ePAPR).
>
> The same applies to other patches.

Well, this makes the debugging much harder, but I will change it to generic
names. Also existing Exynos dtsi should be fixed in this area (Exynos4 still
use such more descriptive names). I will check how hard is to add real
domain names directly to the Exynos power domain driver then.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH 2/8] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Fri, Jan 27, 2017 at 11:33:36AM +0100, Marek Szyprowski wrote:
> Hi Krzysztof,
> 
> On 2017-01-27 08:46, Krzysztof Kozlowski wrote:
> > On Wed, Jan 25, 2017 at 12:55:36PM +0100, Marek Szyprowski wrote:
> > > This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
> > > contains following devices: a clock controller, three GSCL video scalers and
> > > their SYSMMUs.
> > > 
> > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > > ---
> > >   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
> > >   1 file changed, 13 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > > index 16072c1c3ed3..74c767d756ac 100644
> > > --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > > +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> > > @@ -425,6 +425,7 @@
> > >   			clocks = <&xxti>,
> > >   				<&cmu_top CLK_ACLK_GSCL_111>,
> > >   				<&cmu_top CLK_ACLK_GSCL_333>;
> > > +			power-domains = <&pd_gscl>;
> > >   		};
> > >   		cmu_apollo: clock-controller@11900000 {
> > > @@ -525,6 +526,12 @@
> > >   				<&cmu_top CLK_ACLK_CAM1_552>;
> > >   		};
> > > +		pd_gscl: gscl-power-domain@105c4000 {
> > The name of node: just "power-domain". This should be generic class of
> > device (following ePAPR).
> > 
> > The same applies to other patches.
> 
> Well, this makes the debugging much harder, but I will change it to generic
> names.

Good point. I remember some patch from Javier trying to address this but
I cannot find it anymore.

Anyway, I don't think power-domains should be treated here differently
then rest of devices (which have generic names: clock-controller,
pinctrl, i2s, i2c etc).

> Also existing Exynos dtsi should be fixed in this area (Exynos4 still
> use such more descriptive names).

I am trying to bring some shape to new code but of course you are right
- old code should be adjusted as well (maybe as part of some bigger
  cleanup). Exynos5420 uses short/generic names.

> I will check how hard is to add real
> domain names directly to the Exynos power domain driver then.

Thanks!

Krzysztof