Linux-RISC-V Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Clément Léger" <cleger@rivosinc.com>
To: Andrew Jones <ajones@ventanamicro.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	charlie@rivosinc.com, jesse@rivosinc.com,
	Anup Patel <apatel@ventanamicro.com>
Subject: Re: [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback
Date: Fri, 7 Feb 2025 18:36:28 +0100	[thread overview]
Message-ID: <00cbde9c-39b4-4445-98af-70dfd1fbd62a@rivosinc.com> (raw)
In-Reply-To: <20250207161939.46139-17-ajones@ventanamicro.com>



On 07/02/2025 17:19, Andrew Jones wrote:
> Whether or not we have RISCV_PROBE_VECTOR_UNALIGNED_ACCESS we need to
> set up a cpu hotplug callback to check if we have vector at all,
> since, when we don't have vector, we need to set
> vector_misaligned_access to unsupported rather than leave it the
> default of unknown.
> 
> Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/kernel/unaligned_access_speed.c | 31 +++++++++++-----------
>  1 file changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> index c9d3237649bb..d9d4ca1fadc7 100644
> --- a/arch/riscv/kernel/unaligned_access_speed.c
> +++ b/arch/riscv/kernel/unaligned_access_speed.c
> @@ -356,6 +356,20 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus
>  	per_cpu(vector_misaligned_access, cpu) = speed;
>  }
>  
> +/* Measure unaligned access speed on all CPUs present at boot in parallel. */
> +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused)
> +{
> +	schedule_on_each_cpu(check_vector_unaligned_access);
Hey Andrew,

While at it, could you add a comment stating that schedule_on_cpu()
(while documented as really slow) is used due to kernel_vector_begin()
needing interrupts to be enabled ? I stumbled upon that while reworking
misaligned.

Thanks,

Clément

> +
> +	return 0;
> +}
> +#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */
> +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused)
> +{
> +	return 0;
> +}
> +#endif
> +
>  static int riscv_online_cpu_vec(unsigned int cpu)
>  {
>  	if (!has_vector()) {
> @@ -363,27 +377,16 @@ static int riscv_online_cpu_vec(unsigned int cpu)
>  		return 0;
>  	}
>  
> +#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS
>  	if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN)
>  		return 0;
>  
>  	check_vector_unaligned_access_emulated(NULL);
>  	check_vector_unaligned_access(NULL);
> -	return 0;
> -}
> -
> -/* Measure unaligned access speed on all CPUs present at boot in parallel. */
> -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused)
> -{
> -	schedule_on_each_cpu(check_vector_unaligned_access);
> +#endif
>  
>  	return 0;
>  }
> -#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */
> -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __always_unused)
> -{
> -	return 0;
> -}
> -#endif
>  
>  static int __init check_unaligned_access_all_cpus(void)
>  {
> @@ -409,10 +412,8 @@ static int __init check_unaligned_access_all_cpus(void)
>  	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online",
>  				  riscv_online_cpu, riscv_offline_cpu);
>  #endif
> -#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS
>  	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online",
>  				  riscv_online_cpu_vec, NULL);
> -#endif
>  
>  	return 0;
>  }


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2025-02-07 17:45 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-07 16:19 [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Andrew Jones
2025-02-07 16:19 ` [PATCH 1/9] riscv: Annotate unaligned access init functions Andrew Jones
2025-02-13 12:59   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Andrew Jones
2025-02-07 16:47   ` Clément Léger
2025-02-07 17:08     ` Andrew Jones
2025-02-07 17:43       ` Clément Léger
2025-02-07 18:08         ` Andrew Jones
2025-02-13 13:02   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 3/9] riscv: Fix check_unaligned_access_all_cpus Andrew Jones
2025-02-13 13:12   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 4/9] riscv: Change check_unaligned_access_speed_all_cpus to void Andrew Jones
2025-02-07 16:42   ` Clément Léger
2025-02-13 13:15   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 5/9] riscv: Fix set up of cpu hotplug callbacks Andrew Jones
2025-02-07 16:44   ` Clément Léger
2025-02-13 13:25   ` Alexandre Ghiti
2025-02-13 13:33   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback Andrew Jones
2025-02-07 17:36   ` Clément Léger [this message]
2025-02-07 18:15     ` Andrew Jones
2025-02-13 13:28   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Andrew Jones
2025-02-08  1:22   ` Charlie Jenkins
2025-02-10  9:43     ` Andrew Jones
2025-02-10 17:10       ` Charlie Jenkins
2025-02-10 10:16     ` Anup Patel
2025-02-10 11:07       ` Clément Léger
2025-02-10 14:06         ` Andrew Jones
2025-02-10 14:20           ` Clément Léger
2025-02-10 17:20             ` Charlie Jenkins
2025-02-10 20:42               ` Clément Léger
2025-02-10 20:53                 ` Charlie Jenkins
2025-02-10 20:57                   ` Clément Léger
2025-02-10 21:13                     ` Charlie Jenkins
2025-02-11  4:26                     ` Anup Patel
2025-02-11  8:37                       ` Clément Léger
2025-02-11 18:09                       ` Palmer Dabbelt
2025-02-10 17:19       ` Charlie Jenkins
2025-02-10 20:37         ` Clément Léger
2025-02-11  9:04           ` Andrew Jones
2025-02-07 16:19 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 16:19 ` [PATCH 9/9] riscv: Add Ventana unaligned access table entries Andrew Jones
2025-02-07 18:10 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 18:19   ` Andrew Jones
2025-02-08  7:59 ` [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Anup Patel
2025-02-10  9:26   ` Andrew Jones
2025-02-10  9:58     ` Anup Patel
2025-02-10 11:01       ` Andrew Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=00cbde9c-39b4-4445-98af-70dfd1fbd62a@rivosinc.com \
    --to=cleger@rivosinc.com \
    --cc=ajones@ventanamicro.com \
    --cc=apatel@ventanamicro.com \
    --cc=charlie@rivosinc.com \
    --cc=jesse@rivosinc.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox