From: "Clément Léger" <cleger@rivosinc.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
charlie@rivosinc.com, jesse@rivosinc.com,
Anup Patel <apatel@ventanamicro.com>
Subject: Re: [PATCH 2/9] riscv: Fix riscv_online_cpu_vec
Date: Fri, 7 Feb 2025 18:43:26 +0100 [thread overview]
Message-ID: <fdabae33-a1df-41f7-9e1f-9973f252599a@rivosinc.com> (raw)
In-Reply-To: <20250207-f0e7e2b868ef3e9f2a174f29@orel>
On 07/02/2025 18:08, Andrew Jones wrote:
> On Fri, Feb 07, 2025 at 05:47:28PM +0100, Clément Léger wrote:
>>
>>
>> On 07/02/2025 17:19, Andrew Jones wrote:
>>> We shouldn't probe when we already know vector is unsupported and
>>> we should probe when we see we don't yet know whether it's supported.
>>> Furthermore, we should ensure we've set the access type to
>>> unsupported when we don't have vector at all.
>>>
>>> Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe")
>>> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
>>> ---
>>> arch/riscv/kernel/unaligned_access_speed.c | 6 ++++--
>>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
>>> index b7a8ff7ba6df..161964cf2abc 100644
>>> --- a/arch/riscv/kernel/unaligned_access_speed.c
>>> +++ b/arch/riscv/kernel/unaligned_access_speed.c
>>> @@ -367,10 +367,12 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus
>>>
>>> static int riscv_online_cpu_vec(unsigned int cpu)
>>> {
>>> - if (!has_vector())
>>> + if (!has_vector()) {
>>> + per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED;
>>> return 0;
>>> + }
>>>
>>> - if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED)
>>> + if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN)
>>> return 0;
>>>
>>> check_vector_unaligned_access_emulated(NULL);
>>
>> Hi Andrew,
>>
>> Wouldn't it be easier just not to register the hotplug callback in case
>> !has_vector() ? In which case just set all possible cpus
>> vector_misaligned_access to RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED
>> at startup.
>
> We could do that, but I have another use for the hotplug callback that
> you'll see near the end of the series.
Ok, I saw patch 7/9.
BTW, what happened to patch 8 ? I thought it was in my spam but even
lore.kernel.org does not have it:
https://lore.kernel.org/linux-riscv/20250207161939.46139-11-ajones@ventanamicro.com/T/#t
Thanks,
Clément
>
> Thanks,
> drew
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next prev parent reply other threads:[~2025-02-07 17:54 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-07 16:19 [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Andrew Jones
2025-02-07 16:19 ` [PATCH 1/9] riscv: Annotate unaligned access init functions Andrew Jones
2025-02-13 12:59 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Andrew Jones
2025-02-07 16:47 ` Clément Léger
2025-02-07 17:08 ` Andrew Jones
2025-02-07 17:43 ` Clément Léger [this message]
2025-02-07 18:08 ` Andrew Jones
2025-02-13 13:02 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 3/9] riscv: Fix check_unaligned_access_all_cpus Andrew Jones
2025-02-13 13:12 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 4/9] riscv: Change check_unaligned_access_speed_all_cpus to void Andrew Jones
2025-02-07 16:42 ` Clément Léger
2025-02-13 13:15 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 5/9] riscv: Fix set up of cpu hotplug callbacks Andrew Jones
2025-02-07 16:44 ` Clément Léger
2025-02-13 13:25 ` Alexandre Ghiti
2025-02-13 13:33 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback Andrew Jones
2025-02-07 17:36 ` Clément Léger
2025-02-07 18:15 ` Andrew Jones
2025-02-13 13:28 ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Andrew Jones
2025-02-08 1:22 ` Charlie Jenkins
2025-02-10 9:43 ` Andrew Jones
2025-02-10 17:10 ` Charlie Jenkins
2025-02-10 10:16 ` Anup Patel
2025-02-10 11:07 ` Clément Léger
2025-02-10 14:06 ` Andrew Jones
2025-02-10 14:20 ` Clément Léger
2025-02-10 17:20 ` Charlie Jenkins
2025-02-10 20:42 ` Clément Léger
2025-02-10 20:53 ` Charlie Jenkins
2025-02-10 20:57 ` Clément Léger
2025-02-10 21:13 ` Charlie Jenkins
2025-02-11 4:26 ` Anup Patel
2025-02-11 8:37 ` Clément Léger
2025-02-11 18:09 ` Palmer Dabbelt
2025-02-10 17:19 ` Charlie Jenkins
2025-02-10 20:37 ` Clément Léger
2025-02-11 9:04 ` Andrew Jones
2025-02-07 16:19 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 16:19 ` [PATCH 9/9] riscv: Add Ventana unaligned access table entries Andrew Jones
2025-02-07 18:10 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 18:19 ` Andrew Jones
2025-02-08 7:59 ` [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Anup Patel
2025-02-10 9:26 ` Andrew Jones
2025-02-10 9:58 ` Anup Patel
2025-02-10 11:01 ` Andrew Jones
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