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From: Andrew Jones <ajones@ventanamicro.com>
To: linux-riscv@lists.infradead.org
Cc: cleger@rivosinc.com
Subject: Re: [PATCH 8/9] riscv: Implement check_unaligned_access_table
Date: Fri, 7 Feb 2025 19:19:35 +0100	[thread overview]
Message-ID: <20250207-ed32c2f6c418ba86ca82d455@orel> (raw)
In-Reply-To: <20250207181048.6045-2-ajones@ventanamicro.com>


This is the same as the other 8/9 (for those of you that received it). For
whatever reason, the linux-riscv mailing list dropped the original 8/9,
though, so I've sent it again.

Thanks,
drew

On Fri, Feb 07, 2025 at 07:10:49PM +0100, Andrew Jones wrote:
> Define the table entry type and implement the table lookup to find
> unaligned access types by id registers which is used to skip probing.
> 
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  arch/riscv/kernel/unaligned_access_speed.c | 91 +++++++++++++++++++++-
>  1 file changed, 89 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c
> index f8497097e79d..bd6db4c42daf 100644
> --- a/arch/riscv/kernel/unaligned_access_speed.c
> +++ b/arch/riscv/kernel/unaligned_access_speed.c
> @@ -12,6 +12,7 @@
>  #include <linux/types.h>
>  #include <asm/cpufeature.h>
>  #include <asm/hwprobe.h>
> +#include <asm/sbi.h>
>  #include <asm/vector.h>
>  
>  #include "copy-unaligned.h"
> @@ -230,11 +231,89 @@ static int __init lock_and_set_unaligned_access_static_branch(void)
>  
>  arch_initcall_sync(lock_and_set_unaligned_access_static_branch);
>  
> -static bool check_unaligned_access_table(void)
> +/*
> + * An unaligned_access_table_entry maps harts (or collections of harts) to
> + * unaligned access types. @level is used to determine whether @marchid and/or
> + * @mimpid should to be considered. All (level, mvendorid, marchid, mimpid)
> + * tuples formed from each table entry must be unique.
> + */
> +enum id_level {
> +	LEVEL_VENDOR,
> +	LEVEL_ARCH,
> +	LEVEL_IMP,
> +};
> +struct unaligned_access_table_entry {
> +	enum id_level level;
> +	u32 mvendorid;
> +	ulong marchid;
> +	ulong mimpid;
> +	long type;
> +};
> +
> +static struct unaligned_access_table_entry unaligned_access_table_entries[] = {
> +};
> +
> +/*
> + * Search unaligned_access_table_entries[] for the most specific match,
> + * i.e. if there are two entries, one with mvendorid = V and level = VENDOR
> + * and another with mvendorid = V, level = ARCH, and marchid = A, then
> + * a hart with {V,A,?} will match the latter while a hart with {V,!A,?}
> + * will match the former.
> + */
> +static bool __check_unaligned_access_table(int cpu, long *ptr, int nr_entries,
> +					   struct unaligned_access_table_entry table[])
>  {
> +	struct unaligned_access_table_entry *entry, *match = NULL;
> +	u32 mvendorid = riscv_cached_mvendorid(cpu);
> +	ulong marchid = riscv_cached_marchid(cpu);
> +	ulong mimpid = riscv_cached_mimpid(cpu);
> +	int i;
> +
> +	for (i = 0; i < nr_entries; ++i) {
> +		entry = &table[i];
> +
> +		switch (entry->level) {
> +		case LEVEL_VENDOR:
> +			if (!match && entry->mvendorid == mvendorid) {
> +				/* The match, unless we find an ARCH or IMP level match. */
> +				match = entry;
> +			}
> +			break;
> +		case LEVEL_ARCH:
> +			if (entry->mvendorid == mvendorid && entry->marchid == marchid) {
> +				/* The match, unless we find an IMP level match. */
> +				match = entry;
> +			}
> +			break;
> +		case LEVEL_IMP:
> +			if (entry->mvendorid == mvendorid && entry->marchid == marchid &&
> +			    entry->mimpid == mimpid) {
> +				match = entry;
> +				goto matched;
> +			}
> +			break;
> +		}
> +	}
> +
> +	if (match) {
> +matched:
> +		*ptr = match->type;
> +		return true;
> +	}
> +
>  	return false;
>  }
>  
> +static bool check_unaligned_access_table(void)
> +{
> +	int cpu = smp_processor_id();
> +	long *ptr = per_cpu_ptr(&misaligned_access_speed, cpu);
> +
> +	return __check_unaligned_access_table(cpu, ptr,
> +					      ARRAY_SIZE(unaligned_access_table_entries),
> +					      unaligned_access_table_entries);
> +}
> +
>  static int riscv_online_cpu(unsigned int cpu)
>  {
>  	if (check_unaligned_access_table())
> @@ -380,9 +459,17 @@ static int __init vec_check_unaligned_access_speed_all_cpus(void *unused __alway
>  }
>  #endif
>  
> +static struct unaligned_access_table_entry vec_unaligned_access_table_entries[] = {
> +};
> +
>  static bool check_vector_unaligned_access_table(void)
>  {
> -	return false;
> +	int cpu = smp_processor_id();
> +	long *ptr = per_cpu_ptr(&vector_misaligned_access, cpu);
> +
> +	return __check_unaligned_access_table(cpu, ptr,
> +					      ARRAY_SIZE(vec_unaligned_access_table_entries),
> +					      vec_unaligned_access_table_entries);
>  }
>  
>  static int riscv_online_cpu_vec(unsigned int cpu)
> -- 
> 2.48.1
> 

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  reply	other threads:[~2025-02-07 18:19 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-07 16:19 [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Andrew Jones
2025-02-07 16:19 ` [PATCH 1/9] riscv: Annotate unaligned access init functions Andrew Jones
2025-02-13 12:59   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Andrew Jones
2025-02-07 16:47   ` Clément Léger
2025-02-07 17:08     ` Andrew Jones
2025-02-07 17:43       ` Clément Léger
2025-02-07 18:08         ` Andrew Jones
2025-02-13 13:02   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 3/9] riscv: Fix check_unaligned_access_all_cpus Andrew Jones
2025-02-13 13:12   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 4/9] riscv: Change check_unaligned_access_speed_all_cpus to void Andrew Jones
2025-02-07 16:42   ` Clément Léger
2025-02-13 13:15   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 5/9] riscv: Fix set up of cpu hotplug callbacks Andrew Jones
2025-02-07 16:44   ` Clément Léger
2025-02-13 13:25   ` Alexandre Ghiti
2025-02-13 13:33   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback Andrew Jones
2025-02-07 17:36   ` Clément Léger
2025-02-07 18:15     ` Andrew Jones
2025-02-13 13:28   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Andrew Jones
2025-02-08  1:22   ` Charlie Jenkins
2025-02-10  9:43     ` Andrew Jones
2025-02-10 17:10       ` Charlie Jenkins
2025-02-10 10:16     ` Anup Patel
2025-02-10 11:07       ` Clément Léger
2025-02-10 14:06         ` Andrew Jones
2025-02-10 14:20           ` Clément Léger
2025-02-10 17:20             ` Charlie Jenkins
2025-02-10 20:42               ` Clément Léger
2025-02-10 20:53                 ` Charlie Jenkins
2025-02-10 20:57                   ` Clément Léger
2025-02-10 21:13                     ` Charlie Jenkins
2025-02-11  4:26                     ` Anup Patel
2025-02-11  8:37                       ` Clément Léger
2025-02-11 18:09                       ` Palmer Dabbelt
2025-02-10 17:19       ` Charlie Jenkins
2025-02-10 20:37         ` Clément Léger
2025-02-11  9:04           ` Andrew Jones
2025-02-07 16:19 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 16:19 ` [PATCH 9/9] riscv: Add Ventana unaligned access table entries Andrew Jones
2025-02-07 18:10 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 18:19   ` Andrew Jones [this message]
2025-02-08  7:59 ` [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Anup Patel
2025-02-10  9:26   ` Andrew Jones
2025-02-10  9:58     ` Anup Patel
2025-02-10 11:01       ` Andrew Jones

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