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From: Andrew Jones <ajones@ventanamicro.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 paul.walmsley@sifive.com, palmer@dabbelt.com,
	charlie@rivosinc.com, jesse@rivosinc.com
Subject: Re: [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping
Date: Mon, 10 Feb 2025 12:01:23 +0100	[thread overview]
Message-ID: <20250210-c79541eaea0d2d922f019384@orel> (raw)
In-Reply-To: <CAK9=C2X5Hu_LQHmXUea7Xhq5cHaJqtcncgwUeb2+2uMvbTiW3w@mail.gmail.com>

On Mon, Feb 10, 2025 at 03:28:13PM +0530, Anup Patel wrote:
> On Mon, Feb 10, 2025 at 2:56 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> >
> > On Sat, Feb 08, 2025 at 01:29:42PM +0530, Anup Patel wrote:
> > > On Fri, Feb 7, 2025 at 9:49 PM Andrew Jones <ajones@ventanamicro.com> wrote:
> > > >
> > > > The first six patches of this series are fixes and cleanups of the
> > > > unaligned access speed probing code. The next two patches introduce
> > > > support to skip probing by matching vendor/arch/imp ids and checking a
> > > > table for the access speed type. The last patch applies the new skip
> > > > support to Ventana harts.
> > >
> > > Alternatively, we can also skip probing misaligned access when Zicclsm
> > > extension is present in the ISA string. The Zicclsm extension is defined
> > > as part of the ratified RVA23 profile.
> >
> > The definition of Zicclsm doesn't explicitly state that misaligned word
> > accesses will be faster than byte accesses to the same addresses. There's
> > also this spec issue[1] which appears to state that Zicclsm cannot be used
> > to infer fast misaligned accesses.
> >
> > But, like Charlie suggests, maybe we should advocate the creation of an
> > extension (or "named feature") which allows specifically advertising that
> > misaligned accesses are fast.
> >
> > [1] https://github.com/riscv/riscv-isa-manual/issues/1611
> 
> I am not sure when such an extension would show up so for now
> skipping unaligned tests based on implementation ID seems
> reasonable.
> 
> Also, it seems this series is totally skipping the existing boot-time
> print for fast unaligned access. Please try to keep the boot-time
> print in some form.

Sure. We have hwprobe, but now that people are likely used to seeing it
in dmesg, then we should probably keep something there.

Thanks,
drew

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      reply	other threads:[~2025-02-10 11:20 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-07 16:19 [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Andrew Jones
2025-02-07 16:19 ` [PATCH 1/9] riscv: Annotate unaligned access init functions Andrew Jones
2025-02-13 12:59   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Andrew Jones
2025-02-07 16:47   ` Clément Léger
2025-02-07 17:08     ` Andrew Jones
2025-02-07 17:43       ` Clément Léger
2025-02-07 18:08         ` Andrew Jones
2025-02-13 13:02   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 3/9] riscv: Fix check_unaligned_access_all_cpus Andrew Jones
2025-02-13 13:12   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 4/9] riscv: Change check_unaligned_access_speed_all_cpus to void Andrew Jones
2025-02-07 16:42   ` Clément Léger
2025-02-13 13:15   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 5/9] riscv: Fix set up of cpu hotplug callbacks Andrew Jones
2025-02-07 16:44   ` Clément Léger
2025-02-13 13:25   ` Alexandre Ghiti
2025-02-13 13:33   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback Andrew Jones
2025-02-07 17:36   ` Clément Léger
2025-02-07 18:15     ` Andrew Jones
2025-02-13 13:28   ` Alexandre Ghiti
2025-02-07 16:19 ` [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Andrew Jones
2025-02-08  1:22   ` Charlie Jenkins
2025-02-10  9:43     ` Andrew Jones
2025-02-10 17:10       ` Charlie Jenkins
2025-02-10 10:16     ` Anup Patel
2025-02-10 11:07       ` Clément Léger
2025-02-10 14:06         ` Andrew Jones
2025-02-10 14:20           ` Clément Léger
2025-02-10 17:20             ` Charlie Jenkins
2025-02-10 20:42               ` Clément Léger
2025-02-10 20:53                 ` Charlie Jenkins
2025-02-10 20:57                   ` Clément Léger
2025-02-10 21:13                     ` Charlie Jenkins
2025-02-11  4:26                     ` Anup Patel
2025-02-11  8:37                       ` Clément Léger
2025-02-11 18:09                       ` Palmer Dabbelt
2025-02-10 17:19       ` Charlie Jenkins
2025-02-10 20:37         ` Clément Léger
2025-02-11  9:04           ` Andrew Jones
2025-02-07 16:19 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 16:19 ` [PATCH 9/9] riscv: Add Ventana unaligned access table entries Andrew Jones
2025-02-07 18:10 ` [PATCH 8/9] riscv: Implement check_unaligned_access_table Andrew Jones
2025-02-07 18:19   ` Andrew Jones
2025-02-08  7:59 ` [PATCH 0/9] riscv: Unaligned access speed probing fixes and skipping Anup Patel
2025-02-10  9:26   ` Andrew Jones
2025-02-10  9:58     ` Anup Patel
2025-02-10 11:01       ` Andrew Jones [this message]

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