[v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[Andy Chiu]

The series composes of two parts. The first part provides a quick fix for
the issue on a recent thread[1]. The issue happens when a platform has
ununified vector register length across multiple cores. Specifically,
patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
vlenb is observed by the system. Patch 2 fixes the issue by failing the
boot process of a secondary core if vlenb mismatches.

The second part of the series provide a finer grain view of the Vector
extension. Patch 3 give the obsolete ISA parser the ability to expand
ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x,
Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5
updates all callsites such that Vector subextensions are maximumly
supported by the kernel.

Two parts of the series are sent together to ease the effort of picking
dependency patches. The first part can be merged independent of the
second one if necessary.

The series is tested on a QEMU and verified that booting, Vector
programs context-switch, signal, ptrace, prctl(sysctl knob) interfaces
works when we only report partial V from the ISA.

This patch should be able to apply on risc-v for-next branch on top of
the commit 886516fae2b7 ("RISC-V: fix check for zvkb with tip-of-tree clang")

[1]: https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u

Andy Chiu (6):
  riscv: vector: add a comment when calling riscv_setup_vsize()
  riscv: smp: fail booting up smp if inconsistent vlen is detected
  riscv: cpufeature: call match_isa_ext() for single-letter extensions
  riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
  riscv: hwprobe: add zve Vector subextesnions into hwprobe interface
  riscv: vector: adjust minimum Vector requirement to ZVE32X

 Documentation/arch/riscv/hwprobe.rst   | 15 +++++++
 arch/riscv/include/asm/hwcap.h         |  5 +++
 arch/riscv/include/asm/switch_to.h     |  2 +-
 arch/riscv/include/asm/vector.h        | 21 ++++++----
 arch/riscv/include/asm/xor.h           |  2 +-
 arch/riscv/include/uapi/asm/hwprobe.h  |  5 +++
 arch/riscv/kernel/cpufeature.c         | 57 +++++++++++++++++++++++---
 arch/riscv/kernel/head.S               | 14 +++----
 arch/riscv/kernel/kernel_mode_vector.c |  4 +-
 arch/riscv/kernel/process.c            |  4 +-
 arch/riscv/kernel/signal.c             |  6 +--
 arch/riscv/kernel/smpboot.c            | 14 ++++---
 arch/riscv/kernel/sys_hwprobe.c        | 12 ++++--
 arch/riscv/kernel/vector.c             | 15 ++++---
 arch/riscv/lib/uaccess.S               |  2 +-
 15 files changed, 135 insertions(+), 43 deletions(-)

-- 
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[v1, 1/6] riscv: vector: add a comment when calling riscv_setup_vsize()

[Andy Chiu]

The function would fail when it detects the calling hart's vlen doesn't
match the first one's. The boot hart is the first hart calling this
function during riscv_fill_hwcap, so it is impossible to fail here. Add
a comment about this behavior.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 89920f84d0a3..1b21f1e568e1 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -671,6 +671,10 @@ void __init riscv_fill_hwcap(void)
 	}
 
 	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+		/*
+		 * This callsite can't fail here. This is the first time we
+		 * call during boot, so riscv_v_vsize must be zero.
+		 */
 		riscv_v_setup_vsize();
 		/*
 		 * ISA string in device tree might have 'v' flag, but
-- 
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[v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected

[Andy Chiu]

Currently we only support Vector for SMP platforms, that is, all SMP
cores have the same vlenb. If we happen to detect a mismatching vlen, it
is better to just fail bootting it up to prevent further race/scheduling
issues.

Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context")
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/head.S    | 14 +++++++-------
 arch/riscv/kernel/smpboot.c | 14 +++++++++-----
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 4236a69c35cb..a158fa9f2656 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -165,9 +165,15 @@ secondary_start_sbi:
 #endif
 	call .Lsetup_trap_vector
 	scs_load_current
-	tail smp_callin
+	call smp_callin
 #endif /* CONFIG_SMP */
 
+.align 2
+.Lsecondary_park:
+	/* We lack SMP support or have too many harts, so park this hart */
+	wfi
+	j .Lsecondary_park
+
 .align 2
 .Lsetup_trap_vector:
 	/* Set trap vector to exception handler */
@@ -181,12 +187,6 @@ secondary_start_sbi:
 	csrw CSR_SCRATCH, zero
 	ret
 
-.align 2
-.Lsecondary_park:
-	/* We lack SMP support or have too many harts, so park this hart */
-	wfi
-	j .Lsecondary_park
-
 SYM_CODE_END(_start)
 
 SYM_CODE_START(_start_kernel)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index cfbe4b840d42..1f86ee10192f 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -218,6 +218,15 @@ asmlinkage __visible void smp_callin(void)
 	struct mm_struct *mm = &init_mm;
 	unsigned int curr_cpuid = smp_processor_id();
 
+	if (has_vector()) {
+		/*
+		 * Return as early as possible so the hart with a mismatching
+		 * vlen won't boot.
+		 */
+		if (riscv_v_setup_vsize())
+			return;
+	}
+
 	/* All kernel threads share the same mm context.  */
 	mmgrab(mm);
 	current->active_mm = mm;
@@ -230,11 +239,6 @@ asmlinkage __visible void smp_callin(void)
 	numa_add_cpu(curr_cpuid);
 	set_cpu_online(curr_cpuid, 1);
 
-	if (has_vector()) {
-		if (riscv_v_setup_vsize())
-			elf_hwcap &= ~COMPAT_HWCAP_ISA_V;
-	}
-
 	riscv_user_isa_enable();
 
 	/*
-- 
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[v1, 3/6] riscv: cpufeature: call match_isa_ext() for single-letter extensions

[Andy Chiu]

Single-letter extensions may also imply multiple subextensions. For
example, Vector extension implies zve64d, and zve64d implies zve64f.

Extension parsing for "riscv,isa-extensions" has the ability to resolve
the dependency by calling match_isa_ext(). This patch makes deprecated
parser call the same function for single letter extensions.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/kernel/cpufeature.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1b21f1e568e1..8986ceb58188 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -470,6 +470,10 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 
 		if (unlikely(ext_err))
 			continue;
+
+		for (int i = 0; i < riscv_isa_ext_count; i++)
+			match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
+
 		if (!ext_long) {
 			int nr = tolower(*ext) - 'a';
 
@@ -477,9 +481,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
 				*this_hwcap |= isa2hwcap[nr];
 				set_bit(nr, isainfo->isa);
 			}
-		} else {
-			for (int i = 0; i < riscv_isa_ext_count; i++)
-				match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo);
 		}
 	}
 }
-- 
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[v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Andy Chiu]

Multiple Vector subextensions are added. Also, the patch takes care of
the dependencies of Vector subextensions by macro expansions. So, if
some "embedded" platform only reports "zve64f" on the ISA string, the
parser is able to expand it to zve32x zve32f zve64x and zve64f.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/include/asm/hwcap.h |  5 +++++
 arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
 2 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5340f818746b..24efea44f1ab 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -80,6 +80,11 @@
 #define RISCV_ISA_EXT_ZFA		71
 #define RISCV_ISA_EXT_ZTSO		72
 #define RISCV_ISA_EXT_ZACAS		73
+#define RISCV_ISA_EXT_ZVE32X		74
+#define RISCV_ISA_EXT_ZVE32F		75
+#define RISCV_ISA_EXT_ZVE64X		76
+#define RISCV_ISA_EXT_ZVE64F		77
+#define RISCV_ISA_EXT_ZVE64D		78
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 8986ceb58188..3aa0df3f3b41 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
 	RISCV_ISA_EXT_ZVKB
 };
 
+#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE32F,		\
+	RISCV_ISA_EXT_ZVE32X,
+
+#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE64F,		\
+	RISCV_ISA_EXT_ZVE64X,		\
+	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
+
+#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
+	RISCV_ISA_EXT_ZVE64D,		\
+	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
+
+static const unsigned int riscv_zve32f_exts[] = {
+	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64f_exts[] = {
+	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64d_exts[] = {
+	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
+};
+
+static const unsigned int riscv_zve64x_exts[] = {
+	RISCV_ISA_EXT_ZVE32X,
+	RISCV_ISA_EXT_ZVE64X
+};
+
+static const unsigned int riscv_v_exts[] = {
+	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
+};
+
 /*
  * The canonical order of ISA extension names in the ISA string is defined in
  * chapter 27 of the unprivileged specification.
@@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
 	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
 	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
-	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
+	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
 	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
 	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
@@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
 	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
 	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
+	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
+	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
+	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
+	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
+	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
 	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
 	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
 	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
-- 
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[v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface

[Andy Chiu]

The following Vector subextensions for "embedded" platforms are added
into RISCV_HWPROBE_KEY_IMA_EXT_0:
 - ZVE32X
 - ZVE32F
 - ZVE64X
 - ZVE64F
 - ZVE64D

Extensions end with X mean the platform don't have a Vector FPU.
Extensions end with F/D mean whether single (F) or double (D) precision
Vector operation is supported.

The number 32 or 64 follows from ZVE tells the maximum element length.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
 arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
 arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
 3 files changed, 25 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index b2bcc9eed9aa..d0b02e012e5d 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -188,6 +188,21 @@ The following keys are defined:
        manual starting from commit 95cf1f9 ("Add changes requested by Ved
        during signoff")
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
+    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 9f2a8e3ff204..b9a0876e969f 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -59,6 +59,11 @@ struct riscv_hwprobe {
 #define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
 #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
 #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
+#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 36)
+#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 37)
+#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 38)
+#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 39)
+#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 40)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index a7c56b41efd2..2500d175ed66 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -111,6 +111,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZTSO);
 		EXT_KEY(ZACAS);
 		EXT_KEY(ZICOND);
+		EXT_KEY(ZVE32X);
+		EXT_KEY(ZVE32F);
+		EXT_KEY(ZVE64X);
+		EXT_KEY(ZVE64F);
+		EXT_KEY(ZVE64D);
 
 		if (has_vector()) {
 			EXT_KEY(ZVBB);
-- 
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[v1, 6/6] riscv: vector: adjust minimum Vector requirement to ZVE32X

[Andy Chiu]

Make has_vector take one argument. This argument represents the minimum
Vector subextension that the following Vector actions assume.

Also, change riscv_v_first_use_handler(), and boot code that calls
riscv_v_setup_vsize() to accept the minimum Vector sub-extension,
ZVE32X.

Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs
compiled and run with ZVE32X should be supported by the kernel on most
aspects. This includes context-switch, signal, ptrace, prctl, and
hwprobe.

One exception is that ELF_HWCAP returns 'V' only if full V is supported
on the platform. This means that the system without a full V must not
rely on ELF_HWCAP to tell whether it is allowable to execute Vector
without first invoking a prctl() check.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
---
 arch/riscv/include/asm/switch_to.h     |  2 +-
 arch/riscv/include/asm/vector.h        | 21 ++++++++++++++-------
 arch/riscv/include/asm/xor.h           |  2 +-
 arch/riscv/kernel/cpufeature.c         |  5 ++++-
 arch/riscv/kernel/kernel_mode_vector.c |  4 ++--
 arch/riscv/kernel/process.c            |  4 ++--
 arch/riscv/kernel/signal.c             |  6 +++---
 arch/riscv/kernel/smpboot.c            |  2 +-
 arch/riscv/kernel/sys_hwprobe.c        |  5 +++--
 arch/riscv/kernel/vector.c             | 15 +++++++++------
 arch/riscv/lib/uaccess.S               |  2 +-
 11 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 7efdb0584d47..df1adf196c4f 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -78,7 +78,7 @@ do {							\
 	struct task_struct *__next = (next);		\
 	if (has_fpu())					\
 		__switch_to_fpu(__prev, __next);	\
-	if (has_vector())					\
+	if (has_vector(ZVE32X))			\
 		__switch_to_vector(__prev, __next);	\
 	((last) = __switch_to(__prev, __next));		\
 } while (0)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 731dcd0ed4de..b96750493dfb 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -18,6 +18,7 @@
 #include <asm/cpufeature.h>
 #include <asm/csr.h>
 #include <asm/asm.h>
+#include <asm/bug.h>
 
 extern unsigned long riscv_v_vsize;
 int riscv_v_setup_vsize(void);
@@ -35,10 +36,16 @@ static inline u32 riscv_v_flags(void)
 	return READ_ONCE(current->thread.riscv_v_flags);
 }
 
-static __always_inline bool has_vector(void)
-{
-	return riscv_has_extension_unlikely(RISCV_ISA_EXT_v);
-}
+#define has_vector(VEXT)						\
+({									\
+	static_assert(RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32X ||	\
+		      RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32F ||	\
+		      RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64X ||	\
+		      RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64F ||	\
+		      RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64D ||	\
+		      RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_v);		\
+	riscv_has_extension_unlikely(RISCV_ISA_EXT_##VEXT);		\
+})
 
 static inline void __riscv_v_vstate_clean(struct pt_regs *regs)
 {
@@ -131,7 +138,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_
 	riscv_v_enable();
 	asm volatile (
 		".option push\n\t"
-		".option arch, +v\n\t"
+		".option arch, +zve32x\n\t"
 		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"
 		"vle8.v		v0, (%1)\n\t"
 		"add		%1, %1, %0\n\t"
@@ -153,7 +160,7 @@ static inline void __riscv_v_vstate_discard(void)
 	riscv_v_enable();
 	asm volatile (
 		".option push\n\t"
-		".option arch, +v\n\t"
+		".option arch, +zve32x\n\t"
 		"vsetvli	%0, x0, e8, m8, ta, ma\n\t"
 		"vmv.v.i	v0, -1\n\t"
 		"vmv.v.i	v8, -1\n\t"
@@ -267,7 +274,7 @@ bool riscv_v_vstate_ctrl_user_allowed(void);
 struct pt_regs;
 
 static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; }
-static __always_inline bool has_vector(void) { return false; }
+static __always_inline bool has_vector(unsigned long min_sub_ext) { return false; }
 static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; }
 static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }
 static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }
diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
index 96011861e46b..46042ef5a2f7 100644
--- a/arch/riscv/include/asm/xor.h
+++ b/arch/riscv/include/asm/xor.h
@@ -61,7 +61,7 @@ static struct xor_block_template xor_block_rvv = {
 	do {        \
 		xor_speed(&xor_block_8regs);    \
 		xor_speed(&xor_block_32regs);    \
-		if (has_vector()) { \
+		if (has_vector(ZVE32X)) { \
 			xor_speed(&xor_block_rvv);\
 		} \
 	} while (0)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 3aa0df3f3b41..4879f88660cd 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -710,12 +710,15 @@ void __init riscv_fill_hwcap(void)
 		elf_hwcap &= ~COMPAT_HWCAP_ISA_F;
 	}
 
-	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
+	if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) {
 		/*
 		 * This callsite can't fail here. This is the first time we
 		 * call during boot, so riscv_v_vsize must be zero.
 		 */
 		riscv_v_setup_vsize();
+	}
+
+	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
 		/*
 		 * ISA string in device tree might have 'v' flag, but
 		 * CONFIG_RISCV_ISA_V is disabled in kernel.
diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c
index 6afe80c7f03a..0d4d1a03d1c7 100644
--- a/arch/riscv/kernel/kernel_mode_vector.c
+++ b/arch/riscv/kernel/kernel_mode_vector.c
@@ -208,7 +208,7 @@ void kernel_vector_begin(void)
 {
 	bool nested = false;
 
-	if (WARN_ON(!has_vector()))
+	if (WARN_ON(!has_vector(ZVE32X)))
 		return;
 
 	BUG_ON(!may_use_simd());
@@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin);
  */
 void kernel_vector_end(void)
 {
-	if (WARN_ON(!has_vector()))
+	if (WARN_ON(!has_vector(ZVE32X)))
 		return;
 
 	riscv_v_disable();
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index 92922dbd5b5c..919e72f9fff6 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -178,7 +178,7 @@ void flush_thread(void)
 void arch_release_task_struct(struct task_struct *tsk)
 {
 	/* Free the vector context of datap. */
-	if (has_vector())
+	if (has_vector(ZVE32X))
 		riscv_v_thread_free(tsk);
 }
 
@@ -225,7 +225,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
 		p->thread.s[0] = 0;
 	}
 	p->thread.riscv_v_flags = 0;
-	if (has_vector())
+	if (has_vector(ZVE32X))
 		riscv_v_thread_alloc(p);
 	p->thread.ra = (unsigned long)ret_from_fork;
 	p->thread.sp = (unsigned long)childregs; /* kernel sp */
diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c
index 501e66debf69..a96e6e969a3f 100644
--- a/arch/riscv/kernel/signal.c
+++ b/arch/riscv/kernel/signal.c
@@ -188,7 +188,7 @@ static long restore_sigcontext(struct pt_regs *regs,
 
 			return 0;
 		case RISCV_V_MAGIC:
-			if (!has_vector() || !riscv_v_vstate_query(regs) ||
+			if (!has_vector(ZVE32X) || !riscv_v_vstate_query(regs) ||
 			    size != riscv_v_sc_size)
 				return -EINVAL;
 
@@ -210,7 +210,7 @@ static size_t get_rt_frame_size(bool cal_all)
 
 	frame_size = sizeof(*frame);
 
-	if (has_vector()) {
+	if (has_vector(ZVE32X)) {
 		if (cal_all || riscv_v_vstate_query(task_pt_regs(current)))
 			total_context_size += riscv_v_sc_size;
 	}
@@ -283,7 +283,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame,
 	if (has_fpu())
 		err |= save_fp_state(regs, &sc->sc_fpregs);
 	/* Save the vector state. */
-	if (has_vector() && riscv_v_vstate_query(regs))
+	if (has_vector(ZVE32X) && riscv_v_vstate_query(regs))
 		err |= save_v_state(regs, (void __user **)&sc_ext_ptr);
 	/* Write zero to fp-reserved space and check it on restore_sigcontext */
 	err |= __put_user(0, &sc->sc_extdesc.reserved);
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 1f86ee10192f..4eb36d75f091 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -218,7 +218,7 @@ asmlinkage __visible void smp_callin(void)
 	struct mm_struct *mm = &init_mm;
 	unsigned int curr_cpuid = smp_processor_id();
 
-	if (has_vector()) {
+	if (has_vector(ZVE32X)) {
 		/*
 		 * Return as early as possible so the hart with a mismatching
 		 * vlen won't boot.
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 2500d175ed66..37c441489c7e 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -69,7 +69,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (riscv_isa_extension_available(NULL, c))
 		pair->value |= RISCV_HWPROBE_IMA_C;
 
-	if (has_vector())
+	if (has_vector(v))
 		pair->value |= RISCV_HWPROBE_IMA_V;
 
 	/*
@@ -117,7 +117,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(ZVE64F);
 		EXT_KEY(ZVE64D);
 
-		if (has_vector()) {
+		/*  Most Vector crypto extensions require at least ZVE32X */
+		if (has_vector(ZVE32X)) {
 			EXT_KEY(ZVBB);
 			EXT_KEY(ZVBC);
 			EXT_KEY(ZVKB);
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 6727d1d3b8f2..e8a47fa72351 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -53,7 +53,7 @@ int riscv_v_setup_vsize(void)
 
 void __init riscv_v_setup_ctx_cache(void)
 {
-	if (!has_vector())
+	if (!has_vector(ZVE32X))
 		return;
 
 	riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx",
@@ -173,8 +173,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs)
 	u32 __user *epc = (u32 __user *)regs->epc;
 	u32 insn = (u32)regs->badaddr;
 
+	if (!has_vector(ZVE32X))
+		return false;
+
 	/* Do not handle if V is not supported, or disabled */
-	if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V))
+	if (!riscv_v_vstate_ctrl_user_allowed())
 		return false;
 
 	/* If V has been enabled then it is not the first-use trap */
@@ -213,7 +216,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk)
 	bool inherit;
 	int cur, next;
 
-	if (!has_vector())
+	if (!has_vector(ZVE32X))
 		return;
 
 	next = riscv_v_ctrl_get_next(tsk);
@@ -235,7 +238,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk)
 
 long riscv_v_vstate_ctrl_get_current(void)
 {
-	if (!has_vector())
+	if (!has_vector(ZVE32X))
 		return -EINVAL;
 
 	return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK;
@@ -246,7 +249,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg)
 	bool inherit;
 	int cur, next;
 
-	if (!has_vector())
+	if (!has_vector(ZVE32X))
 		return -EINVAL;
 
 	if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK)
@@ -296,7 +299,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = {
 
 static int __init riscv_v_sysctl_init(void)
 {
-	if (has_vector())
+	if (has_vector(ZVE32X))
 		if (!register_sysctl("abi", riscv_v_default_vstate_table))
 			return -EINVAL;
 	return 0;
diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
index bc22c078aba8..bbe143bb32a0 100644
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@ -14,7 +14,7 @@
 
 SYM_FUNC_START(__asm_copy_to_user)
 #ifdef CONFIG_RISCV_ISA_V
-	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V)
+	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V)
 	REG_L	t0, riscv_v_usercopy_threshold
 	bltu	a2, t0, fallback_scalar_usercopy
 	tail enter_vector_usercopy
-- 
2.17.1


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Re: [v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface

[Clément Léger]

On 12/03/2024 13:36, Andy Chiu wrote:
> The following Vector subextensions for "embedded" platforms are added
> into RISCV_HWPROBE_KEY_IMA_EXT_0:
>  - ZVE32X
>  - ZVE32F
>  - ZVE64X
>  - ZVE64F
>  - ZVE64D
> 
> Extensions end with X mean the platform don't have a Vector FPU.
> Extensions end with F/D mean whether single (F) or double (D) precision
> Vector operation is supported.
> 
> The number 32 or 64 follows from ZVE tells the maximum element length.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
>  arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
>  arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
>  3 files changed, 25 insertions(+)
> 
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index b2bcc9eed9aa..d0b02e012e5d 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -188,6 +188,21 @@ The following keys are defined:
>         manual starting from commit 95cf1f9 ("Add changes requested by Ved
>         during signoff")
>  
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
>    information about the selected set of processors.
>  
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 9f2a8e3ff204..b9a0876e969f 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -59,6 +59,11 @@ struct riscv_hwprobe {
>  #define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
>  #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
>  #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
> +#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 36)
> +#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 37)
> +#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 38)
> +#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 39)
> +#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 40)
>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index a7c56b41efd2..2500d175ed66 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -111,6 +111,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>  		EXT_KEY(ZTSO);
>  		EXT_KEY(ZACAS);
>  		EXT_KEY(ZICOND);
> +		EXT_KEY(ZVE32X);
> +		EXT_KEY(ZVE32F);
> +		EXT_KEY(ZVE64X);
> +		EXT_KEY(ZVE64F);
> +		EXT_KEY(ZVE64D);

Hi Andy,

I'm not sure but since these extensions are conditioned by the fact
vector should be supported by the kernel, they probably needs to be put
under the if below:

>  
>  		if (has_vector()) {

			<--- Here --->
>  			EXT_KEY(ZVBB);

Thanks !

Clément

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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Clément Léger]

On 12/03/2024 13:36, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),

Hi Andy,

Nit: Since RISCV_ISA_EXT_ZVE32F is already used here as .id, you don't
need to insert it in the riscv_zve32f_exts array. It won't hurt but the
existing extensions that uses the __RISCV_ISA_EXT_SUPERSET() macro don't
do that.

> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),

Ditto for the last 3 __RISCV_ISA_EXT_SUPERSET().

Apart from that, it looks good !

Thanks,

Clément

>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),

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Re: [v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface

[Clément Léger]

Oh and one other thing, there is a typo in the commit title:
"subextesnions" instead of "subextensions"

Thanks !

Clément

On 12/03/2024 13:42, Clément Léger wrote:
> 
> 
> On 12/03/2024 13:36, Andy Chiu wrote:
>> The following Vector subextensions for "embedded" platforms are added
>> into RISCV_HWPROBE_KEY_IMA_EXT_0:
>>  - ZVE32X
>>  - ZVE32F
>>  - ZVE64X
>>  - ZVE64F
>>  - ZVE64D
>>
>> Extensions end with X mean the platform don't have a Vector FPU.
>> Extensions end with F/D mean whether single (F) or double (D) precision
>> Vector operation is supported.
>>
>> The number 32 or 64 follows from ZVE tells the maximum element length.
>>
>> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
>> ---
>>  Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
>>  arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
>>  arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
>>  3 files changed, 25 insertions(+)
>>
>> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
>> index b2bcc9eed9aa..d0b02e012e5d 100644
>> --- a/Documentation/arch/riscv/hwprobe.rst
>> +++ b/Documentation/arch/riscv/hwprobe.rst
>> @@ -188,6 +188,21 @@ The following keys are defined:
>>         manual starting from commit 95cf1f9 ("Add changes requested by Ved
>>         during signoff")
>>  
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
>> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
>> +
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
>> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
>> +
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
>> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
>> +
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
>> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
>> +
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
>> +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
>> +
>>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
>>    information about the selected set of processors.
>>  
>> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
>> index 9f2a8e3ff204..b9a0876e969f 100644
>> --- a/arch/riscv/include/uapi/asm/hwprobe.h
>> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
>> @@ -59,6 +59,11 @@ struct riscv_hwprobe {
>>  #define		RISCV_HWPROBE_EXT_ZTSO		(1ULL << 33)
>>  #define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)
>>  #define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)
>> +#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 36)
>> +#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 37)
>> +#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 38)
>> +#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 39)
>> +#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 40)
>>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
>> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
>> index a7c56b41efd2..2500d175ed66 100644
>> --- a/arch/riscv/kernel/sys_hwprobe.c
>> +++ b/arch/riscv/kernel/sys_hwprobe.c
>> @@ -111,6 +111,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>>  		EXT_KEY(ZTSO);
>>  		EXT_KEY(ZACAS);
>>  		EXT_KEY(ZICOND);
>> +		EXT_KEY(ZVE32X);
>> +		EXT_KEY(ZVE32F);
>> +		EXT_KEY(ZVE64X);
>> +		EXT_KEY(ZVE64F);
>> +		EXT_KEY(ZVE64D);
> 
> Hi Andy,
> 
> I'm not sure but since these extensions are conditioned by the fact
> vector should be supported by the kernel, they probably needs to be put
> under the if below:
> 
>>  
>>  		if (has_vector()) {
> 
> 			<--- Here --->
>>  			EXT_KEY(ZVBB);
> 
> Thanks !
> 
> Clément

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Re: [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1905 bytes --]

On Tue, Mar 12, 2024 at 08:36:23PM +0800, Andy Chiu wrote:
> Currently we only support Vector for SMP platforms, that is, all SMP
> cores have the same vlenb. If we happen to detect a mismatching vlen, it
> is better to just fail bootting it up to prevent further race/scheduling
> issues.
> 
> Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context")
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

Reported-by: Conor Dooley <conor.dooley@microchip.com>
Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/
cc: stable@vger.kernel.org

I actually thought I had sent a patch for this, but I don't seem to
have. I did write one, so I guess I just did not send it.

> ---
>  arch/riscv/kernel/head.S    | 14 +++++++-------
>  arch/riscv/kernel/smpboot.c | 14 +++++++++-----
>  2 files changed, 16 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index 4236a69c35cb..a158fa9f2656 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -165,9 +165,15 @@ secondary_start_sbi:
>  #endif
>  	call .Lsetup_trap_vector
>  	scs_load_current
> -	tail smp_callin
> +	call smp_callin
>  #endif /* CONFIG_SMP */
>  
> +.align 2
> +.Lsecondary_park:
> +	/* We lack SMP support or have too many harts, so park this hart */
> +	wfi
> +	j .Lsecondary_park
> +
>  .align 2
>  .Lsetup_trap_vector:
>  	/* Set trap vector to exception handler */
> @@ -181,12 +187,6 @@ secondary_start_sbi:
>  	csrw CSR_SCRATCH, zero
>  	ret
>  
> -.align 2
> -.Lsecondary_park:
> -	/* We lack SMP support or have too many harts, so park this hart */
> -	wfi
> -	j .Lsecondary_park
> -
>  SYM_CODE_END(_start)
>  
>  SYM_CODE_START(_start_kernel)

Why does this change? There's no mention of why in the commit message.

Thanks,
Conor.

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Re: [v1, 1/6] riscv: vector: add a comment when calling riscv_setup_vsize()

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1359 bytes --]

On Tue, Mar 12, 2024 at 08:36:22PM +0800, Andy Chiu wrote:
> The function would fail when it detects the calling hart's vlen doesn't
> match the first one's. The boot hart is the first hart calling this
> function during riscv_fill_hwcap, so it is impossible to fail here. Add
> a comment about this behavior.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/kernel/cpufeature.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 89920f84d0a3..1b21f1e568e1 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -671,6 +671,10 @@ void __init riscv_fill_hwcap(void)
>  	}
>  
>  	if (elf_hwcap & COMPAT_HWCAP_ISA_V) {
> +		/*
> +		 * This callsite can't fail here. This is the first time we
> +		 * call during boot,

> so riscv_v_vsize must be zero.

The last part of this comment does not make sense, just say that it
cannot fail when called on the boot hart and leave it at that.

> +		 */
>  		riscv_v_setup_vsize();
>  		/*
>  		 * ISA string in device tree might have 'v' flag, but
> -- 
> 2.17.1
> 
> 
> _______________________________________________
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> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 4085 bytes --]

On Tue, Mar 12, 2024 at 08:36:25PM +0800, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>

These new extensions need to be added to the dt-bindings.

> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> -- 
> 2.17.1
> 
> 
> _______________________________________________
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Re: [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[Stefan O'Rear]

On Tue, Mar 12, 2024, at 8:36 AM, Andy Chiu wrote:
> The series composes of two parts. The first part provides a quick fix for
> the issue on a recent thread[1]. The issue happens when a platform has
> ununified vector register length across multiple cores. Specifically,
> patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
> vlenb is observed by the system. Patch 2 fixes the issue by failing the
> boot process of a secondary core if vlenb mismatches.
>
> The second part of the series provide a finer grain view of the Vector
> extension. Patch 3 give the obsolete ISA parser the ability to expand
> ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x,
> Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5
> updates all callsites such that Vector subextensions are maximumly
> supported by the kernel.

What is the end user programming interface for this intended to be? prctl
call using inline asm ecall in the ifunc resolver, possibly automated using
function multi-versioning? Can we do better with a different interface?

-s

> Two parts of the series are sent together to ease the effort of picking
> dependency patches. The first part can be merged independent of the
> second one if necessary.
>
> The series is tested on a QEMU and verified that booting, Vector
> programs context-switch, signal, ptrace, prctl(sysctl knob) interfaces
> works when we only report partial V from the ISA.
>
> This patch should be able to apply on risc-v for-next branch on top of
> the commit 886516fae2b7 ("RISC-V: fix check for zvkb with tip-of-tree clang")
>
> [1]: 
> https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u
>
> Andy Chiu (6):
>   riscv: vector: add a comment when calling riscv_setup_vsize()
>   riscv: smp: fail booting up smp if inconsistent vlen is detected
>   riscv: cpufeature: call match_isa_ext() for single-letter extensions
>   riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
>   riscv: hwprobe: add zve Vector subextesnions into hwprobe interface
>   riscv: vector: adjust minimum Vector requirement to ZVE32X
>
>  Documentation/arch/riscv/hwprobe.rst   | 15 +++++++
>  arch/riscv/include/asm/hwcap.h         |  5 +++
>  arch/riscv/include/asm/switch_to.h     |  2 +-
>  arch/riscv/include/asm/vector.h        | 21 ++++++----
>  arch/riscv/include/asm/xor.h           |  2 +-
>  arch/riscv/include/uapi/asm/hwprobe.h  |  5 +++
>  arch/riscv/kernel/cpufeature.c         | 57 +++++++++++++++++++++++---
>  arch/riscv/kernel/head.S               | 14 +++----
>  arch/riscv/kernel/kernel_mode_vector.c |  4 +-
>  arch/riscv/kernel/process.c            |  4 +-
>  arch/riscv/kernel/signal.c             |  6 +--
>  arch/riscv/kernel/smpboot.c            | 14 ++++---
>  arch/riscv/kernel/sys_hwprobe.c        | 12 ++++--
>  arch/riscv/kernel/vector.c             | 15 ++++---
>  arch/riscv/lib/uaccess.S               |  2 +-
>  15 files changed, 135 insertions(+), 43 deletions(-)
>
> -- 
> 2.17.1
>
>
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Re: [v1, 2/6] riscv: smp: fail booting up smp if inconsistent vlen is detected

[Andy Chiu]

On Tue, Mar 12, 2024 at 8:59 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Mar 12, 2024 at 08:36:23PM +0800, Andy Chiu wrote:
> > Currently we only support Vector for SMP platforms, that is, all SMP
> > cores have the same vlenb. If we happen to detect a mismatching vlen, it
> > is better to just fail bootting it up to prevent further race/scheduling
> > issues.
> >
> > Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context")
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
>
> Reported-by: Conor Dooley <conor.dooley@microchip.com>
> Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/
> cc: stable@vger.kernel.org
>
> I actually thought I had sent a patch for this, but I don't seem to
> have. I did write one, so I guess I just did not send it.
>
> > ---
> >  arch/riscv/kernel/head.S    | 14 +++++++-------
> >  arch/riscv/kernel/smpboot.c | 14 +++++++++-----
> >  2 files changed, 16 insertions(+), 12 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index 4236a69c35cb..a158fa9f2656 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -165,9 +165,15 @@ secondary_start_sbi:
> >  #endif
> >       call .Lsetup_trap_vector
> >       scs_load_current
> > -     tail smp_callin
> > +     call smp_callin
> >  #endif /* CONFIG_SMP */
> >
> > +.align 2
> > +.Lsecondary_park:
> > +     /* We lack SMP support or have too many harts, so park this hart */
> > +     wfi
> > +     j .Lsecondary_park
> > +
> >  .align 2
> >  .Lsetup_trap_vector:
> >       /* Set trap vector to exception handler */
> > @@ -181,12 +187,6 @@ secondary_start_sbi:
> >       csrw CSR_SCRATCH, zero
> >       ret
> >
> > -.align 2
> > -.Lsecondary_park:
> > -     /* We lack SMP support or have too many harts, so park this hart */
> > -     wfi
> > -     j .Lsecondary_park
> > -
> >  SYM_CODE_END(_start)
> >
> >  SYM_CODE_START(_start_kernel)
>
> Why does this change? There's no mention of why in the commit message.

Ok, I will add some explanation in the commit message.

This directs the core to secondary_park whenever smp_callin() faills
and returns. So we don't have to re-write the infinity loop in the c
function.

>
> Thanks,
> Conor.

Thanks,
Andy

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Re: [v1, 5/6] riscv: hwprobe: add zve Vector subextesnions into hwprobe interface

[Andy Chiu]

On Tue, Mar 12, 2024 at 8:42 PM Clément Léger <cleger@rivosinc.com> wrote:
>
>
>
> On 12/03/2024 13:36, Andy Chiu wrote:
> > The following Vector subextensions for "embedded" platforms are added
> > into RISCV_HWPROBE_KEY_IMA_EXT_0:
> >  - ZVE32X
> >  - ZVE32F
> >  - ZVE64X
> >  - ZVE64F
> >  - ZVE64D
> >
> > Extensions end with X mean the platform don't have a Vector FPU.
> > Extensions end with F/D mean whether single (F) or double (D) precision
> > Vector operation is supported.
> >
> > The number 32 or 64 follows from ZVE tells the maximum element length.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 15 +++++++++++++++
> >  arch/riscv/include/uapi/asm/hwprobe.h |  5 +++++
> >  arch/riscv/kernel/sys_hwprobe.c       |  5 +++++
> >  3 files changed, 25 insertions(+)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index b2bcc9eed9aa..d0b02e012e5d 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -188,6 +188,21 @@ The following keys are defined:
> >         manual starting from commit 95cf1f9 ("Add changes requested by Ved
> >         during signoff")
> >
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
> > +    supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> > +
> >  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> >    information about the selected set of processors.
> >
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index 9f2a8e3ff204..b9a0876e969f 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -59,6 +59,11 @@ struct riscv_hwprobe {
> >  #define              RISCV_HWPROBE_EXT_ZTSO          (1ULL << 33)
> >  #define              RISCV_HWPROBE_EXT_ZACAS         (1ULL << 34)
> >  #define              RISCV_HWPROBE_EXT_ZICOND        (1ULL << 35)
> > +#define              RISCV_HWPROBE_EXT_ZVE32X        (1ULL << 36)
> > +#define              RISCV_HWPROBE_EXT_ZVE32F        (1ULL << 37)
> > +#define              RISCV_HWPROBE_EXT_ZVE64X        (1ULL << 38)
> > +#define              RISCV_HWPROBE_EXT_ZVE64F        (1ULL << 39)
> > +#define              RISCV_HWPROBE_EXT_ZVE64D        (1ULL << 40)
> >  #define RISCV_HWPROBE_KEY_CPUPERF_0  5
> >  #define              RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
> >  #define              RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index a7c56b41efd2..2500d175ed66 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -111,6 +111,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> >               EXT_KEY(ZTSO);
> >               EXT_KEY(ZACAS);
> >               EXT_KEY(ZICOND);
> > +             EXT_KEY(ZVE32X);
> > +             EXT_KEY(ZVE32F);
> > +             EXT_KEY(ZVE64X);
> > +             EXT_KEY(ZVE64F);
> > +             EXT_KEY(ZVE64D);
>
> Hi Andy,
>
> I'm not sure but since these extensions are conditioned by the fact
> vector should be supported by the kernel, they probably needs to be put
> under the if below:
>
> >
> >               if (has_vector()) {
>
>                         <--- Here --->
> >                       EXT_KEY(ZVBB);

Yes, it makes sense. I will add them under this condition. Combined
with the last patch on this series, it would be something like this in
the end.

if (has_vector(ZVE32X)) {
        <-- Here -->
        EXT_KEY(ZVBB);
}

>
> Thanks !
>
> Clément

Thanks,
Andy

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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Andy Chiu]

On Tue, Mar 12, 2024 at 8:51 PM Clément Léger <cleger@rivosinc.com> wrote:
>
>
>
> On 12/03/2024 13:36, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
>
> Hi Andy,
>
> Nit: Since RISCV_ISA_EXT_ZVE32F is already used here as .id, you don't
> need to insert it in the riscv_zve32f_exts array. It won't hurt but the
> existing extensions that uses the __RISCV_ISA_EXT_SUPERSET() macro don't
> do that.
>

Noted, I will update it in the next revision.

Thanks,
Andy

> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>
> Ditto for the last 3 __RISCV_ISA_EXT_SUPERSET().
>
> Apart from that, it looks good !
>
> Thanks,
>
> Clément
>
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),

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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Samuel Holland]

Hi Andy,

On 2024-03-12 7:36 AM, Andy Chiu wrote:
> Multiple Vector subextensions are added. Also, the patch takes care of
> the dependencies of Vector subextensions by macro expansions. So, if
> some "embedded" platform only reports "zve64f" on the ISA string, the
> parser is able to expand it to zve32x zve32f zve64x and zve64f.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  5 +++++
>  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
>  2 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 5340f818746b..24efea44f1ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -80,6 +80,11 @@
>  #define RISCV_ISA_EXT_ZFA		71
>  #define RISCV_ISA_EXT_ZTSO		72
>  #define RISCV_ISA_EXT_ZACAS		73
> +#define RISCV_ISA_EXT_ZVE32X		74
> +#define RISCV_ISA_EXT_ZVE32F		75
> +#define RISCV_ISA_EXT_ZVE64X		76
> +#define RISCV_ISA_EXT_ZVE64F		77
> +#define RISCV_ISA_EXT_ZVE64D		78
>  
>  #define RISCV_ISA_EXT_MAX		128
>  #define RISCV_ISA_EXT_INVALID		U32_MAX
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8986ceb58188..3aa0df3f3b41 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
>  	RISCV_ISA_EXT_ZVKB
>  };
>  
> +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE32F,		\
> +	RISCV_ISA_EXT_ZVE32X,
> +
> +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64F,		\
> +	RISCV_ISA_EXT_ZVE64X,		\
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +
> +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST	\
> +	RISCV_ISA_EXT_ZVE64D,		\
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +
> +static const unsigned int riscv_zve32f_exts[] = {
> +	RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64f_exts[] = {
> +	RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64d_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
> +static const unsigned int riscv_zve64x_exts[] = {
> +	RISCV_ISA_EXT_ZVE32X,
> +	RISCV_ISA_EXT_ZVE64X
> +};
> +
> +static const unsigned int riscv_v_exts[] = {
> +	RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * chapter 27 of the unprivileged specification.
> @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> -	__RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> +	__RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),

You can use riscv_zve64d_exts here (or #define riscv_v_exts riscv_zve64d_exts)
to avoid allocating a duplicate subextension list.

Regards,
Samuel

>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
>  	__RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
>  	__RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> +	__RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> +	__RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> +	__RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> +	__RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
>  	__RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
>  	__RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
>  	__RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),


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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Andy Chiu]

On Wed, Mar 13, 2024 at 12:01 PM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> Hi Andy,
>
> On 2024-03-12 7:36 AM, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
>
> You can use riscv_zve64d_exts here (or #define riscv_v_exts riscv_zve64d_exts)
> to avoid allocating a duplicate subextension list.

Yes, I should do that, will change that in v2

>
> Regards,
> Samuel
>
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
>

Thanks!
Andy

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Re: [v1, 4/6] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection

[Andy Chiu]

On Tue, Mar 12, 2024 at 9:05 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Tue, Mar 12, 2024 at 08:36:25PM +0800, Andy Chiu wrote:
> > Multiple Vector subextensions are added. Also, the patch takes care of
> > the dependencies of Vector subextensions by macro expansions. So, if
> > some "embedded" platform only reports "zve64f" on the ISA string, the
> > parser is able to expand it to zve32x zve32f zve64x and zve64f.
> >
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
>
> These new extensions need to be added to the dt-bindings.

I am adding a patch for dt-binding after this in v2.

>
> > ---
> >  arch/riscv/include/asm/hwcap.h |  5 +++++
> >  arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++++-
> >  2 files changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 5340f818746b..24efea44f1ab 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -80,6 +80,11 @@
> >  #define RISCV_ISA_EXT_ZFA            71
> >  #define RISCV_ISA_EXT_ZTSO           72
> >  #define RISCV_ISA_EXT_ZACAS          73
> > +#define RISCV_ISA_EXT_ZVE32X         74
> > +#define RISCV_ISA_EXT_ZVE32F         75
> > +#define RISCV_ISA_EXT_ZVE64X         76
> > +#define RISCV_ISA_EXT_ZVE64F         77
> > +#define RISCV_ISA_EXT_ZVE64D         78
> >
> >  #define RISCV_ISA_EXT_MAX            128
> >  #define RISCV_ISA_EXT_INVALID                U32_MAX
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 8986ceb58188..3aa0df3f3b41 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -201,6 +201,40 @@ static const unsigned int riscv_zvbb_exts[] = {
> >       RISCV_ISA_EXT_ZVKB
> >  };
> >
> > +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE32F,           \
> > +     RISCV_ISA_EXT_ZVE32X,
> > +
> > +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64F,           \
> > +     RISCV_ISA_EXT_ZVE64X,           \
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +
> > +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST      \
> > +     RISCV_ISA_EXT_ZVE64D,           \
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +
> > +static const unsigned int riscv_zve32f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64f_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64F_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64d_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> > +static const unsigned int riscv_zve64x_exts[] = {
> > +     RISCV_ISA_EXT_ZVE32X,
> > +     RISCV_ISA_EXT_ZVE64X
> > +};
> > +
> > +static const unsigned int riscv_v_exts[] = {
> > +     RISCV_ISA_EXT_ZVE64D_IMPLY_LIST
> > +};
> > +
> >  /*
> >   * The canonical order of ISA extension names in the ISA string is defined in
> >   * chapter 27 of the unprivileged specification.
> > @@ -248,7 +282,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d),
> >       __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
> >       __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c),
> > -     __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v),
> > +     __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts),
> >       __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
> >       __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> >       __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > @@ -283,6 +317,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> >       __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO),
> >       __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts),
> >       __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC),
> > +     __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts),
> > +     __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts),
> > +     __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts),
> >       __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH),
> >       __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN),
> >       __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB),
> > --
> > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

Thanks!
Andy

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Re: [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[Andy Chiu]

On Tue, Mar 12, 2024 at 9:17 PM Stefan O'Rear <sorear@fastmail.com> wrote:
>
> On Tue, Mar 12, 2024, at 8:36 AM, Andy Chiu wrote:
> > The series composes of two parts. The first part provides a quick fix for
> > the issue on a recent thread[1]. The issue happens when a platform has
> > ununified vector register length across multiple cores. Specifically,
> > patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
> > vlenb is observed by the system. Patch 2 fixes the issue by failing the
> > boot process of a secondary core if vlenb mismatches.
> >
> > The second part of the series provide a finer grain view of the Vector
> > extension. Patch 3 give the obsolete ISA parser the ability to expand
> > ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x,
> > Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5
> > updates all callsites such that Vector subextensions are maximumly
> > supported by the kernel.
>
> What is the end user programming interface for this intended to be? prctl
> call using inline asm ecall in the ifunc resolver, possibly automated using
> function multi-versioning? Can we do better with a different interface?

If a platform supports full V, then the user simply gets it by reading
ELF_HWCAP. ELF_HWCAP has the 'v' bit set when all following conditions
are met:
 1. The single-letter 'v' extension is presented on platform
 2. The kernel has CONFIG_RISCV_ISA_V
 3. The Vector enablement status[1] for the user process is set to
     PR_RISCV_V_VSTATE_CTRL_ON. This is true by default but can be
     changed in Kconfig or the sysctl knob.

If a platform only supports some of Zve* but not V, then ELF_HWCAP
cannot help. The user would end up having to make a prctl call to see
if current's PR_RISCV_V_VSTATE_CTRL_ON is true. I agree we need a
better way for Zve* cases. I am considering if we could duplicate the
information of current vector enablement status from prctl to hwprobe.
Not very sure if this duplication is a good idea though.

[1]: https://www.kernel.org/doc/html/next/riscv/vector.html

Thanks,
Andy





>
> -s
>
> > Two parts of the series are sent together to ease the effort of picking
> > dependency patches. The first part can be merged independent of the
> > second one if necessary.
> >
> > The series is tested on a QEMU and verified that booting, Vector
> > programs context-switch, signal, ptrace, prctl(sysctl knob) interfaces
> > works when we only report partial V from the ISA.
> >
> > This patch should be able to apply on risc-v for-next branch on top of
> > the commit 886516fae2b7 ("RISC-V: fix check for zvkb with tip-of-tree clang")
> >
> > [1]:
> > https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u
> >
> > Andy Chiu (6):
> >   riscv: vector: add a comment when calling riscv_setup_vsize()
> >   riscv: smp: fail booting up smp if inconsistent vlen is detected
> >   riscv: cpufeature: call match_isa_ext() for single-letter extensions
> >   riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
> >   riscv: hwprobe: add zve Vector subextesnions into hwprobe interface
> >   riscv: vector: adjust minimum Vector requirement to ZVE32X
> >
> >  Documentation/arch/riscv/hwprobe.rst   | 15 +++++++
> >  arch/riscv/include/asm/hwcap.h         |  5 +++
> >  arch/riscv/include/asm/switch_to.h     |  2 +-
> >  arch/riscv/include/asm/vector.h        | 21 ++++++----
> >  arch/riscv/include/asm/xor.h           |  2 +-
> >  arch/riscv/include/uapi/asm/hwprobe.h  |  5 +++
> >  arch/riscv/kernel/cpufeature.c         | 57 +++++++++++++++++++++++---
> >  arch/riscv/kernel/head.S               | 14 +++----
> >  arch/riscv/kernel/kernel_mode_vector.c |  4 +-
> >  arch/riscv/kernel/process.c            |  4 +-
> >  arch/riscv/kernel/signal.c             |  6 +--
> >  arch/riscv/kernel/smpboot.c            | 14 ++++---
> >  arch/riscv/kernel/sys_hwprobe.c        | 12 ++++--
> >  arch/riscv/kernel/vector.c             | 15 ++++---
> >  arch/riscv/lib/uaccess.S               |  2 +-
> >  15 files changed, 135 insertions(+), 43 deletions(-)
> >
> > --
> > 2.17.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [v1, 6/6] riscv: vector: adjust minimum Vector requirement to ZVE32X

[Joel Granados]

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On Tue, Mar 12, 2024 at 08:36:27PM +0800, Andy Chiu wrote:
> Make has_vector take one argument. This argument represents the minimum
> Vector subextension that the following Vector actions assume.
> 
> Also, change riscv_v_first_use_handler(), and boot code that calls
> riscv_v_setup_vsize() to accept the minimum Vector sub-extension,
> ZVE32X.
> 
> Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs
> compiled and run with ZVE32X should be supported by the kernel on most
> aspects. This includes context-switch, signal, ptrace, prctl, and
> hwprobe.
> 
> One exception is that ELF_HWCAP returns 'V' only if full V is supported
> on the platform. This means that the system without a full V must not
> rely on ELF_HWCAP to tell whether it is allowable to execute Vector
> without first invoking a prctl() check.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> ---
>  arch/riscv/include/asm/switch_to.h     |  2 +-
>  arch/riscv/include/asm/vector.h        | 21 ++++++++++++++-------
>  arch/riscv/include/asm/xor.h           |  2 +-
>  arch/riscv/kernel/cpufeature.c         |  5 ++++-
>  arch/riscv/kernel/kernel_mode_vector.c |  4 ++--
>  arch/riscv/kernel/process.c            |  4 ++--
>  arch/riscv/kernel/signal.c             |  6 +++---
>  arch/riscv/kernel/smpboot.c            |  2 +-
>  arch/riscv/kernel/sys_hwprobe.c        |  5 +++--
>  arch/riscv/kernel/vector.c             | 15 +++++++++------
>  arch/riscv/lib/uaccess.S               |  2 +-
>  11 files changed, 41 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
> index 7efdb0584d47..df1adf196c4f 100644
> --- a/arch/riscv/include/asm/switch_to.h
> +++ b/arch/riscv/include/asm/switch_to.h
<--- snip --->
>  
>  long riscv_v_vstate_ctrl_get_current(void)
>  {
> -	if (!has_vector())
> +	if (!has_vector(ZVE32X))
>  		return -EINVAL;
>  
>  	return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK;
> @@ -246,7 +249,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg)
>  	bool inherit;
>  	int cur, next;
>  
> -	if (!has_vector())
> +	if (!has_vector(ZVE32X))
>  		return -EINVAL;
>  
>  	if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK)
> @@ -296,7 +299,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = {
>  
>  static int __init riscv_v_sysctl_init(void)
>  {
> -	if (has_vector())
> +	if (has_vector(ZVE32X))
>  		if (!register_sysctl("abi", riscv_v_default_vstate_table))
>  			return -EINVAL;
>  	return 0;
Not really sure why I got this, it probably has to do with this line :)
I don't see any changes that can affect sysctl here.

Acked-by: Joel Granados <j.granados@samsung.com>

> diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
> index bc22c078aba8..bbe143bb32a0 100644
> --- a/arch/riscv/lib/uaccess.S
> +++ b/arch/riscv/lib/uaccess.S
> @@ -14,7 +14,7 @@
>  
>  SYM_FUNC_START(__asm_copy_to_user)
>  #ifdef CONFIG_RISCV_ISA_V
> -	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V)
> +	ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V)
>  	REG_L	t0, riscv_v_usercopy_threshold
>  	bltu	a2, t0, fallback_scalar_usercopy
>  	tail enter_vector_usercopy
> -- 
> 2.17.1
> 

-- 

Joel Granados

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Re: [v1, 0/6] Support Zve32[xf] and Zve64[xfd] Vector subextensions

[Stefan O'Rear]

On Wed, Mar 13, 2024, at 5:15 AM, Andy Chiu wrote:
> On Tue, Mar 12, 2024 at 9:17 PM Stefan O'Rear <sorear@fastmail.com> wrote:
>>
>> On Tue, Mar 12, 2024, at 8:36 AM, Andy Chiu wrote:
>> > The series composes of two parts. The first part provides a quick fix for
>> > the issue on a recent thread[1]. The issue happens when a platform has
>> > ununified vector register length across multiple cores. Specifically,
>> > patch 1 adds a comment at a callsite of riscv_setup_vsize to clarify how
>> > vlenb is observed by the system. Patch 2 fixes the issue by failing the
>> > boot process of a secondary core if vlenb mismatches.
>> >
>> > The second part of the series provide a finer grain view of the Vector
>> > extension. Patch 3 give the obsolete ISA parser the ability to expand
>> > ISA extensions for sigle letter extensions. Patch 3, 4 introduces Zve32x,
>> > Zve32f, Zve64x, Zve64f, Zve64d for isa parsing and hwprobe. Patch 5
>> > updates all callsites such that Vector subextensions are maximumly
>> > supported by the kernel.
>>
>> What is the end user programming interface for this intended to be? prctl
>> call using inline asm ecall in the ifunc resolver, possibly automated using
>> function multi-versioning? Can we do better with a different interface?
>
> If a platform supports full V, then the user simply gets it by reading
> ELF_HWCAP. ELF_HWCAP has the 'v' bit set when all following conditions
> are met:
>  1. The single-letter 'v' extension is presented on platform
>  2. The kernel has CONFIG_RISCV_ISA_V
>  3. The Vector enablement status[1] for the user process is set to
>      PR_RISCV_V_VSTATE_CTRL_ON. This is true by default but can be
>      changed in Kconfig or the sysctl knob.
>
> If a platform only supports some of Zve* but not V, then ELF_HWCAP
> cannot help. The user would end up having to make a prctl call to see
> if current's PR_RISCV_V_VSTATE_CTRL_ON is true. I agree we need a
> better way for Zve* cases. I am considering if we could duplicate the
> information of current vector enablement status from prctl to hwprobe.
> Not very sure if this duplication is a good idea though.

I considered this a while ago, but the vdso hwprobe only has access to
data at the granularity of time namespaces, which aren't relevant for the
prctl. We could use a flag to request process-level information, which
would force a syscall, but it's unclear that's any better than using a
raw prctl syscall.

What would work perfectly is passing the Linux-defined bits in
AT_HWCAP[234], but that seems like a difficult sell at this point.

-s

> [1]: https://www.kernel.org/doc/html/next/riscv/vector.html
>
> Thanks,
> Andy
>
>
>
>
>
>>
>> -s
>>
>> > Two parts of the series are sent together to ease the effort of picking
>> > dependency patches. The first part can be merged independent of the
>> > second one if necessary.
>> >
>> > The series is tested on a QEMU and verified that booting, Vector
>> > programs context-switch, signal, ptrace, prctl(sysctl knob) interfaces
>> > works when we only report partial V from the ISA.
>> >
>> > This patch should be able to apply on risc-v for-next branch on top of
>> > the commit 886516fae2b7 ("RISC-V: fix check for zvkb with tip-of-tree clang")
>> >
>> > [1]:
>> > https://lore.kernel.org/all/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/T/#u
>> >
>> > Andy Chiu (6):
>> >   riscv: vector: add a comment when calling riscv_setup_vsize()
>> >   riscv: smp: fail booting up smp if inconsistent vlen is detected
>> >   riscv: cpufeature: call match_isa_ext() for single-letter extensions
>> >   riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection
>> >   riscv: hwprobe: add zve Vector subextesnions into hwprobe interface
>> >   riscv: vector: adjust minimum Vector requirement to ZVE32X
>> >
>> >  Documentation/arch/riscv/hwprobe.rst   | 15 +++++++
>> >  arch/riscv/include/asm/hwcap.h         |  5 +++
>> >  arch/riscv/include/asm/switch_to.h     |  2 +-
>> >  arch/riscv/include/asm/vector.h        | 21 ++++++----
>> >  arch/riscv/include/asm/xor.h           |  2 +-
>> >  arch/riscv/include/uapi/asm/hwprobe.h  |  5 +++
>> >  arch/riscv/kernel/cpufeature.c         | 57 +++++++++++++++++++++++---
>> >  arch/riscv/kernel/head.S               | 14 +++----
>> >  arch/riscv/kernel/kernel_mode_vector.c |  4 +-
>> >  arch/riscv/kernel/process.c            |  4 +-
>> >  arch/riscv/kernel/signal.c             |  6 +--
>> >  arch/riscv/kernel/smpboot.c            | 14 ++++---
>> >  arch/riscv/kernel/sys_hwprobe.c        | 12 ++++--
>> >  arch/riscv/kernel/vector.c             | 15 ++++---
>> >  arch/riscv/lib/uaccess.S               |  2 +-
>> >  15 files changed, 135 insertions(+), 43 deletions(-)
>> >
>> > --
>> > 2.17.1
>> >
>> >
>> > _______________________________________________
>> > linux-riscv mailing list
>> > linux-riscv@lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-riscv
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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