[PATCH] riscv: Update MIPS vendor id to 0x127.

[PATCH] riscv: Update MIPS vendor id to 0x127.

[Aleksa Paunovic via B4 Relay]

From: Chao-ying Fu <cfu@wavecomp.com>

[1] defines MIPS vendor id as 0x127.

[1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/include/asm/vendorid_list.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -9,6 +9,6 @@
 #define MICROCHIP_VENDOR_ID	0x029
 #define SIFIVE_VENDOR_ID	0x489
 #define THEAD_VENDOR_ID		0x5b7
-#define MIPS_VENDOR_ID		0x722
+#define MIPS_VENDOR_ID		0x127
 
 #endif

---
base-commit: dcb6fa37fd7bc9c3d2b066329b0d27dedf8becaa
change-id: 20251031-mips-vendorid-df103aedf117

Best regards,
-- 
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>



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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Conor Dooley]

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On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
> From: Chao-ying Fu <cfu@wavecomp.com>
> 
> [1] defines MIPS vendor id as 0x127.
> 
> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> 
> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")

Incorrect format for fixes tags!

> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  arch/riscv/include/asm/vendorid_list.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -9,6 +9,6 @@
>  #define MICROCHIP_VENDOR_ID	0x029
>  #define SIFIVE_VENDOR_ID	0x489
>  #define THEAD_VENDOR_ID		0x5b7
> -#define MIPS_VENDOR_ID		0x722
> +#define MIPS_VENDOR_ID		0x127

How was this ever wrong? Do devices exist with this old ID? Do we need
to support both as vendor IDs for MIPS?
Also, this was added in the wrong point in the list (it's meant to be
alphanumeric order IIRC). Sorting by the ID makes things annoying to
humans to read.

>  
>  #endif
> 
> ---
> base-commit: dcb6fa37fd7bc9c3d2b066329b0d27dedf8becaa
> change-id: 20251031-mips-vendorid-df103aedf117
> 
> Best regards,
> -- 
> Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 

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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Aleksa Paunovic]

Hi Conor,


Thank you for your response!


On 11/3/25 23:07, Conor Dooley wrote:

> On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
>> From: Chao-ying Fu <cfu@wavecomp.com>
>>
>> [1] defines MIPS vendor id as 0x127.
>>
>> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
>>
>> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
> Incorrect format for fixes tags!
Will fix that in v2.
>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>>  arch/riscv/include/asm/vendorid_list.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
>> --- a/arch/riscv/include/asm/vendorid_list.h
>> +++ b/arch/riscv/include/asm/vendorid_list.h
>> @@ -9,6 +9,6 @@
>>  #define MICROCHIP_VENDOR_ID	0x029
>>  #define SIFIVE_VENDOR_ID	0x489
>>  #define THEAD_VENDOR_ID		0x5b7
>> -#define MIPS_VENDOR_ID		0x722
>> +#define MIPS_VENDOR_ID		0x127
> How was this ever wrong? Do devices exist with this old ID? Do we need
> to support both as vendor IDs for MIPS?
I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
It shouldn't cause any problems in the future though.
> Also, this was added in the wrong point in the list (it's meant to be
> alphanumeric order IIRC). Sorting by the ID makes things annoying to
> humans to read.
Will fix that as well.


Best regards,

Aleksa

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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1780 bytes --]

On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
> On 11/3/25 23:07, Conor Dooley wrote:
> > On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
> >> From: Chao-ying Fu <cfu@wavecomp.com>
> >>
> >> [1] defines MIPS vendor id as 0x127.
> >>
> >> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> >>
> >> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
> > Incorrect format for fixes tags!
> 
> Will fix that in v2.
> 
> >
> >> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> >> ---
> >>  arch/riscv/include/asm/vendorid_list.h | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> >> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> >> --- a/arch/riscv/include/asm/vendorid_list.h
> >> +++ b/arch/riscv/include/asm/vendorid_list.h
> >> @@ -9,6 +9,6 @@
> >>  #define MICROCHIP_VENDOR_ID	0x029
> >>  #define SIFIVE_VENDOR_ID	0x489
> >>  #define THEAD_VENDOR_ID		0x5b7
> >> -#define MIPS_VENDOR_ID		0x722
> >> +#define MIPS_VENDOR_ID		0x127
> > How was this ever wrong? Do devices exist with this old ID? Do we need
> > to support both as vendor IDs for MIPS?
> 
> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
> It shouldn't cause any problems in the future though.

So all the hardware uses the 0x127 id? Where did 0x722 come from?
I recall qemu defaults to 0x0, so were none of the mips code paths
tested, or were they tested with a qemu modified to use 0x722?

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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Aleksa Paunovic]

On 11/4/25 14:18, Conor Dooley wrote:

> On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
>> On 11/3/25 23:07, Conor Dooley wrote:
>>> On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
>>>> From: Chao-ying Fu <cfu@wavecomp.com>
>>>>
>>>> [1] defines MIPS vendor id as 0x127.
>>>>
>>>> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
>>>>
>>>> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
>>> Incorrect format for fixes tags!
>> Will fix that in v2.
>>
>>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>> ---
>>>>  arch/riscv/include/asm/vendorid_list.h | 2 +-
>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
>>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
>>>> --- a/arch/riscv/include/asm/vendorid_list.h
>>>> +++ b/arch/riscv/include/asm/vendorid_list.h
>>>> @@ -9,6 +9,6 @@
>>>>  #define MICROCHIP_VENDOR_ID	0x029
>>>>  #define SIFIVE_VENDOR_ID	0x489
>>>>  #define THEAD_VENDOR_ID		0x5b7
>>>> -#define MIPS_VENDOR_ID		0x722
>>>> +#define MIPS_VENDOR_ID		0x127
>>> How was this ever wrong? Do devices exist with this old ID? Do we need
>>> to support both as vendor IDs for MIPS?
>> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
>> It shouldn't cause any problems in the future though.
> So all the hardware uses the 0x127 id? Where did 0x722 come from?
> I recall qemu defaults to 0x0, so were none of the mips code paths
> tested, or were they tested with a qemu modified to use 0x722?


That is correct, all hardware uses the 0x127 id. 

I'm not sure where we got 0x722 from - perhaps I or someone else misread the value 

(0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).


Everything was tested with qemu modified to use 0x722. Please see [1], for example.


[1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/


I apologize for the confusion.
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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Conor Dooley]

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On Tue, Nov 04, 2025 at 02:06:31PM +0000, Aleksa Paunovic wrote:
> On 11/4/25 14:18, Conor Dooley wrote:
> 
> > On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
> >> On 11/3/25 23:07, Conor Dooley wrote:
> >>> On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
> >>>> From: Chao-ying Fu <cfu@wavecomp.com>

While I am here, you have a From: header with Chao-ying it it, but the
patch has not been signed off by them.

> >>>>
> >>>> [1] defines MIPS vendor id as 0x127.
> >>>>
> >>>> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> >>>>
> >>>> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
> >>> Incorrect format for fixes tags!
> >> Will fix that in v2.
> >>
> >>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> >>>> ---
> >>>>  arch/riscv/include/asm/vendorid_list.h | 2 +-
> >>>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> >>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> >>>> --- a/arch/riscv/include/asm/vendorid_list.h
> >>>> +++ b/arch/riscv/include/asm/vendorid_list.h
> >>>> @@ -9,6 +9,6 @@
> >>>>  #define MICROCHIP_VENDOR_ID	0x029
> >>>>  #define SIFIVE_VENDOR_ID	0x489
> >>>>  #define THEAD_VENDOR_ID		0x5b7
> >>>> -#define MIPS_VENDOR_ID		0x722
> >>>> +#define MIPS_VENDOR_ID		0x127
> >>> How was this ever wrong? Do devices exist with this old ID? Do we need
> >>> to support both as vendor IDs for MIPS?
> >> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
> >> It shouldn't cause any problems in the future though.
> > So all the hardware uses the 0x127 id? Where did 0x722 come from?
> > I recall qemu defaults to 0x0, so were none of the mips code paths
> > tested, or were they tested with a qemu modified to use 0x722?
> 
> 
> That is correct, all hardware uses the 0x127 id. 
> 
> I'm not sure where we got 0x722 from - perhaps I or someone else misread the value 
> 
> (0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).
> 
> 
> Everything was tested with qemu modified to use 0x722. Please see [1], for example.
> 
> 
> [1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/

Okay, cool. Can you put this information into the commit message? It
should really explain what went wrong and what is impacted by the
change.

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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Aleksa Paunovic]

On 11/4/25 15:09, Conor Dooley wrote:
> On Tue, Nov 04, 2025 at 02:06:31PM +0000, Aleksa Paunovic wrote:
>> On 11/4/25 14:18, Conor Dooley wrote:
>>
>>> On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
>>>> On 11/3/25 23:07, Conor Dooley wrote:
>>>>> On Mon, Nov 03, 2025 at 04:05:48PM +0100, Aleksa Paunovic wrote:
>>>>>> From: Chao-ying Fu <cfu@wavecomp.com>
> While I am here, you have a From: header with Chao-ying it it, but the
> patch has not been signed off by them.
>
>>>>>> [1] defines MIPS vendor id as 0x127.
>>>>>>
>>>>>> [1] https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
>>>>>>
>>>>>> Fixes: a8fed1bc03ace27902338e4f0d318335883ac847 ("riscv: Add xmipsexectl as a vendor extension")
>>>>> Incorrect format for fixes tags!
>>>> Will fix that in v2.
>>>>
>>>>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>>>> ---
>>>>>>  arch/riscv/include/asm/vendorid_list.h | 2 +-
>>>>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
>>>>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
>>>>>> --- a/arch/riscv/include/asm/vendorid_list.h
>>>>>> +++ b/arch/riscv/include/asm/vendorid_list.h
>>>>>> @@ -9,6 +9,6 @@
>>>>>>  #define MICROCHIP_VENDOR_ID	0x029
>>>>>>  #define SIFIVE_VENDOR_ID	0x489
>>>>>>  #define THEAD_VENDOR_ID		0x5b7
>>>>>> -#define MIPS_VENDOR_ID		0x722
>>>>>> +#define MIPS_VENDOR_ID		0x127
>>>>> How was this ever wrong? Do devices exist with this old ID? Do we need
>>>>> to support both as vendor IDs for MIPS?
>>>> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
>>>> It shouldn't cause any problems in the future though.
>>> So all the hardware uses the 0x127 id? Where did 0x722 come from?
>>> I recall qemu defaults to 0x0, so were none of the mips code paths
>>> tested, or were they tested with a qemu modified to use 0x722?
>>
>> That is correct, all hardware uses the 0x127 id. 
>>
>> I'm not sure where we got 0x722 from - perhaps I or someone else misread the value 
>>
>> (0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).
>>
>>
>> Everything was tested with qemu modified to use 0x722. Please see [1], for example.
>>
>>
>> [1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/
> Okay, cool. Can you put this information into the commit message? It
> should really explain what went wrong and what is impacted by the
> change.
Will do. Thanks again! 
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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Paul Walmsley]

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On Tue, 4 Nov 2025, Aleksa Paunovic wrote:

> On 11/4/25 14:18, Conor Dooley wrote:
> 
> > On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
> >
> >>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> >>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
> >>>> --- a/arch/riscv/include/asm/vendorid_list.h
> >>>> +++ b/arch/riscv/include/asm/vendorid_list.h
> >>>> @@ -9,6 +9,6 @@
> >>>>  #define MICROCHIP_VENDOR_ID	0x029
> >>>>  #define SIFIVE_VENDOR_ID	0x489
> >>>>  #define THEAD_VENDOR_ID		0x5b7
> >>>> -#define MIPS_VENDOR_ID		0x722
> >>>> +#define MIPS_VENDOR_ID		0x127
> >>> How was this ever wrong? Do devices exist with this old ID? Do we need
> >>> to support both as vendor IDs for MIPS?
> >> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing. 
> >> It shouldn't cause any problems in the future though.
> > So all the hardware uses the 0x127 id? Where did 0x722 come from?
> > I recall qemu defaults to 0x0, so were none of the mips code paths
> > tested, or were they tested with a qemu modified to use 0x722?
> 
> 
> That is correct, all hardware uses the 0x127 id. 
> 
> I'm not sure where we got 0x722 from - perhaps I or someone else misread the value 
> 
> (0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).
> 
> 
> Everything was tested with qemu modified to use 0x722. Please see [1], for example.
> 
> 
> [1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/

Something that would really help: when you post patches, please 
describe how they were tested.  Something like "Functionality tested on 
MIPS Boston with a P8700 bitstream" or "Boot-tested on upstream QEMU 
vx.y.z" or whatever.  This should go either in the series cover letter or 
below the line in the patch description.  At least then we know if the 
testing was done on something that's likely to resemble the final 
hardware product.

This goes for everyone else on the list, too, by the way.  Some people are 
really good about doing this.  For those of you who have been doing this 
already, please keep up the great work.


- Paul

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Re: [PATCH] riscv: Update MIPS vendor id to 0x127.

[Aleksa Paunovic]

On 11/19/25 04:26, Paul Walmsley wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Tue, 4 Nov 2025, Aleksa Paunovic wrote:
>
>> On 11/4/25 14:18, Conor Dooley wrote:
>>
>>> On Tue, Nov 04, 2025 at 11:53:49AM +0000, Aleksa Paunovic wrote:
>>>
>>>>>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
>>>>>> index 3b09874d7a6dfb8f8aa45b0be41c20711d539e78..55205f7938055ba2b744dba5118bba935bcac008 100644
>>>>>> --- a/arch/riscv/include/asm/vendorid_list.h
>>>>>> +++ b/arch/riscv/include/asm/vendorid_list.h
>>>>>> @@ -9,6 +9,6 @@
>>>>>>  #define MICROCHIP_VENDOR_ID     0x029
>>>>>>  #define SIFIVE_VENDOR_ID        0x489
>>>>>>  #define THEAD_VENDOR_ID         0x5b7
>>>>>> -#define MIPS_VENDOR_ID          0x722
>>>>>> +#define MIPS_VENDOR_ID          0x127
>>>>> How was this ever wrong? Do devices exist with this old ID? Do we need
>>>>> to support both as vendor IDs for MIPS?
>>>> I'm not sure how it first started, but since we worked on qemu as well, we never noticed any issues while testing.
>>>> It shouldn't cause any problems in the future though.
>>> So all the hardware uses the 0x127 id? Where did 0x722 come from?
>>> I recall qemu defaults to 0x0, so were none of the mips code paths
>>> tested, or were they tested with a qemu modified to use 0x722?
>>
>> That is correct, all hardware uses the 0x127 id.
>>
>> I'm not sure where we got 0x722 from - perhaps I or someone else misread the value
>>
>> (0x27 and 0x2 are both mentioned in the Programmer's Guide mvendorid bit descriptions).
>>
>>
>> Everything was tested with qemu modified to use 0x722. Please see [1], for example.
>>
>>
>> [1] https://patchew.org/QEMU/20250717093833.402237-1-djordje.todorovic@htecgroup.com/20250717093833.402237-4-djordje.todorovic@htecgroup.com/
> Something that would really help: when you post patches, please
> describe how they were tested.  Something like "Functionality tested on
> MIPS Boston with a P8700 bitstream" or "Boot-tested on upstream QEMU
> vx.y.z" or whatever.  This should go either in the series cover letter or
> below the line in the patch description.  At least then we know if the
> testing was done on something that's likely to resemble the final
> hardware product.
>
> This goes for everyone else on the list, too, by the way.  Some people are
> really good about doing this.  For those of you who have been doing this
> already, please keep up the great work.

Hi Paul,
 
Thanks a lot for the feedback and clarifications!
 
The kernel does successfully boot on our FPGA even with an incorrect vendor ID 
(0x722 came from an older/legacy source) —
we only noticed the errata issue on the FPGA, and while debugging with printk() we identified what was wrong,
and why with qemu we have not had issues...
 
We’re currently setting up a public CI/CD infrastructure
that will automatically test against both riscv-next and pjw/riscv trees on our FPGA and QEMU. 
Once it’s live, we’ll share the public link so others can follow the results as well.
 
Best regards,
Aleksa
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