[kvm-unit-tests PATCH v2 1/3] s390x/spec_ex: Use PSW macro

[kvm-unit-tests PATCH v2 1/3] s390x/spec_ex: Use PSW macro

[Nina Schoetterl-Glausch]

Replace explicit psw definition by PSW macro.
No functional change intended.

Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index 42ecaed3..2adc5996 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -105,10 +105,7 @@ static int check_invalid_psw(void)
 /* For normal PSWs bit 12 has to be 0 to be a valid PSW*/
 static int psw_bit_12_is_1(void)
 {
-	struct psw invalid = {
-		.mask = BIT(63 - 12),
-		.addr = 0x00000000deadbeee
-	};
+	struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee);
 
 	expect_invalid_psw(invalid);
 	load_psw(invalid);
@@ -118,10 +115,7 @@ static int psw_bit_12_is_1(void)
 /* A short PSW needs to have bit 12 set to be valid. */
 static int short_psw_bit_12_is_0(void)
 {
-	struct psw invalid = {
-		.mask = BIT(63 - 12),
-		.addr = 0x00000000deadbeee
-	};
+	struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee);
 	struct short_psw short_invalid = {
 		.mask = 0x0,
 		.addr = 0xdeadbeee
-- 
2.36.1

[kvm-unit-tests PATCH v2 2/3] s390x/spec_ex: Add test introducing odd address into PSW

[Nina Schoetterl-Glausch]

Instructions on s390 must be halfword aligned.
Introducing an odd instruction address into the PSW leads to a
specification exception when attempting to execute the instruction at
the odd address.
Add a test for this.

Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index 2adc5996..a26c56aa 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw)
 	invalid_psw_expected = true;
 }
 
+static void clear_invalid_psw(void)
+{
+	expected_psw = PSW(0, 0);
+	invalid_psw_expected = false;
+}
+
 static int check_invalid_psw(void)
 {
 	/* Since the fixup sets this to false we check for false here. */
 	if (!invalid_psw_expected) {
+		/*
+		 * Early exception recognition: pgm_int_id == 0.
+		 * Late exception recognition: psw address has been
+		 *	incremented by pgm_int_id (unpredictable value)
+		 */
 		if (expected_psw.mask == invalid_psw.mask &&
-		    expected_psw.addr == invalid_psw.addr)
+		    expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id)
 			return 0;
 		report_fail("Wrong invalid PSW");
 	} else {
@@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void)
 	return check_invalid_psw();
 }
 
+extern char misaligned_code[];
+asm (  ".balign	2\n"
+"	. = . + 1\n"
+"misaligned_code:\n"
+"	larl	%r0,0\n"
+"	bcr	0xf,%r1\n"
+);
+
+static int psw_odd_address(void)
+{
+	struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
+	uint64_t executed_addr;
+
+	expect_invalid_psw(odd);
+	fixup_psw.mask = extract_psw_mask();
+	asm volatile ( "xr	%%r0,%%r0\n"
+		"	larl	%%r1,0f\n"
+		"	stg	%%r1,%[fixup_addr]\n"
+		"	lpswe	%[odd_psw]\n"
+		"0:	lr	%[executed_addr],%%r0\n"
+	: [fixup_addr] "=&T" (fixup_psw.addr),
+	  [executed_addr] "=d" (executed_addr)
+	: [odd_psw] "Q" (odd)
+	: "cc", "%r0", "%r1"
+	);
+
+	if (!executed_addr) {
+		return check_invalid_psw();
+	} else {
+		assert(executed_addr == odd.addr);
+		clear_invalid_psw();
+		report_fail("did not execute unaligned instructions");
+		return 1;
+	}
+}
+
 /* A short PSW needs to have bit 12 set to be valid. */
 static int short_psw_bit_12_is_0(void)
 {
@@ -170,6 +217,7 @@ struct spec_ex_trigger {
 static const struct spec_ex_trigger spec_ex_triggers[] = {
 	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
 	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
+	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
 	{ "bad_alignment", &bad_alignment, true, NULL },
 	{ "not_even", &not_even, true, NULL },
 	{ NULL, NULL, false, NULL },
-- 
2.36.1

[kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Nina Schoetterl-Glausch]

The EXECUTE instruction executes the instruction at the given target
address. This address must be halfword aligned, otherwise a
specification exception occurs.
Add a test for this.

Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
---
 s390x/spec_ex.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
index a26c56aa..dd097f9b 100644
--- a/s390x/spec_ex.c
+++ b/s390x/spec_ex.c
@@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
 	return 0;
 }
 
+static int odd_ex_target(void)
+{
+	uint64_t pre_target_addr;
+	int to = 0, from = 0x0dd;
+
+	asm volatile ( ".pushsection .rodata\n"
+		"pre_odd_ex_target:\n"
+		"	.balign	2\n"
+		"	. = . + 1\n"
+		"	lr	%[to],%[from]\n"
+		"	.popsection\n"
+
+		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
+		"	ex	0,1(%[pre_target_addr])\n"
+		: [pre_target_addr] "=&a" (pre_target_addr),
+		  [to] "+d" (to)
+		: [from] "d" (from)
+	);
+
+	assert((pre_target_addr + 1) & 1);
+	report(to != from, "did not perform ex with odd target");
+	return 0;
+}
+
 static int bad_alignment(void)
 {
 	uint32_t words[5] __attribute__((aligned(16)));
@@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
 	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
 	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
 	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
+	{ "odd_ex_target", &odd_ex_target, true, NULL },
 	{ "bad_alignment", &bad_alignment, true, NULL },
 	{ "not_even", &not_even, true, NULL },
 	{ NULL, NULL, false, NULL },
-- 
2.36.1

Re: [kvm-unit-tests PATCH v2 1/3] s390x/spec_ex: Use PSW macro

[Nina Schoetterl-Glausch]

Messed up the recipients on the cover letter...


Instructions on s390 must be halfword aligned.
Add two tests for that.
These currently fail when using TCG.

v1 -> v2:
 * rebase
 * use PSW macros
 * simplify odd psw test (thanks Claudio)
 * rename some identifiers
 * pick up R-b (thanks Claudio)

Nina Schoetterl-Glausch (3):
  s390x/spec_ex: Use PSW macro
  s390x/spec_ex: Add test introducing odd address into PSW
  s390x/spec_ex: Add test of EXECUTE with odd target address

 s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 76 insertions(+), 9 deletions(-)

Range-diff against v1:
-:  -------- > 1:  d82f4fb6 s390x/spec_ex: Use PSW macro
1:  62f61c07 ! 2:  e537797f s390x/spec_ex: Add test introducing odd address into PSW
    @@ Commit message
         Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
     
      ## s390x/spec_ex.c ##
    -@@ s390x/spec_ex.c: static void fixup_invalid_psw(struct stack_frame_int *stack)
    - /*
    -  * Load possibly invalid psw, but setup fixup_psw before,
    -  * so that fixup_invalid_psw() can bring us back onto the right track.
    -+ * The provided argument is loaded into register 1.
    -  * Also acts as compiler barrier, -> none required in expect/check_invalid_psw
    -  */
    --static void load_psw(struct psw psw)
    -+static void load_psw_with_arg(struct psw psw, uint64_t arg)
    - {
    - 	uint64_t scratch;
    - 
    -@@ s390x/spec_ex.c: static void load_psw(struct psw psw)
    - 	fixup_psw.mask = extract_psw_mask();
    - 	asm volatile ( "larl	%[scratch],0f\n"
    - 		"	stg	%[scratch],%[fixup_addr]\n"
    -+		"	lgr	%%r1,%[arg]\n"
    - 		"	lpswe	%[psw]\n"
    - 		"0:	nop\n"
    - 		: [scratch] "=&d" (scratch),
    - 		  [fixup_addr] "=&T" (fixup_psw.addr)
    --		: [psw] "Q" (psw)
    --		: "cc", "memory"
    -+		: [psw] "Q" (psw),
    -+		  [arg] "d" (arg)
    -+		: "cc", "memory", "%r1"
    - 	);
    - }
    - 
    -+static void load_psw(struct psw psw)
    -+{
    -+	load_psw_with_arg(psw, 0);
    -+}
    -+
    - static void load_short_psw(struct short_psw psw)
    - {
    - 	uint64_t scratch;
     @@ s390x/spec_ex.c: static void expect_invalid_psw(struct psw psw)
      	invalid_psw_expected = true;
      }
      
     +static void clear_invalid_psw(void)
     +{
    -+	expected_psw = (struct psw){0};
    ++	expected_psw = PSW(0, 0);
     +	invalid_psw_expected = false;
     +}
     +
    @@ s390x/spec_ex.c: static void expect_invalid_psw(struct psw psw)
      {
      	/* Since the fixup sets this to false we check for false here. */
      	if (!invalid_psw_expected) {
    ++		/*
    ++		 * Early exception recognition: pgm_int_id == 0.
    ++		 * Late exception recognition: psw address has been
    ++		 *	incremented by pgm_int_id (unpredictable value)
    ++		 */
      		if (expected_psw.mask == invalid_psw.mask &&
     -		    expected_psw.addr == invalid_psw.addr)
     +		    expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id)
    @@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
      	return check_invalid_psw();
      }
      
    ++extern char misaligned_code[];
    ++asm (  ".balign	2\n"
    ++"	. = . + 1\n"
    ++"misaligned_code:\n"
    ++"	larl	%r0,0\n"
    ++"	bcr	0xf,%r1\n"
    ++);
    ++
     +static int psw_odd_address(void)
     +{
    -+	struct psw odd = {
    -+		.mask = extract_psw_mask(),
    -+	};
    -+	uint64_t regs[16];
    -+	int r;
    ++	struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
    ++	uint64_t executed_addr;
     +
    -+	/*
    -+	 * This asm is reentered at an odd address, which should cause a specification
    -+	 * exception before the first unaligned instruction is executed.
    -+	 * In this case, the interrupt handler fixes the address and the test succeeds.
    -+	 * If, however, unaligned instructions *are* executed, they are jumped to
    -+	 * from somewhere, with unknown registers, so save and restore those before.
    -+	 */
    -+	asm volatile ( "stmg	%%r0,%%r15,%[regs]\n"
    -+		//can only offset by even number when using larl -> increment by one
    -+		"	larl	%[r],0f\n"
    -+		"	aghi	%[r],1\n"
    -+		"	stg	%[r],%[addr]\n"
    -+		"	xr	%[r],%[r]\n"
    -+		"	brc	0xf,1f\n"
    -+		"0:	. = . + 1\n"
    -+		"	lmg	%%r0,%%r15,0(%%r1)\n"
    -+		//address of the instruction itself, should be odd, store for assert
    -+		"	larl	%[r],0\n"
    -+		"	stg	%[r],%[addr]\n"
    -+		"	larl	%[r],0f\n"
    -+		"	aghi	%[r],1\n"
    -+		"	bcr	0xf,%[r]\n"
    -+		"0:	. = . + 1\n"
    -+		"1:\n"
    -+	: [addr] "=T" (odd.addr),
    -+	  [regs] "=Q" (regs),
    -+	  [r] "=d" (r)
    -+	: : "cc", "memory"
    ++	expect_invalid_psw(odd);
    ++	fixup_psw.mask = extract_psw_mask();
    ++	asm volatile ( "xr	%%r0,%%r0\n"
    ++		"	larl	%%r1,0f\n"
    ++		"	stg	%%r1,%[fixup_addr]\n"
    ++		"	lpswe	%[odd_psw]\n"
    ++		"0:	lr	%[executed_addr],%%r0\n"
    ++	: [fixup_addr] "=&T" (fixup_psw.addr),
    ++	  [executed_addr] "=d" (executed_addr)
    ++	: [odd_psw] "Q" (odd)
    ++	: "cc", "%r0", "%r1"
     +	);
     +
    -+	if (!r) {
    -+		expect_invalid_psw(odd);
    -+		load_psw_with_arg(odd, (uint64_t)&regs);
    ++	if (!executed_addr) {
     +		return check_invalid_psw();
     +	} else {
    -+		assert(odd.addr & 1);
    ++		assert(executed_addr == odd.addr);
     +		clear_invalid_psw();
    -+		report_fail("executed unaligned instructions");
    ++		report_fail("did not execute unaligned instructions");
     +		return 1;
     +	}
     +}
2:  30075863 ! 3:  dc552880 s390x/spec_ex: Add test of EXECUTE with odd target address
    @@ s390x/spec_ex.c: static int short_psw_bit_12_is_0(void)
      
     +static int odd_ex_target(void)
     +{
    -+	uint64_t target_addr_pre;
    ++	uint64_t pre_target_addr;
     +	int to = 0, from = 0x0dd;
     +
     +	asm volatile ( ".pushsection .rodata\n"
    -+		"odd_ex_target_pre_insn:\n"
    -+		"	.balign 2\n"
    ++		"pre_odd_ex_target:\n"
    ++		"	.balign	2\n"
     +		"	. = . + 1\n"
     +		"	lr	%[to],%[from]\n"
     +		"	.popsection\n"
     +
    -+		"	larl	%[target_addr_pre],odd_ex_target_pre_insn\n"
    -+		"	ex	0,1(%[target_addr_pre])\n"
    -+		: [target_addr_pre] "=&a" (target_addr_pre),
    ++		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
    ++		"	ex	0,1(%[pre_target_addr])\n"
    ++		: [pre_target_addr] "=&a" (pre_target_addr),
     +		  [to] "+d" (to)
     +		: [from] "d" (from)
     +	);
     +
    -+	assert((target_addr_pre + 1) & 1);
    ++	assert((pre_target_addr + 1) & 1);
     +	report(to != from, "did not perform ex with odd target");
     +	return 0;
     +}

base-commit: e3c5c3ef2524c58023073c0fadde2e8ae3c04ec6
-- 
2.36.1

Re: [kvm-unit-tests PATCH v2 1/3] s390x/spec_ex: Use PSW macro

[Janosch Frank]

On 2/21/23 18:48, Nina Schoetterl-Glausch wrote:
> Replace explicit psw definition by PSW macro.
> No functional change intended.
> 
> Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> ---
>   s390x/spec_ex.c | 10 ++--------
>   1 file changed, 2 insertions(+), 8 deletions(-)
> 
> diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> index 42ecaed3..2adc5996 100644
> --- a/s390x/spec_ex.c
> +++ b/s390x/spec_ex.c
> @@ -105,10 +105,7 @@ static int check_invalid_psw(void)
>   /* For normal PSWs bit 12 has to be 0 to be a valid PSW*/
>   static int psw_bit_12_is_1(void)
>   {
> -	struct psw invalid = {
> -		.mask = BIT(63 - 12),
> -		.addr = 0x00000000deadbeee
> -	};
> +	struct psw invalid = PSW(BIT(63 - 12), 0x00000000deadbeee);

I think we've passed the point where we can use a constant for the short 
psw. But we can convert that at a later time, I'll add it to the TODO 
list, so:

Reviewed-by: Janosch Frank <frankja@linux.ibm.com>

Re: [kvm-unit-tests PATCH v2 2/3] s390x/spec_ex: Add test introducing odd address into PSW

[Claudio Imbrenda]

On Tue, 21 Feb 2023 18:48:21 +0100
Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:

> Instructions on s390 must be halfword aligned.
> Introducing an odd instruction address into the PSW leads to a
> specification exception when attempting to execute the instruction at
> the odd address.
> Add a test for this.
> 
> Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> ---
>  s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> index 2adc5996..a26c56aa 100644
> --- a/s390x/spec_ex.c
> +++ b/s390x/spec_ex.c
> @@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw)
>  	invalid_psw_expected = true;
>  }
>  
> +static void clear_invalid_psw(void)
> +{
> +	expected_psw = PSW(0, 0);
> +	invalid_psw_expected = false;
> +}
> +
>  static int check_invalid_psw(void)
>  {
>  	/* Since the fixup sets this to false we check for false here. */
>  	if (!invalid_psw_expected) {
> +		/*
> +		 * Early exception recognition: pgm_int_id == 0.
> +		 * Late exception recognition: psw address has been
> +		 *	incremented by pgm_int_id (unpredictable value)
> +		 */
>  		if (expected_psw.mask == invalid_psw.mask &&
> -		    expected_psw.addr == invalid_psw.addr)
> +		    expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id)
>  			return 0;
>  		report_fail("Wrong invalid PSW");
>  	} else {
> @@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void)
>  	return check_invalid_psw();
>  }
>  
> +extern char misaligned_code[];
> +asm (  ".balign	2\n"

which section will this end up in?

> +"	. = . + 1\n"
> +"misaligned_code:\n"
> +"	larl	%r0,0\n"
> +"	bcr	0xf,%r1\n"

you should just use
        br %r1
it's shorter and easier to understand

> +);
> +
> +static int psw_odd_address(void)
> +{
> +	struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
> +	uint64_t executed_addr;
> +
> +	expect_invalid_psw(odd);
> +	fixup_psw.mask = extract_psw_mask();
> +	asm volatile ( "xr	%%r0,%%r0\n"
> +		"	larl	%%r1,0f\n"
> +		"	stg	%%r1,%[fixup_addr]\n"
> +		"	lpswe	%[odd_psw]\n"
> +		"0:	lr	%[executed_addr],%%r0\n"
> +	: [fixup_addr] "=&T" (fixup_psw.addr),
> +	  [executed_addr] "=d" (executed_addr)
> +	: [odd_psw] "Q" (odd)
> +	: "cc", "%r0", "%r1"
> +	);
> +
> +	if (!executed_addr) {
> +		return check_invalid_psw();
> +	} else {
> +		assert(executed_addr == odd.addr);
> +		clear_invalid_psw();
> +		report_fail("did not execute unaligned instructions");
> +		return 1;
> +	}
> +}
> +
>  /* A short PSW needs to have bit 12 set to be valid. */
>  static int short_psw_bit_12_is_0(void)
>  {
> @@ -170,6 +217,7 @@ struct spec_ex_trigger {
>  static const struct spec_ex_trigger spec_ex_triggers[] = {
>  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
>  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
> +	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
>  	{ "bad_alignment", &bad_alignment, true, NULL },
>  	{ "not_even", &not_even, true, NULL },
>  	{ NULL, NULL, false, NULL },

Re: [kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Claudio Imbrenda]

On Tue, 21 Feb 2023 18:48:22 +0100
Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:

> The EXECUTE instruction executes the instruction at the given target
> address. This address must be halfword aligned, otherwise a
> specification exception occurs.
> Add a test for this.
> 
> Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> ---
>  s390x/spec_ex.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> index a26c56aa..dd097f9b 100644
> --- a/s390x/spec_ex.c
> +++ b/s390x/spec_ex.c
> @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
>  	return 0;
>  }
>  
> +static int odd_ex_target(void)
> +{
> +	uint64_t pre_target_addr;
> +	int to = 0, from = 0x0dd;
> +
> +	asm volatile ( ".pushsection .rodata\n"

and this should go in a .text.something subsection, as we discussed
offline

> +		"pre_odd_ex_target:\n"

shouldn't the label be after the align?

> +		"	.balign	2\n"

(i.e. here)

> +		"	. = . + 1\n"
> +		"	lr	%[to],%[from]\n"
> +		"	.popsection\n"
> +
> +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> +		"	ex	0,1(%[pre_target_addr])\n"
> +		: [pre_target_addr] "=&a" (pre_target_addr),
> +		  [to] "+d" (to)
> +		: [from] "d" (from)
> +	);
> +
> +	assert((pre_target_addr + 1) & 1);
> +	report(to != from, "did not perform ex with odd target");
> +	return 0;
> +}
> +
>  static int bad_alignment(void)
>  {
>  	uint32_t words[5] __attribute__((aligned(16)));
> @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
>  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
>  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
>  	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
> +	{ "odd_ex_target", &odd_ex_target, true, NULL },
>  	{ "bad_alignment", &bad_alignment, true, NULL },
>  	{ "not_even", &not_even, true, NULL },
>  	{ NULL, NULL, false, NULL },

Re: [kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Nina Schoetterl-Glausch]

On Tue, 2023-03-14 at 16:25 +0100, Claudio Imbrenda wrote:
> On Tue, 21 Feb 2023 18:48:22 +0100
> Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:
> 
> > The EXECUTE instruction executes the instruction at the given target
> > address. This address must be halfword aligned, otherwise a
> > specification exception occurs.
> > Add a test for this.
> > 
> > Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> > ---
> >  s390x/spec_ex.c | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> > 
> > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> > index a26c56aa..dd097f9b 100644
> > --- a/s390x/spec_ex.c
> > +++ b/s390x/spec_ex.c
> > @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
> >  	return 0;
> >  }
> >  
> > +static int odd_ex_target(void)
> > +{
> > +	uint64_t pre_target_addr;
> > +	int to = 0, from = 0x0dd;
> > +
> > +	asm volatile ( ".pushsection .rodata\n"
> 
> and this should go in a .text.something subsection, as we discussed
> offline

Yes.
> 
> > +		"pre_odd_ex_target:\n"
> 
> shouldn't the label be after the align?

No, larl needs an aligned address, and the ex below adds 1.
That's why it has the pre_ prefix, it's not the ex target itself.
> 
> > +		"	.balign	2\n"
> 
> (i.e. here)
> 
> > +		"	. = . + 1\n"
> > +		"	lr	%[to],%[from]\n"
> > +		"	.popsection\n"
> > +
> > +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> > +		"	ex	0,1(%[pre_target_addr])\n"
> > +		: [pre_target_addr] "=&a" (pre_target_addr),
> > +		  [to] "+d" (to)
> > +		: [from] "d" (from)
> > +	);
> > +
> > +	assert((pre_target_addr + 1) & 1);
> > +	report(to != from, "did not perform ex with odd target");
> > +	return 0;
> > +}
> > +
> >  static int bad_alignment(void)
> >  {
> >  	uint32_t words[5] __attribute__((aligned(16)));
> > @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
> >  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
> >  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
> >  	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
> > +	{ "odd_ex_target", &odd_ex_target, true, NULL },
> >  	{ "bad_alignment", &bad_alignment, true, NULL },
> >  	{ "not_even", &not_even, true, NULL },
> >  	{ NULL, NULL, false, NULL },
> 

Re: [kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Claudio Imbrenda]

On Tue, 14 Mar 2023 17:41:24 +0100
Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:

> On Tue, 2023-03-14 at 16:25 +0100, Claudio Imbrenda wrote:
> > On Tue, 21 Feb 2023 18:48:22 +0100
> > Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:
> >   
> > > The EXECUTE instruction executes the instruction at the given target
> > > address. This address must be halfword aligned, otherwise a
> > > specification exception occurs.
> > > Add a test for this.
> > > 
> > > Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> > > ---
> > >  s390x/spec_ex.c | 25 +++++++++++++++++++++++++
> > >  1 file changed, 25 insertions(+)
> > > 
> > > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> > > index a26c56aa..dd097f9b 100644
> > > --- a/s390x/spec_ex.c
> > > +++ b/s390x/spec_ex.c
> > > @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
> > >  	return 0;
> > >  }
> > >  
> > > +static int odd_ex_target(void)
> > > +{
> > > +	uint64_t pre_target_addr;
> > > +	int to = 0, from = 0x0dd;
> > > +
> > > +	asm volatile ( ".pushsection .rodata\n"  
> > 
> > and this should go in a .text.something subsection, as we discussed
> > offline  
> 
> Yes.
> >   
> > > +		"pre_odd_ex_target:\n"  
> > 
> > shouldn't the label be after the align?  
> 
> No, larl needs an aligned address, and the ex below adds 1.
> That's why it has the pre_ prefix, it's not the ex target itself.

I understand that, but 
> >   
> > > +		"	.balign	2\n"  

doesn't the address get aligned here?
so the label here would be aligned to 2

> > 
> > (i.e. here)
> >   
> > > +		"	. = . + 1\n"

and here it gets the +1?

> > > +		"	lr	%[to],%[from]\n"
> > > +		"	.popsection\n"
> > > +
> > > +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> > > +		"	ex	0,1(%[pre_target_addr])\n"
> > > +		: [pre_target_addr] "=&a" (pre_target_addr),
> > > +		  [to] "+d" (to)
> > > +		: [from] "d" (from)
> > > +	);
> > > +
> > > +	assert((pre_target_addr + 1) & 1);
> > > +	report(to != from, "did not perform ex with odd target");
> > > +	return 0;
> > > +}
> > > +
> > >  static int bad_alignment(void)
> > >  {
> > >  	uint32_t words[5] __attribute__((aligned(16)));
> > > @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
> > >  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
> > >  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
> > >  	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
> > > +	{ "odd_ex_target", &odd_ex_target, true, NULL },
> > >  	{ "bad_alignment", &bad_alignment, true, NULL },
> > >  	{ "not_even", &not_even, true, NULL },
> > >  	{ NULL, NULL, false, NULL },  
> >   
> 

Re: [kvm-unit-tests PATCH v2 3/3] s390x/spec_ex: Add test of EXECUTE with odd target address

[Nina Schoetterl-Glausch]

On Tue, 2023-03-14 at 18:12 +0100, Claudio Imbrenda wrote:
> On Tue, 14 Mar 2023 17:41:24 +0100
> Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:
> 
> > On Tue, 2023-03-14 at 16:25 +0100, Claudio Imbrenda wrote:
> > > On Tue, 21 Feb 2023 18:48:22 +0100
> > > Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:
> > >   
> > > > The EXECUTE instruction executes the instruction at the given target
> > > > address. This address must be halfword aligned, otherwise a
> > > > specification exception occurs.
> > > > Add a test for this.
> > > > 
> > > > Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> > > > ---
> > > >  s390x/spec_ex.c | 25 +++++++++++++++++++++++++
> > > >  1 file changed, 25 insertions(+)
> > > > 
> > > > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> > > > index a26c56aa..dd097f9b 100644
> > > > --- a/s390x/spec_ex.c
> > > > +++ b/s390x/spec_ex.c
> > > > @@ -177,6 +177,30 @@ static int short_psw_bit_12_is_0(void)
> > > >  	return 0;
> > > >  }
> > > >  
> > > > +static int odd_ex_target(void)
> > > > +{
> > > > +	uint64_t pre_target_addr;
> > > > +	int to = 0, from = 0x0dd;
> > > > +
> > > > +	asm volatile ( ".pushsection .rodata\n"  
> > > 
> > > and this should go in a .text.something subsection, as we discussed
> > > offline  
> > 
> > Yes.
> > >   
> > > > +		"pre_odd_ex_target:\n"  
> > > 
> > > shouldn't the label be after the align?  
> > 
> > No, larl needs an aligned address, and the ex below adds 1.
> > That's why it has the pre_ prefix, it's not the ex target itself.
> 
> I understand that, but 
> > >   
> > > > +		"	.balign	2\n"  
> 
> doesn't the address get aligned here?
> so the label here would be aligned to 2

Uh, yeah, sorry.
> 
> > > 
> > > (i.e. here)
> > >   
> > > > +		"	. = . + 1\n"
> 
> and here it gets the +1?
> 
> > > > +		"	lr	%[to],%[from]\n"
> > > > +		"	.popsection\n"
> > > > +
> > > > +		"	larl	%[pre_target_addr],pre_odd_ex_target\n"
> > > > +		"	ex	0,1(%[pre_target_addr])\n"
> > > > +		: [pre_target_addr] "=&a" (pre_target_addr),
> > > > +		  [to] "+d" (to)
> > > > +		: [from] "d" (from)
> > > > +	);
> > > > +
> > > > +	assert((pre_target_addr + 1) & 1);
> > > > +	report(to != from, "did not perform ex with odd target");
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  static int bad_alignment(void)
> > > >  {
> > > >  	uint32_t words[5] __attribute__((aligned(16)));
> > > > @@ -218,6 +242,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = {
> > > >  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
> > > >  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
> > > >  	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
> > > > +	{ "odd_ex_target", &odd_ex_target, true, NULL },
> > > >  	{ "bad_alignment", &bad_alignment, true, NULL },
> > > >  	{ "not_even", &not_even, true, NULL },
> > > >  	{ NULL, NULL, false, NULL },  
> > >   
> > 
> 

Re: [kvm-unit-tests PATCH v2 2/3] s390x/spec_ex: Add test introducing odd address into PSW

[Nina Schoetterl-Glausch]

On Tue, 2023-03-14 at 16:21 +0100, Claudio Imbrenda wrote:
> On Tue, 21 Feb 2023 18:48:21 +0100
> Nina Schoetterl-Glausch <nsg@linux.ibm.com> wrote:
> 
> > Instructions on s390 must be halfword aligned.
> > Introducing an odd instruction address into the PSW leads to a
> > specification exception when attempting to execute the instruction at
> > the odd address.
> > Add a test for this.
> > 
> > Signed-off-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
> > ---
> >  s390x/spec_ex.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 49 insertions(+), 1 deletion(-)
> > 
> > diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c
> > index 2adc5996..a26c56aa 100644
> > --- a/s390x/spec_ex.c
> > +++ b/s390x/spec_ex.c
> > @@ -88,12 +88,23 @@ static void expect_invalid_psw(struct psw psw)
> >  	invalid_psw_expected = true;
> >  }
> >  
> > +static void clear_invalid_psw(void)
> > +{
> > +	expected_psw = PSW(0, 0);
> > +	invalid_psw_expected = false;
> > +}
> > +
> >  static int check_invalid_psw(void)
> >  {
> >  	/* Since the fixup sets this to false we check for false here. */
> >  	if (!invalid_psw_expected) {
> > +		/*
> > +		 * Early exception recognition: pgm_int_id == 0.
> > +		 * Late exception recognition: psw address has been
> > +		 *	incremented by pgm_int_id (unpredictable value)
> > +		 */
> >  		if (expected_psw.mask == invalid_psw.mask &&
> > -		    expected_psw.addr == invalid_psw.addr)
> > +		    expected_psw.addr == invalid_psw.addr - lowcore.pgm_int_id)
> >  			return 0;
> >  		report_fail("Wrong invalid PSW");
> >  	} else {
> > @@ -112,6 +123,42 @@ static int psw_bit_12_is_1(void)
> >  	return check_invalid_psw();
> >  }
> >  
> > +extern char misaligned_code[];
> > +asm (  ".balign	2\n"
> 
> which section will this end up in?

.text
> 
> > +"	. = . + 1\n"
> > +"misaligned_code:\n"
> > +"	larl	%r0,0\n"
> > +"	bcr	0xf,%r1\n"
> 
> you should just use
>         br %r1
> it's shorter and easier to understand

Yes.
> 
> > +);
> > +
> > +static int psw_odd_address(void)
> > +{
> > +	struct psw odd = PSW_WITH_CUR_MASK((uint64_t)&misaligned_code);
> > +	uint64_t executed_addr;
> > +
> > +	expect_invalid_psw(odd);
> > +	fixup_psw.mask = extract_psw_mask();
> > +	asm volatile ( "xr	%%r0,%%r0\n"
> > +		"	larl	%%r1,0f\n"
> > +		"	stg	%%r1,%[fixup_addr]\n"
> > +		"	lpswe	%[odd_psw]\n"
> > +		"0:	lr	%[executed_addr],%%r0\n"
> > +	: [fixup_addr] "=&T" (fixup_psw.addr),
> > +	  [executed_addr] "=d" (executed_addr)
> > +	: [odd_psw] "Q" (odd)
> > +	: "cc", "%r0", "%r1"
> > +	);
> > +
> > +	if (!executed_addr) {
> > +		return check_invalid_psw();
> > +	} else {
> > +		assert(executed_addr == odd.addr);
> > +		clear_invalid_psw();
> > +		report_fail("did not execute unaligned instructions");
> > +		return 1;
> > +	}
> > +}
> > +
> >  /* A short PSW needs to have bit 12 set to be valid. */
> >  static int short_psw_bit_12_is_0(void)
> >  {
> > @@ -170,6 +217,7 @@ struct spec_ex_trigger {
> >  static const struct spec_ex_trigger spec_ex_triggers[] = {
> >  	{ "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw },
> >  	{ "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw },
> > +	{ "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw },
> >  	{ "bad_alignment", &bad_alignment, true, NULL },
> >  	{ "not_even", &not_even, true, NULL },
> >  	{ NULL, NULL, false, NULL },
>