ARM Sunxi Platform Development
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From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>,
	Mikhail Kalashnikov <iuncuim@gmail.com>,
	Yixun Lan <dlan@gentoo.org>,
	Paul Kocialkowski <paulk@sys-base.io>,
	linux-sunxi@lists.linux.dev, Tom Rini <trini@konsulko.com>
Subject: [PATCH v2 03/20] sunxi: clock: H6: factor out H6/H616 CPU clock setup
Date: Fri, 18 Jul 2025 00:54:38 +0100	[thread overview]
Message-ID: <20250717235455.32528-4-andre.przywara@arm.com> (raw)
In-Reply-To: <20250717235455.32528-1-andre.przywara@arm.com>

When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.

The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/mach-sunxi/clock_sun50i_h6.c | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index 90436b45b40..84064c4ed86 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -120,29 +120,37 @@ static void clock_set_pll(u32 *reg, unsigned int n)
 	}
 }
 
-void clock_set_pll1(unsigned int clk)
+static void clock_h6_set_cpu_pll(unsigned int n_factor)
 {
 	void *const ccm = (void *)SUNXI_CCM_BASE;
 	u32 val;
 
-	/* Do not support clocks < 288MHz as they need factor P */
-	if (clk < 288000000) clk = 288000000;
-
-	/* Switch to 24MHz clock while changing PLL1 */
+	/* Switch CPU clock source to 24MHz HOSC while changing the PLL */
 	val = readl(ccm + CCU_H6_CPU_AXI_CFG);
 	val &= ~CCM_CPU_AXI_MUX_MASK;
 	val |= CCM_CPU_AXI_MUX_OSC24M;
 	writel(val, ccm + CCU_H6_CPU_AXI_CFG);
 
-	clock_set_pll(ccm + CCU_H6_PLL1_CFG, clk / 24000000);
+	clock_set_pll(ccm + CCU_H6_PLL1_CFG, n_factor);
 
-	/* Switch CPU to PLL1 */
+	/* Switch CPU clock source to the CPU PLL */
 	val = readl(ccm + CCU_H6_CPU_AXI_CFG);
 	val &= ~CCM_CPU_AXI_MUX_MASK;
 	val |= CCM_CPU_AXI_MUX_PLL_CPUX;
 	writel(val, ccm + CCU_H6_CPU_AXI_CFG);
 }
 
+void clock_set_pll1(unsigned int clk)
+{
+	/* Do not support clocks < 288MHz as they need factor P */
+	if (clk < 288000000)
+		clk = 288000000;
+
+	clk /= 24000000;
+
+	clock_h6_set_cpu_pll(clk);
+}
+
 int clock_twi_onoff(int port, int state)
 {
 	void *const ccm = (void *)SUNXI_CCM_BASE;
-- 
2.46.3


  parent reply	other threads:[~2025-07-17 23:56 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-17 23:54 [PATCH v2 00/20] sunxi: Add Allwinner A523 support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 01/20] sunxi: clock: H6: unify PLL control bit definitions Andre Przywara
2025-07-17 23:54 ` [PATCH v2 02/20] sunxi: clock: H6: factor out clock_set_pll() Andre Przywara
2025-07-17 23:54 ` Andre Przywara [this message]
2025-07-17 23:54 ` [PATCH v2 04/20] sunxi: clock: H6: add A523 CPU PLL support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 05/20] sunxi: spl: add support for Allwinner A523 watchdog Andre Przywara
2025-07-17 23:54 ` [PATCH v2 06/20] clk: sunxi: Add support for the A523 CCU Andre Przywara
2025-07-17 23:54 ` [PATCH v2 07/20] clk: sunxi: Add support for the A523 -R CCU Andre Przywara
2025-07-17 23:54 ` [PATCH v2 08/20] pinctrl: sunxi: add Allwinner A523 pinctrl description Andre Przywara
2025-07-17 23:54 ` [PATCH v2 09/20] sunxi: mmc: add support for Allwinner A523 MMC mod clock Andre Przywara
2025-07-22  0:32   ` Andre Przywara
2025-07-17 23:54 ` [PATCH v2 10/20] power: regulator: add AXP323 support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 11/20] sunxi: update cpu_sunxi_ncat2.h Andre Przywara
2025-07-17 23:54 ` [PATCH v2 12/20] sunxi: sun50i_h6: add A523 SPL clock setup code Andre Przywara
2025-07-22  0:14   ` Andre Przywara
2025-07-27 20:15   ` Jernej Škrabec
2025-07-17 23:54 ` [PATCH v2 13/20] sunxi: A523: add DRAM initialisation routine Andre Przywara
2025-07-27 20:16   ` Jernej Škrabec
2025-07-17 23:54 ` [PATCH v2 14/20] sunxi: A523: add DDR3 DRAM support Andre Przywara
2025-07-25  4:44   ` Mikhail Kalashnikov
2025-07-25 23:48   ` Andre Przywara
2025-07-26  0:04   ` [PATCH] FIXUP! a523: DDR3: rework Andre Przywara
2025-07-17 23:54 ` [PATCH v2 15/20] sunxi: add basic A523 support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 16/20] arm64: dts: allwinner: Add Allwinner A523 .dtsi file Andre Przywara
2025-07-17 23:54 ` [PATCH v2 17/20] arm64: dts: allwinner: a523: add X96Q-Pro+ support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 18/20] arm64: dts: allwinner: a523: add Radxa A5E support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 19/20] arm64: dts: allwinner: a523: add Avaota-A1 router support Andre Przywara
2025-07-17 23:54 ` [PATCH v2 20/20] sunxi: A523: add defconfigs for three boards Andre Przywara
2025-07-22  0:35   ` Andre Przywara
2025-07-22  2:49     ` Yixun Lan
2025-07-22 10:30       ` Andre Przywara
2025-07-19  2:05 ` [PATCH v2 00/20] sunxi: Add Allwinner A523 support Yixun Lan

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