Re: [PATCH v2 09/20] sunxi: mmc: add support for Allwinner A523 MMC mod clock

[Andre Przywara <andre.przywara@arm.com>]

On Fri, 18 Jul 2025 00:54:44 +0100
Andre Przywara <andre.przywara@arm.com> wrote:

> The Allwinner A523 SoC has a slightly changed mod clock, where the P
> factor, formerly a shift value, is now a second divider value.
> Also the input clock is not PLL_PERIPH0_2X (1200MHz) anymore, but
> PLL_PERIPH0_400M, so adjust the input rate calculation accordingly.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/mmc/sunxi_mmc.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 06c1e09bf26..7c85030be16 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -99,6 +99,15 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
>  		 */
>  		if (IS_ENABLED(CONFIG_MACH_SUN8I_R528))
>  			pll_hz /= 2;
> +
> +		/*
> +		 * The A523/T527 uses PERIPH0_400M as the MMC input clock,
> +		 * which is the PERIPH0 nominal rate (1200MHz) / 3.

As Yixun figured correctly, a recent patch fixed the PLL PERIPH0 clock
calculation for NCAT2 chips, so the routine reports 600 MHz, to stay
compatible with older SoCs. So the divider here must be 3, really, not
6.
But this is only half the truth, since for MMC2 the base clock is
PLL_PERIPH0_800M, so we must multiply this by 2 again afterwards, to
reach the proper eMMC frequency.

Fixed in my tree.

Cheers,
Andre

> +		 * Together with the fixed post-divider of 2 of the MMC mod
> +		 * clock, that gives a divider of 6.
> +		 */
> +		if (IS_ENABLED(CONFIG_MACH_SUN55I_A523))
> +			pll_hz /= 6;
>  	}
>  
>  	div = pll_hz / hz;
> @@ -153,6 +162,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
>  			CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
>  	}
>  
> +	/* The A523 has a second divider, not a shift. */
> +	if (IS_ENABLED(CONFIG_MACH_SUN55I_A523))
> +		n = (1U << n) - 1;
> +
>  	writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
>  	       CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
>  
> @@ -559,7 +572,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
>  	cfg->host_caps = MMC_MODE_4BIT;
>  
>  	if ((IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN8I) ||
> -	    IS_ENABLED(CONFIG_SUN50I_GEN_H6)) && (sdc_no == 2))
> +	    IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_MACH_SUN55I_A523)) &&
> +	    (sdc_no == 2))
>  		cfg->host_caps = MMC_MODE_8BIT;
>  
>  	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;