[PATCH v4 00/12] Tegra114: implement EMC support

[PATCH v4 00/12] Tegra114: implement EMC support

[Svyatoslav Ryhel]

Add support for External Memory Controller found in Tegra 4 SoC along
with adjustments required for it to work properly.

Tested on ASUS TF701T (T40X) and Nvidia Tegratab (T40S). Both work fine.

---
Changes in v2:
- fix programming completion detection (changed EMC reg to MC reg reading)
- Tegra114 incorporated into Tegra124 dt-bindings schema

Changes in v3:
- adjusted MC and EMC schema to move description and ref into common property
- added Tegra114 support into devfreq driver
- added MC/EMC to DC interconnections

Changes in v4:
- fix number of EMC clocks required by activity counter transaction
- set minItems/maxItems for MC and EMC registers
- removed CONFIG_TEGRA124_CLK_EMC ifdefs from clk-tegra114
- minimized changes to tegra114_clock_init
- switch to devm_tegra_core_dev_init_opp_table
- switch to readl_poll_timeout_atomic for polling
- adjust DLL_CHANGE logic
- drop touching EMC_CLKCHANGE_SR_ENABLE
- use for_each_child_of_node_scoped for timing iteration
- add emc-mc timing check
- added print for amount of timings and ramcode
- align commit and code style
---

Svyatoslav Ryhel (12):
  devfreq: tegra30-devfreq: add support for Tegra114
  ARM: tegra: Add ACTMON node to Tegra114 device tree
  dt-bindings: memory: Document Tegra114 Memory Controller
  memory: tegra: implement EMEM regs and ICC ops for Tegra114
  dt-bindings: memory: Add Tegra114 memory client IDs
  clk: tegra: set up proper EMC clock implementation for Tegra114
  dt-bindings: memory: Document Tegra114 External Memory Controller
  soc: tegra: common: add Tegra114 support to
    devm_tegra_core_dev_init_opp_table
  memory: tegra: Add Tegra114 EMC driver
  ARM: tegra: Add External Memory Controller node on Tegra114
  ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON
    device-tree nodes
  ARM: tegra: add DC interconnections for Tegra114

 .../nvidia,tegra124-emc.yaml                  |  174 +-
 .../nvidia,tegra124-mc.yaml                   |   31 +-
 .../dts/nvidia/tegra114-peripherals-opp.dtsi  |  151 ++
 arch/arm/boot/dts/nvidia/tegra114.dtsi        |   55 +
 drivers/clk/tegra/clk-tegra114.c              |   39 +-
 drivers/devfreq/tegra30-devfreq.c             |   17 +-
 drivers/memory/tegra/Kconfig                  |   12 +
 drivers/memory/tegra/Makefile                 |    1 +
 drivers/memory/tegra/tegra114-emc.c           | 1463 +++++++++++++++++
 drivers/memory/tegra/tegra114.c               |  193 +++
 drivers/soc/tegra/common.c                    |    5 +-
 include/dt-bindings/memory/tegra114-mc.h      |   67 +
 12 files changed, 2016 insertions(+), 192 deletions(-)
 create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
 create mode 100644 drivers/memory/tegra/tegra114-emc.c

-- 
2.51.0

[PATCH v4 01/12] devfreq: tegra30-devfreq: add support for Tegra114

[Svyatoslav Ryhel]

Lets add Tegra114 support to activity monitor device as a preparation to
upcoming EMC controller support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/devfreq/tegra30-devfreq.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
index 8ea5b482bfb3..fa83480a923f 100644
--- a/drivers/devfreq/tegra30-devfreq.c
+++ b/drivers/devfreq/tegra30-devfreq.c
@@ -963,16 +963,22 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
 	return 0;
 }
 
+/*
+ * The activity counter is incremented every 256 memory transactions. However,
+ * the number of clock cycles required for each transaction varies across
+ * different SoC generations. For instance, a single transaction takes 2 EMC
+ * clocks on Tegra30, 1 EMC clock on Tegra114, and 4 EMC clocks on Tegra124.
+ */
 static const struct tegra_devfreq_soc_data tegra124_soc = {
 	.configs = tegra124_device_configs,
-
-	/*
-	 * Activity counter is incremented every 256 memory transactions,
-	 * and each transaction takes 4 EMC clocks.
-	 */
 	.count_weight = 4 * 256,
 };
 
+static const struct tegra_devfreq_soc_data tegra114_soc = {
+	.configs = tegra124_device_configs,
+	.count_weight = 256,
+};
+
 static const struct tegra_devfreq_soc_data tegra30_soc = {
 	.configs = tegra30_device_configs,
 	.count_weight = 2 * 256,
@@ -980,6 +986,7 @@ static const struct tegra_devfreq_soc_data tegra30_soc = {
 
 static const struct of_device_id tegra_devfreq_of_match[] = {
 	{ .compatible = "nvidia,tegra30-actmon",  .data = &tegra30_soc, },
+	{ .compatible = "nvidia,tegra114-actmon", .data = &tegra114_soc, },
 	{ .compatible = "nvidia,tegra124-actmon", .data = &tegra124_soc, },
 	{ },
 };
-- 
2.51.0

[PATCH v4 02/12] ARM: tegra: Add ACTMON node to Tegra114 device tree

[Svyatoslav Ryhel]

Add support for ACTMON on Tegra114. This is used to monitor activity from
different components. Based on the collected statistics, the rate at which
the external memory needs to be clocked can be derived.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 arch/arm/boot/dts/nvidia/tegra114.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 02d2c40dd79a..ef0618e9eec1 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -312,6 +312,18 @@ ahb: ahb@6000c000 {
 		reg = <0x6000c000 0x150>;
 	};
 
+	actmon: actmon@6000c800 {
+		compatible = "nvidia,tegra114-actmon";
+		reg = <0x6000c800 0x400>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_ACTMON>,
+			 <&tegra_car TEGRA114_CLK_EMC>;
+		clock-names = "actmon", "emc";
+		resets = <&tegra_car TEGRA114_CLK_ACTMON>;
+		reset-names = "actmon";
+		#cooling-cells = <2>;
+	};
+
 	gpio: gpio@6000d000 {
 		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 		reg = <0x6000d000 0x1000>;
-- 
2.51.0

[PATCH v4 03/12] dt-bindings: memory: Document Tegra114 Memory Controller

[Svyatoslav Ryhel]

Add Tegra114 support into existing Tegra124 MC schema with the most
notable difference in the amount of EMEM timings.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 .../nvidia,tegra124-mc.yaml                   | 31 +++++--------------
 1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
index 7b18b4d11e0a..f8747cebb680 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml
@@ -19,7 +19,9 @@ description: |
 
 properties:
   compatible:
-    const: nvidia,tegra124-mc
+    enum:
+      - nvidia,tegra114-mc
+      - nvidia,tegra124-mc
 
   reg:
     maxItems: 1
@@ -64,29 +66,12 @@ patternProperties:
 
           nvidia,emem-configuration:
             $ref: /schemas/types.yaml#/definitions/uint32-array
-            description: |
+            description:
               Values to be written to the EMEM register block. See section
-              "15.6.1 MC Registers" in the TRM.
-            items:
-              - description: MC_EMEM_ARB_CFG
-              - description: MC_EMEM_ARB_OUTSTANDING_REQ
-              - description: MC_EMEM_ARB_TIMING_RCD
-              - description: MC_EMEM_ARB_TIMING_RP
-              - description: MC_EMEM_ARB_TIMING_RC
-              - description: MC_EMEM_ARB_TIMING_RAS
-              - description: MC_EMEM_ARB_TIMING_FAW
-              - description: MC_EMEM_ARB_TIMING_RRD
-              - description: MC_EMEM_ARB_TIMING_RAP2PRE
-              - description: MC_EMEM_ARB_TIMING_WAP2PRE
-              - description: MC_EMEM_ARB_TIMING_R2R
-              - description: MC_EMEM_ARB_TIMING_W2W
-              - description: MC_EMEM_ARB_TIMING_R2W
-              - description: MC_EMEM_ARB_TIMING_W2R
-              - description: MC_EMEM_ARB_DA_TURNS
-              - description: MC_EMEM_ARB_DA_COVERS
-              - description: MC_EMEM_ARB_MISC0
-              - description: MC_EMEM_ARB_MISC1
-              - description: MC_EMEM_ARB_RING1_THROTTLE
+              "20.11.1 MC Registers" in the Tegea114 TRM or
+              "15.6.1 MC Registers" in the Tegra124 TRM.
+            minItems: 18
+            maxItems: 19
 
         required:
           - clock-frequency
-- 
2.51.0

[PATCH v4 04/12] memory: tegra: implement EMEM regs and ICC ops for Tegra114

[Svyatoslav Ryhel]

Prepare Internal Memory Controller for introduction of External Memory
Controller.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/memory/tegra/tegra114.c | 193 ++++++++++++++++++++++++++++++++
 1 file changed, 193 insertions(+)

diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index d03a5d162dbd..c615857f7fad 100644
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
  */
 
+#include <linux/device.h>
 #include <linux/of.h>
 #include <linux/mm.h>
 
@@ -1165,6 +1166,195 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {
 	TEGRA114_MC_RESET(VI,       0x200, 0x204, 17),
 };
 
+static void tegra114_mc_tune_client_latency(struct tegra_mc *mc,
+					    const struct tegra_mc_client *client,
+					    unsigned int bandwidth_mbytes_sec)
+{
+	u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
+	unsigned int fifo_size = client->fifo_size;
+	u32 arb_nsec, la_ticks, value;
+
+	/* see 20.3.1.1 Client Configuration in Tegra4 TRM v01p */
+	if (bandwidth_mbytes_sec)
+		arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;
+	else
+		arb_nsec = U32_MAX;
+
+	/*
+	 * Latency allowness should be set with consideration for the module's
+	 * latency tolerance and internal buffering capabilities.
+	 *
+	 * Display memory clients use isochronous transfers and have very low
+	 * tolerance to a belated transfers. Hence we need to compensate the
+	 * memory arbitration imperfection for them in order to prevent FIFO
+	 * underflow condition when memory bus is busy.
+	 *
+	 * VI clients also need a stronger compensation.
+	 */
+	switch (client->swgroup) {
+	case TEGRA_SWGROUP_MPCORE:
+	case TEGRA_SWGROUP_PTC:
+		/*
+		 * We always want lower latency for these clients, hence
+		 * don't touch them.
+		 */
+		return;
+
+	case TEGRA_SWGROUP_DC:
+	case TEGRA_SWGROUP_DCB:
+		arb_tolerance_compensation_nsec = 1050;
+		arb_tolerance_compensation_div = 2;
+		break;
+
+	case TEGRA_SWGROUP_VI:
+		arb_tolerance_compensation_nsec = 1050;
+		arb_tolerance_compensation_div = 1;
+		break;
+
+	default:
+		arb_tolerance_compensation_nsec = 150;
+		arb_tolerance_compensation_div = 1;
+		break;
+	}
+
+	if (arb_nsec > arb_tolerance_compensation_nsec)
+		arb_nsec -= arb_tolerance_compensation_nsec;
+	else
+		arb_nsec = 0;
+
+	arb_nsec /= arb_tolerance_compensation_div;
+
+	/*
+	 * Latency allowance is a number of ticks a request from a particular
+	 * client may wait in the EMEM arbiter before it becomes a high-priority
+	 * request.
+	 */
+	la_ticks = arb_nsec / mc->tick;
+	la_ticks = min(la_ticks, client->regs.la.mask);
+
+	value = mc_readl(mc, client->regs.la.reg);
+	value &= ~(client->regs.la.mask << client->regs.la.shift);
+	value |= la_ticks << client->regs.la.shift;
+	mc_writel(mc, value, client->regs.la.reg);
+}
+
+static int tegra114_mc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);
+	const struct tegra_mc_client *client = &mc->soc->clients[src->id];
+	u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);
+
+	/*
+	 * Skip pre-initialization that is done by icc_node_add(), which sets
+	 * bandwidth to maximum for all clients before drivers are loaded.
+	 *
+	 * This doesn't make sense for us because we don't have drivers for all
+	 * clients and it's okay to keep configuration left from bootloader
+	 * during boot, at least for today.
+	 */
+	if (src == dst)
+		return 0;
+
+	/* convert bytes/sec to megabytes/sec */
+	do_div(peak_bandwidth, 1000000);
+
+	tegra114_mc_tune_client_latency(mc, client, peak_bandwidth);
+
+	return 0;
+}
+
+static int tegra114_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
+				    u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
+{
+	/*
+	 * ISO clients need to reserve extra bandwidth up-front because
+	 * there could be high bandwidth pressure during initial filling
+	 * of the client's FIFO buffers.  Secondly, we need to take into
+	 * account impurities of the memory subsystem.
+	 */
+	if (tag & TEGRA_MC_ICC_TAG_ISO)
+		peak_bw = tegra_mc_scale_percents(peak_bw, 400);
+
+	*agg_avg += avg_bw;
+	*agg_peak = max(*agg_peak, peak_bw);
+
+	return 0;
+}
+
+static struct icc_node_data *
+tegra114_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
+{
+	struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
+	const struct tegra_mc_client *client;
+	unsigned int i, idx = spec->args[0];
+	struct icc_node_data *ndata;
+	struct icc_node *node;
+
+	list_for_each_entry(node, &mc->provider.nodes, node_list) {
+		if (node->id != idx)
+			continue;
+
+		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
+		if (!ndata)
+			return ERR_PTR(-ENOMEM);
+
+		client = &mc->soc->clients[idx];
+		ndata->node = node;
+
+		switch (client->swgroup) {
+		case TEGRA_SWGROUP_DC:
+		case TEGRA_SWGROUP_DCB:
+		case TEGRA_SWGROUP_PTC:
+		case TEGRA_SWGROUP_VI:
+			/* these clients are isochronous by default */
+			ndata->tag = TEGRA_MC_ICC_TAG_ISO;
+			break;
+
+		default:
+			ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
+			break;
+		}
+
+		return ndata;
+	}
+
+	for (i = 0; i < mc->soc->num_clients; i++) {
+		if (mc->soc->clients[i].id == idx)
+			return ERR_PTR(-EPROBE_DEFER);
+	}
+
+	dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
+
+	return ERR_PTR(-EINVAL);
+}
+
+static const struct tegra_mc_icc_ops tegra114_mc_icc_ops = {
+	.xlate_extended = tegra114_mc_of_icc_xlate_extended,
+	.aggregate = tegra114_mc_icc_aggreate,
+	.set = tegra114_mc_icc_set,
+};
+
+static const unsigned long tegra114_mc_emem_regs[] = {
+	MC_EMEM_ARB_CFG,
+	MC_EMEM_ARB_OUTSTANDING_REQ,
+	MC_EMEM_ARB_TIMING_RCD,
+	MC_EMEM_ARB_TIMING_RP,
+	MC_EMEM_ARB_TIMING_RC,
+	MC_EMEM_ARB_TIMING_RAS,
+	MC_EMEM_ARB_TIMING_FAW,
+	MC_EMEM_ARB_TIMING_RRD,
+	MC_EMEM_ARB_TIMING_RAP2PRE,
+	MC_EMEM_ARB_TIMING_WAP2PRE,
+	MC_EMEM_ARB_TIMING_R2R,
+	MC_EMEM_ARB_TIMING_W2W,
+	MC_EMEM_ARB_TIMING_R2W,
+	MC_EMEM_ARB_TIMING_W2R,
+	MC_EMEM_ARB_DA_TURNS,
+	MC_EMEM_ARB_DA_COVERS,
+	MC_EMEM_ARB_MISC0,
+	MC_EMEM_ARB_RING1_THROTTLE,
+};
+
 const struct tegra_mc_soc tegra114_mc_soc = {
 	.clients = tegra114_mc_clients,
 	.num_clients = ARRAY_SIZE(tegra114_mc_clients),
@@ -1172,10 +1362,13 @@ const struct tegra_mc_soc tegra114_mc_soc = {
 	.atom_size = 32,
 	.client_id_mask = 0x7f,
 	.smmu = &tegra114_smmu_soc,
+	.emem_regs = tegra114_mc_emem_regs,
+	.num_emem_regs = ARRAY_SIZE(tegra114_mc_emem_regs),
 	.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
 		   MC_INT_DECERR_EMEM,
 	.reset_ops = &tegra_mc_reset_ops_common,
 	.resets = tegra114_mc_resets,
 	.num_resets = ARRAY_SIZE(tegra114_mc_resets),
+	.icc_ops = &tegra114_mc_icc_ops,
 	.ops = &tegra30_mc_ops,
 };
-- 
2.51.0

[PATCH v4 05/12] dt-bindings: memory: Add Tegra114 memory client IDs

[Svyatoslav Ryhel]

Each memory client has unique hardware ID, add these IDs.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 include/dt-bindings/memory/tegra114-mc.h | 67 ++++++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h
index dfe99c8a5ba5..5e0d6a1b91f2 100644
--- a/include/dt-bindings/memory/tegra114-mc.h
+++ b/include/dt-bindings/memory/tegra114-mc.h
@@ -40,4 +40,71 @@
 #define TEGRA114_MC_RESET_VDE		14
 #define TEGRA114_MC_RESET_VI		15
 
+#define TEGRA114_MC_PTCR		0
+#define TEGRA114_MC_DISPLAY0A		1
+#define TEGRA114_MC_DISPLAY0AB		2
+#define TEGRA114_MC_DISPLAY0B		3
+#define TEGRA114_MC_DISPLAY0BB		4
+#define TEGRA114_MC_DISPLAY0C		5
+#define TEGRA114_MC_DISPLAY0CB		6
+#define TEGRA114_MC_DISPLAY1B		7
+#define TEGRA114_MC_DISPLAY1BB		8
+#define TEGRA114_MC_EPPUP		9
+#define TEGRA114_MC_G2PR		10
+#define TEGRA114_MC_G2SR		11
+#define TEGRA114_MC_MPEUNIFBR		12
+#define TEGRA114_MC_VIRUV		13
+#define TEGRA114_MC_AFIR		14
+#define TEGRA114_MC_AVPCARM7R		15
+#define TEGRA114_MC_DISPLAYHC		16
+#define TEGRA114_MC_DISPLAYHCB		17
+#define TEGRA114_MC_FDCDRD		18
+#define TEGRA114_MC_FDCDRD2		19
+#define TEGRA114_MC_G2DR		20
+#define TEGRA114_MC_HDAR		21
+#define TEGRA114_MC_HOST1XDMAR		22
+#define TEGRA114_MC_HOST1XR		23
+#define TEGRA114_MC_IDXSRD		24
+#define TEGRA114_MC_IDXSRD2		25
+#define TEGRA114_MC_MPE_IPRED		26
+#define TEGRA114_MC_MPEAMEMRD		27
+#define TEGRA114_MC_MPECSRD		28
+#define TEGRA114_MC_PPCSAHBDMAR		29
+#define TEGRA114_MC_PPCSAHBSLVR		30
+#define TEGRA114_MC_SATAR		31
+#define TEGRA114_MC_TEXSRD		32
+#define TEGRA114_MC_TEXSRD2		33
+#define TEGRA114_MC_VDEBSEVR		34
+#define TEGRA114_MC_VDEMBER		35
+#define TEGRA114_MC_VDEMCER		36
+#define TEGRA114_MC_VDETPER		37
+#define TEGRA114_MC_MPCORELPR		38
+#define TEGRA114_MC_MPCORER		39
+#define TEGRA114_MC_EPPU		40
+#define TEGRA114_MC_EPPV		41
+#define TEGRA114_MC_EPPY		42
+#define TEGRA114_MC_MPEUNIFBW		43
+#define TEGRA114_MC_VIWSB		44
+#define TEGRA114_MC_VIWU		45
+#define TEGRA114_MC_VIWV		46
+#define TEGRA114_MC_VIWY		47
+#define TEGRA114_MC_G2DW		48
+#define TEGRA114_MC_AFIW		49
+#define TEGRA114_MC_AVPCARM7W		50
+#define TEGRA114_MC_FDCDWR		51
+#define TEGRA114_MC_FDCDWR2		52
+#define TEGRA114_MC_HDAW		53
+#define TEGRA114_MC_HOST1XW		54
+#define TEGRA114_MC_ISPW		55
+#define TEGRA114_MC_MPCORELPW		56
+#define TEGRA114_MC_MPCOREW		57
+#define TEGRA114_MC_MPECSWR		58
+#define TEGRA114_MC_PPCSAHBDMAW		59
+#define TEGRA114_MC_PPCSAHBSLVW		60
+#define TEGRA114_MC_SATAW		61
+#define TEGRA114_MC_VDEBSEVW		62
+#define TEGRA114_MC_VDEDBGW		63
+#define TEGRA114_MC_VDEMBEW		64
+#define TEGRA114_MC_VDETPMW		65
+
 #endif
-- 
2.51.0

[PATCH v4 06/12] clk: tegra: set up proper EMC clock implementation for Tegra114

[Svyatoslav Ryhel]

Remove current emc and emc_mux clocks and replace them with the proper EMC
clock implementation for correct EMC driver support.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/clk/tegra/clk-tegra114.c | 39 ++++++++++++++++++++------------
 1 file changed, 25 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 8bde72aa5e68..853ef707654a 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] = {
 };
 #define mux_plld_out0_plld2_out0_idx NULL
 
-static const char *mux_pllmcp_clkm[] = {
-	"pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
-};
-
 static const struct clk_div_table pll_re_div_table[] = {
 	{ .val = 0, .div = 1 },
 	{ .val = 1, .div = 2 },
@@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
 	[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
 	[tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
 	[tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
-	[tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
 	[tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
 	[tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
 	[tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
@@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
 					     0, 82, periph_clk_enb_refcnt);
 	clks[TEGRA114_CLK_DSIB] = clk;
 
-	/* emc mux */
-	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
-			       ARRAY_SIZE(mux_pllmcp_clkm),
-			       CLK_SET_RATE_NO_REPARENT,
-			       clk_base + CLK_SOURCE_EMC,
-			       29, 3, 0, &emc_lock);
-
-	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
 				    &emc_lock);
 	clks[TEGRA114_CLK_MC] = clk;
 
@@ -1321,6 +1309,26 @@ static int tegra114_reset_deassert(unsigned long id)
 	return 0;
 }
 
+static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec,
+						void *data)
+{
+	struct clk_hw *hw;
+	struct clk *clk;
+
+	clk = of_clk_src_onecell_get(clkspec, data);
+	if (IS_ERR(clk))
+		return clk;
+
+	hw = __clk_get_hw(clk);
+
+	if (clkspec->args[0] == TEGRA114_CLK_EMC) {
+		if (!tegra124_clk_emc_driver_available(hw))
+			return ERR_PTR(-EPROBE_DEFER);
+	}
+
+	return clk;
+}
+
 static void __init tegra114_clock_init(struct device_node *np)
 {
 	struct device_node *node;
@@ -1368,7 +1376,10 @@ static void __init tegra114_clock_init(struct device_node *np)
 	tegra_init_special_resets(1, tegra114_reset_assert,
 				  tegra114_reset_deassert);
 
-	tegra_add_of_provider(np, of_clk_src_onecell_get);
+	tegra_add_of_provider(np, tegra114_clk_src_onecell_get);
+	clks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,
+							   &emc_lock);
+
 	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
 
 	tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
-- 
2.51.0

[PATCH v4 07/12] dt-bindings: memory: Document Tegra114 External Memory Controller

[Svyatoslav Ryhel]

Include Tegra114 support into existing Tegra124 EMC schema with the most
notable difference being the amount of EMC timings and a few SoC unique
entries.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 .../nvidia,tegra124-emc.yaml                  | 174 +++---------------
 1 file changed, 26 insertions(+), 148 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
index f5f03bf36413..9398aae49093 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
@@ -16,7 +16,9 @@ description: |
 
 properties:
   compatible:
-    const: nvidia,tegra124-emc
+    enum:
+      - nvidia,tegra114-emc
+      - nvidia,tegra124-emc
 
   reg:
     maxItems: 1
@@ -29,6 +31,9 @@ properties:
     items:
       - const: emc
 
+  interrupts:
+    maxItems: 1
+
   "#interconnect-cells":
     const: 0
 
@@ -164,153 +169,12 @@ patternProperties:
           nvidia,emc-configuration:
             description:
               EMC timing characterization data. These are the registers (see
-              section "15.6.2 EMC Registers" in the TRM) whose values need to
+              section "20.11.2 EMC Registers" in the Tegra114 TRM or section
+              "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
               be specified, according to the board documentation.
             $ref: /schemas/types.yaml#/definitions/uint32-array
-            items:
-              - description: EMC_RC
-              - description: EMC_RFC
-              - description: EMC_RFC_SLR
-              - description: EMC_RAS
-              - description: EMC_RP
-              - description: EMC_R2W
-              - description: EMC_W2R
-              - description: EMC_R2P
-              - description: EMC_W2P
-              - description: EMC_RD_RCD
-              - description: EMC_WR_RCD
-              - description: EMC_RRD
-              - description: EMC_REXT
-              - description: EMC_WEXT
-              - description: EMC_WDV
-              - description: EMC_WDV_MASK
-              - description: EMC_QUSE
-              - description: EMC_QUSE_WIDTH
-              - description: EMC_IBDLY
-              - description: EMC_EINPUT
-              - description: EMC_EINPUT_DURATION
-              - description: EMC_PUTERM_EXTRA
-              - description: EMC_PUTERM_WIDTH
-              - description: EMC_PUTERM_ADJ
-              - description: EMC_CDB_CNTL_1
-              - description: EMC_CDB_CNTL_2
-              - description: EMC_CDB_CNTL_3
-              - description: EMC_QRST
-              - description: EMC_QSAFE
-              - description: EMC_RDV
-              - description: EMC_RDV_MASK
-              - description: EMC_REFRESH
-              - description: EMC_BURST_REFRESH_NUM
-              - description: EMC_PRE_REFRESH_REQ_CNT
-              - description: EMC_PDEX2WR
-              - description: EMC_PDEX2RD
-              - description: EMC_PCHG2PDEN
-              - description: EMC_ACT2PDEN
-              - description: EMC_AR2PDEN
-              - description: EMC_RW2PDEN
-              - description: EMC_TXSR
-              - description: EMC_TXSRDLL
-              - description: EMC_TCKE
-              - description: EMC_TCKESR
-              - description: EMC_TPD
-              - description: EMC_TFAW
-              - description: EMC_TRPAB
-              - description: EMC_TCLKSTABLE
-              - description: EMC_TCLKSTOP
-              - description: EMC_TREFBW
-              - description: EMC_FBIO_CFG6
-              - description: EMC_ODT_WRITE
-              - description: EMC_ODT_READ
-              - description: EMC_FBIO_CFG5
-              - description: EMC_CFG_DIG_DLL
-              - description: EMC_CFG_DIG_DLL_PERIOD
-              - description: EMC_DLL_XFORM_DQS0
-              - description: EMC_DLL_XFORM_DQS1
-              - description: EMC_DLL_XFORM_DQS2
-              - description: EMC_DLL_XFORM_DQS3
-              - description: EMC_DLL_XFORM_DQS4
-              - description: EMC_DLL_XFORM_DQS5
-              - description: EMC_DLL_XFORM_DQS6
-              - description: EMC_DLL_XFORM_DQS7
-              - description: EMC_DLL_XFORM_DQS8
-              - description: EMC_DLL_XFORM_DQS9
-              - description: EMC_DLL_XFORM_DQS10
-              - description: EMC_DLL_XFORM_DQS11
-              - description: EMC_DLL_XFORM_DQS12
-              - description: EMC_DLL_XFORM_DQS13
-              - description: EMC_DLL_XFORM_DQS14
-              - description: EMC_DLL_XFORM_DQS15
-              - description: EMC_DLL_XFORM_QUSE0
-              - description: EMC_DLL_XFORM_QUSE1
-              - description: EMC_DLL_XFORM_QUSE2
-              - description: EMC_DLL_XFORM_QUSE3
-              - description: EMC_DLL_XFORM_QUSE4
-              - description: EMC_DLL_XFORM_QUSE5
-              - description: EMC_DLL_XFORM_QUSE6
-              - description: EMC_DLL_XFORM_QUSE7
-              - description: EMC_DLL_XFORM_ADDR0
-              - description: EMC_DLL_XFORM_ADDR1
-              - description: EMC_DLL_XFORM_ADDR2
-              - description: EMC_DLL_XFORM_ADDR3
-              - description: EMC_DLL_XFORM_ADDR4
-              - description: EMC_DLL_XFORM_ADDR5
-              - description: EMC_DLL_XFORM_QUSE8
-              - description: EMC_DLL_XFORM_QUSE9
-              - description: EMC_DLL_XFORM_QUSE10
-              - description: EMC_DLL_XFORM_QUSE11
-              - description: EMC_DLL_XFORM_QUSE12
-              - description: EMC_DLL_XFORM_QUSE13
-              - description: EMC_DLL_XFORM_QUSE14
-              - description: EMC_DLL_XFORM_QUSE15
-              - description: EMC_DLI_TRIM_TXDQS0
-              - description: EMC_DLI_TRIM_TXDQS1
-              - description: EMC_DLI_TRIM_TXDQS2
-              - description: EMC_DLI_TRIM_TXDQS3
-              - description: EMC_DLI_TRIM_TXDQS4
-              - description: EMC_DLI_TRIM_TXDQS5
-              - description: EMC_DLI_TRIM_TXDQS6
-              - description: EMC_DLI_TRIM_TXDQS7
-              - description: EMC_DLI_TRIM_TXDQS8
-              - description: EMC_DLI_TRIM_TXDQS9
-              - description: EMC_DLI_TRIM_TXDQS10
-              - description: EMC_DLI_TRIM_TXDQS11
-              - description: EMC_DLI_TRIM_TXDQS12
-              - description: EMC_DLI_TRIM_TXDQS13
-              - description: EMC_DLI_TRIM_TXDQS14
-              - description: EMC_DLI_TRIM_TXDQS15
-              - description: EMC_DLL_XFORM_DQ0
-              - description: EMC_DLL_XFORM_DQ1
-              - description: EMC_DLL_XFORM_DQ2
-              - description: EMC_DLL_XFORM_DQ3
-              - description: EMC_DLL_XFORM_DQ4
-              - description: EMC_DLL_XFORM_DQ5
-              - description: EMC_DLL_XFORM_DQ6
-              - description: EMC_DLL_XFORM_DQ7
-              - description: EMC_XM2CMDPADCTRL
-              - description: EMC_XM2CMDPADCTRL4
-              - description: EMC_XM2CMDPADCTRL5
-              - description: EMC_XM2DQPADCTRL2
-              - description: EMC_XM2DQPADCTRL3
-              - description: EMC_XM2CLKPADCTRL
-              - description: EMC_XM2CLKPADCTRL2
-              - description: EMC_XM2COMPPADCTRL
-              - description: EMC_XM2VTTGENPADCTRL
-              - description: EMC_XM2VTTGENPADCTRL2
-              - description: EMC_XM2VTTGENPADCTRL3
-              - description: EMC_XM2DQSPADCTRL3
-              - description: EMC_XM2DQSPADCTRL4
-              - description: EMC_XM2DQSPADCTRL5
-              - description: EMC_XM2DQSPADCTRL6
-              - description: EMC_DSR_VTTGEN_DRV
-              - description: EMC_TXDSRVTTGEN
-              - description: EMC_FBIO_SPARE
-              - description: EMC_ZCAL_WAIT_CNT
-              - description: EMC_MRS_WAIT_CNT2
-              - description: EMC_CTT
-              - description: EMC_CTT_DURATION
-              - description: EMC_CFG_PIPE
-              - description: EMC_DYN_SELF_REF_CONTROL
-              - description: EMC_QPOP
+            minItems: 97
+            maxItems: 143
 
         required:
           - clock-frequency
@@ -318,9 +182,7 @@ patternProperties:
           - nvidia,emc-auto-cal-config2
           - nvidia,emc-auto-cal-config3
           - nvidia,emc-auto-cal-interval
-          - nvidia,emc-bgbias-ctl0
           - nvidia,emc-cfg
-          - nvidia,emc-cfg-2
           - nvidia,emc-ctt-term-ctrl
           - nvidia,emc-mode-1
           - nvidia,emc-mode-2
@@ -344,6 +206,22 @@ required:
   - "#interconnect-cells"
   - operating-points-v2
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra124-emc
+    then:
+      patternProperties:
+        "^emc-timings-[0-9]+$":
+          patternProperties:
+            "^timing-[0-9]+$":
+              required:
+                - nvidia,emc-bgbias-ctl0
+                - nvidia,emc-cfg-2
+
 additionalProperties: false
 
 examples:
-- 
2.51.0

[PATCH v4 08/12] soc: tegra: common: add Tegra114 support to devm_tegra_core_dev_init_opp_table

[Svyatoslav Ryhel]

Determine the Tegra114 hardware version using the SoC Speedo ID bit macro,
mirroring the approach already used for Tegra30 and Tegra124.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/soc/tegra/common.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
index 6292a1c72071..2264dd38893a 100644
--- a/drivers/soc/tegra/common.c
+++ b/drivers/soc/tegra/common.c
@@ -143,7 +143,8 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
 		hw_version = BIT(tegra_sku_info.soc_process_id);
 		config.supported_hw = &hw_version;
 		config.supported_hw_count = 1;
-	} else if (of_machine_is_compatible("nvidia,tegra30")) {
+	} else if (of_machine_is_compatible("nvidia,tegra30") ||
+		   of_machine_is_compatible("nvidia,tegra114")) {
 		hw_version = BIT(tegra_sku_info.soc_speedo_id);
 		config.supported_hw = &hw_version;
 		config.supported_hw_count = 1;
@@ -156,7 +157,7 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
 	}
 
 	/*
-	 * Tegra114+ doesn't support OPP yet, return early for non tegra20/30
+	 * Tegra124+ doesn't support OPP yet, return early for pre-Tegra124
 	 * case.
 	 */
 	if (!config.supported_hw)
-- 
2.51.0

[PATCH v4 09/12] memory: tegra: Add Tegra114 EMC driver

[Svyatoslav Ryhel]

Introduce driver for the External Memory Controller (EMC) found in
Tegra114 SoC. It controls the external DRAM on the board. The purpose of
this driver is to program memory timing for external memory on the EMC
clock rate change.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 drivers/memory/tegra/Kconfig        |   12 +
 drivers/memory/tegra/Makefile       |    1 +
 drivers/memory/tegra/tegra114-emc.c | 1463 +++++++++++++++++++++++++++
 3 files changed, 1476 insertions(+)
 create mode 100644 drivers/memory/tegra/tegra114-emc.c

diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index fc5a27791826..11e7cc357d39 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -35,6 +35,18 @@ config TEGRA30_EMC
 	  This driver is required to change memory timings / clock rate for
 	  external memory.
 
+config TEGRA114_EMC
+	tristate "NVIDIA Tegra114 External Memory Controller driver"
+	default y
+	depends on ARCH_TEGRA_114_SOC || COMPILE_TEST
+	select TEGRA124_CLK_EMC if ARCH_TEGRA
+	select PM_OPP
+	help
+	  This driver is for the External Memory Controller (EMC) found on
+	  Tegra114 chips. The EMC controls the external DRAM on the board.
+	  This driver is required to change memory timings / clock rate for
+	  external memory.
+
 config TEGRA124_EMC
 	tristate "NVIDIA Tegra124 External Memory Controller driver"
 	default ARCH_TEGRA_124_SOC
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index 6334601e6120..6b9156de4b66 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
 
 obj-$(CONFIG_TEGRA20_EMC)  += tegra20-emc.o
 obj-$(CONFIG_TEGRA30_EMC)  += tegra30-emc.o
+obj-$(CONFIG_TEGRA114_EMC) += tegra114-emc.o
 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
diff --git a/drivers/memory/tegra/tegra114-emc.c b/drivers/memory/tegra/tegra114-emc.c
new file mode 100644
index 000000000000..789b8e959a68
--- /dev/null
+++ b/drivers/memory/tegra/tegra114-emc.c
@@ -0,0 +1,1463 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Tegra114 External Memory Controller driver
+ *
+ * Based on downstream driver from NVIDIA and tegra124-emc.c
+ * Copyright (C) 2011-2014 NVIDIA Corporation
+ *
+ * Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk/tegra.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/interconnect-provider.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/sort.h>
+#include <linux/string.h>
+
+#include <soc/tegra/common.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/mc.h>
+
+#include "mc.h"
+
+#define EMC_INTSTATUS				0x0
+#define EMC_INTSTATUS_REFRESH_OVERFLOW		BIT(3)
+#define EMC_INTSTATUS_CLKCHANGE_COMPLETE	BIT(4)
+
+#define EMC_INTMASK				0x4
+
+#define EMC_DBG					0x8
+#define EMC_DBG_READ_MUX_ASSEMBLY		BIT(0)
+#define EMC_DBG_WRITE_MUX_ACTIVE		BIT(1)
+#define EMC_DBG_FORCE_UPDATE			BIT(2)
+#define EMC_DBG_CFG_PRIORITY			BIT(24)
+
+#define EMC_CFG					0xc
+#define EMC_CFG_DSR_VTTGEN_DRV_EN		BIT(18)
+#define EMC_CFG_PWR_MASK			((0xF << 28) | BIT(18))
+#define EMC_CFG_DYN_SREF			BIT(28)
+#define EMC_CFG_DRAM_ACPD			BIT(29)
+#define EMC_CFG_DRAM_CLKSTOP_SR			BIT(30)
+#define EMC_CFG_DRAM_CLKSTOP_PD			BIT(31)
+
+#define EMC_ADR_CFG				0x10
+#define EMC_ADR_CFG_EMEM_NUMDEV			BIT(0)
+
+#define EMC_REFCTRL				0x20
+#define EMC_REFCTRL_DEV_SEL_SHIFT		0
+#define EMC_REFCTRL_ENABLE			BIT(31)
+
+#define EMC_TIMING_CONTROL			0x28
+#define EMC_RC					0x2c
+#define EMC_RFC					0x30
+#define EMC_RAS					0x34
+#define EMC_RP					0x38
+#define EMC_R2W					0x3c
+#define EMC_W2R					0x40
+#define EMC_R2P					0x44
+#define EMC_W2P					0x48
+#define EMC_RD_RCD				0x4c
+#define EMC_WR_RCD				0x50
+#define EMC_RRD					0x54
+#define EMC_REXT				0x58
+#define EMC_WDV					0x5c
+#define EMC_QUSE				0x60
+#define EMC_QRST				0x64
+#define EMC_QSAFE				0x68
+#define EMC_RDV					0x6c
+#define EMC_REFRESH				0x70
+#define EMC_BURST_REFRESH_NUM			0x74
+#define EMC_PDEX2WR				0x78
+#define EMC_PDEX2RD				0x7c
+#define EMC_PCHG2PDEN				0x80
+#define EMC_ACT2PDEN				0x84
+#define EMC_AR2PDEN				0x88
+#define EMC_RW2PDEN				0x8c
+#define EMC_TXSR				0x90
+#define EMC_TCKE				0x94
+#define EMC_TFAW				0x98
+#define EMC_TRPAB				0x9c
+#define EMC_TCLKSTABLE				0xa0
+#define EMC_TCLKSTOP				0xa4
+#define EMC_TREFBW				0xa8
+#define EMC_QUSE_EXTRA				0xac
+#define EMC_ODT_WRITE				0xb0
+#define EMC_ODT_READ				0xb4
+#define EMC_WEXT				0xb8
+#define EMC_CTT					0xbc
+#define EMC_RFC_SLR				0xc0
+#define EMC_MRS_WAIT_CNT2			0xc4
+
+#define EMC_MRS_WAIT_CNT			0xc8
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT	0
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK	\
+	(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT	16
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK		\
+	(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
+
+#define EMC_MRS					0xcc
+#define EMC_MODE_SET_DLL_RESET			BIT(8)
+#define EMC_MODE_SET_LONG_CNT			BIT(26)
+#define EMC_EMRS				0xd0
+#define EMC_REF					0xd4
+#define EMC_PRE					0xd8
+
+#define EMC_SELF_REF				0xe0
+#define EMC_SELF_REF_CMD_ENABLED		BIT(0)
+#define EMC_SELF_REF_DEV_SEL_SHIFT		30
+
+#define EMC_MRW					0xe8
+
+#define EMC_MRR					0xec
+#define EMC_MRR_MA_SHIFT			16
+#define LPDDR2_MR4_TEMP_SHIFT			0
+
+#define EMC_XM2DQSPADCTRL3			0xf8
+#define EMC_FBIO_SPARE				0x100
+
+#define EMC_FBIO_CFG5				0x104
+#define EMC_FBIO_CFG5_DRAM_TYPE_MASK		0x3
+#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT		0
+
+#define EMC_FBIO_CFG6				0x114
+#define EMC_EMRS2				0x12c
+#define EMC_MRW2				0x134
+#define EMC_MRW4				0x13c
+#define EMC_EINPUT				0x14c
+#define EMC_EINPUT_DURATION			0x150
+#define EMC_PUTERM_EXTRA			0x154
+#define EMC_TCKESR				0x158
+#define EMC_TPD					0x15c
+
+#define EMC_AUTO_CAL_CONFIG			0x2a4
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START	BIT(31)
+#define EMC_AUTO_CAL_INTERVAL			0x2a8
+#define EMC_AUTO_CAL_STATUS			0x2ac
+#define EMC_AUTO_CAL_STATUS_ACTIVE		BIT(31)
+#define EMC_STATUS				0x2b4
+#define EMC_STATUS_TIMING_UPDATE_STALLED	BIT(23)
+
+#define EMC_CFG_2				0x2b8
+#define EMC_CFG_2_CLKCHANGE_REQ_ENABLE		BIT(0)
+#define EMC_CFG_2_CLKCHANGE_PD_ENABLE		BIT(1)
+#define EMC_CFG_2_CLKCHANGE_SR_ENABLE		BIT(2)
+
+#define EMC_CFG_DIG_DLL				0x2bc
+#define EMC_CFG_DIG_DLL_PERIOD			0x2c0
+#define EMC_RDV_MASK				0x2cc
+#define EMC_WDV_MASK				0x2d0
+#define EMC_CTT_DURATION			0x2d8
+#define EMC_CTT_TERM_CTRL			0x2dc
+#define EMC_ZCAL_INTERVAL			0x2e0
+#define EMC_ZCAL_WAIT_CNT			0x2e4
+
+#define EMC_ZQ_CAL				0x2ec
+#define EMC_ZQ_CAL_CMD				BIT(0)
+#define EMC_ZQ_CAL_LONG				BIT(4)
+#define EMC_ZQ_CAL_LONG_CMD_DEV0		\
+	(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+#define EMC_ZQ_CAL_LONG_CMD_DEV1		\
+	(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+
+#define EMC_XM2CMDPADCTRL			0x2f0
+#define EMC_XM2DQSPADCTRL			0x2f8
+#define EMC_XM2DQSPADCTRL2			0x2fc
+#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE	BIT(0)
+#define EMC_XM2DQSPADCTRL2_VREF_ENABLE		BIT(5)
+#define EMC_XM2DQPADCTRL			0x300
+#define EMC_XM2DQPADCTRL2			0x304
+#define EMC_XM2CLKPADCTRL			0x308
+#define EMC_XM2COMPPADCTRL			0x30c
+#define EMC_XM2VTTGENPADCTRL			0x310
+#define EMC_XM2VTTGENPADCTRL2			0x314
+#define EMC_XM2QUSEPADCTRL			0x318
+#define EMC_XM2DQSPADCTRL4			0x320
+#define EMC_DLL_XFORM_DQS0			0x328
+#define EMC_DLL_XFORM_DQS1			0x32c
+#define EMC_DLL_XFORM_DQS2			0x330
+#define EMC_DLL_XFORM_DQS3			0x334
+#define EMC_DLL_XFORM_DQS4			0x338
+#define EMC_DLL_XFORM_DQS5			0x33c
+#define EMC_DLL_XFORM_DQS6			0x340
+#define EMC_DLL_XFORM_DQS7			0x344
+#define EMC_DLL_XFORM_QUSE0			0x348
+#define EMC_DLL_XFORM_QUSE1			0x34c
+#define EMC_DLL_XFORM_QUSE2			0x350
+#define EMC_DLL_XFORM_QUSE3			0x354
+#define EMC_DLL_XFORM_QUSE4			0x358
+#define EMC_DLL_XFORM_QUSE5			0x35c
+#define EMC_DLL_XFORM_QUSE6			0x360
+#define EMC_DLL_XFORM_QUSE7			0x364
+#define EMC_DLL_XFORM_DQ0			0x368
+#define EMC_DLL_XFORM_DQ1			0x36c
+#define EMC_DLL_XFORM_DQ2			0x370
+#define EMC_DLL_XFORM_DQ3			0x374
+#define EMC_DLI_TRIM_TXDQS0			0x3a8
+#define EMC_DLI_TRIM_TXDQS1			0x3ac
+#define EMC_DLI_TRIM_TXDQS2			0x3b0
+#define EMC_DLI_TRIM_TXDQS3			0x3b4
+#define EMC_DLI_TRIM_TXDQS4			0x3b8
+#define EMC_DLI_TRIM_TXDQS5			0x3bc
+#define EMC_DLI_TRIM_TXDQS6			0x3c0
+#define EMC_DLI_TRIM_TXDQS7			0x3c4
+#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE	0x3cc
+#define EMC_SEL_DPD_CTRL			0x3d8
+#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD		BIT(8)
+#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD		BIT(5)
+#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD		BIT(4)
+#define EMC_SEL_DPD_CTRL_CA_SEL_DPD		BIT(3)
+#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD		BIT(2)
+#define EMC_SEL_DPD_CTRL_DDR3_MASK	\
+	((0xf << 2) | BIT(8))
+#define EMC_SEL_DPD_CTRL_MASK \
+	((0x3 << 2) | BIT(5) | BIT(8))
+#define EMC_PRE_REFRESH_REQ_CNT			0x3dc
+#define EMC_DYN_SELF_REF_CONTROL		0x3e0
+#define EMC_TXSRDLL				0x3e4
+#define EMC_CCFIFO_ADDR				0x3e8
+#define EMC_CCFIFO_DATA				0x3ec
+#define EMC_CCFIFO_STATUS			0x3f0
+#define EMC_CDB_CNTL_1				0x3f4
+#define EMC_CDB_CNTL_2				0x3f8
+#define EMC_XM2CLKPADCTRL2			0x3fc
+#define EMC_AUTO_CAL_CONFIG2			0x458
+#define EMC_AUTO_CAL_CONFIG3			0x45c
+#define EMC_IBDLY				0x468
+#define EMC_DLL_XFORM_ADDR0			0x46c
+#define EMC_DLL_XFORM_ADDR1			0x470
+#define EMC_DLL_XFORM_ADDR2			0x474
+#define EMC_DSR_VTTGEN_DRV			0x47c
+#define EMC_TXDSRVTTGEN				0x480
+#define EMC_XM2CMDPADCTRL4			0x484
+
+#define DRAM_DEV_SEL_ALL			0
+#define DRAM_DEV_SEL_0				BIT(31)
+#define DRAM_DEV_SEL_1				BIT(30)
+
+#define EMC_CFG_POWER_FEATURES_MASK		\
+	(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
+	EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
+#define EMC_REFCTRL_DEV_SEL(n) ((((n) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
+#define EMC_DRAM_DEV_SEL(n) (((n) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
+
+/* Maximum amount of time in us. to wait for changes to become effective */
+#define EMC_STATUS_UPDATE_TIMEOUT		1000
+
+enum emc_dram_type {
+	DRAM_TYPE_DDR3,
+	DRAM_TYPE_DDR1,
+	DRAM_TYPE_LPDDR2,
+	DRAM_TYPE_DDR2
+};
+
+enum emc_dll_change {
+	DLL_CHANGE_NONE,
+	DLL_CHANGE_ON,
+	DLL_CHANGE_OFF
+};
+
+static const unsigned long emc_burst_regs[] = {
+	EMC_RC,
+	EMC_RFC,
+	EMC_RAS,
+	EMC_RP,
+	EMC_R2W,
+	EMC_W2R,
+	EMC_R2P,
+	EMC_W2P,
+	EMC_RD_RCD,
+	EMC_WR_RCD,
+	EMC_RRD,
+	EMC_REXT,
+	EMC_WEXT,
+	EMC_WDV,
+	EMC_WDV_MASK,
+	EMC_QUSE,
+	EMC_IBDLY,
+	EMC_EINPUT,
+	EMC_EINPUT_DURATION,
+	EMC_PUTERM_EXTRA,
+	EMC_CDB_CNTL_1,
+	EMC_CDB_CNTL_2,
+	EMC_QRST,
+	EMC_QSAFE,
+	EMC_RDV,
+	EMC_RDV_MASK,
+	EMC_REFRESH,
+	EMC_BURST_REFRESH_NUM,
+	EMC_PRE_REFRESH_REQ_CNT,
+	EMC_PDEX2WR,
+	EMC_PDEX2RD,
+	EMC_PCHG2PDEN,
+	EMC_ACT2PDEN,
+	EMC_AR2PDEN,
+	EMC_RW2PDEN,
+	EMC_TXSR,
+	EMC_TXSRDLL,
+	EMC_TCKE,
+	EMC_TCKESR,
+	EMC_TPD,
+	EMC_TFAW,
+	EMC_TRPAB,
+	EMC_TCLKSTABLE,
+	EMC_TCLKSTOP,
+	EMC_TREFBW,
+	EMC_QUSE_EXTRA,
+	EMC_FBIO_CFG6,
+	EMC_ODT_WRITE,
+	EMC_ODT_READ,
+	EMC_FBIO_CFG5,
+	EMC_CFG_DIG_DLL,
+	EMC_CFG_DIG_DLL_PERIOD,
+	EMC_DLL_XFORM_DQS0,
+	EMC_DLL_XFORM_DQS1,
+	EMC_DLL_XFORM_DQS2,
+	EMC_DLL_XFORM_DQS3,
+	EMC_DLL_XFORM_DQS4,
+	EMC_DLL_XFORM_DQS5,
+	EMC_DLL_XFORM_DQS6,
+	EMC_DLL_XFORM_DQS7,
+	EMC_DLL_XFORM_QUSE0,
+	EMC_DLL_XFORM_QUSE1,
+	EMC_DLL_XFORM_QUSE2,
+	EMC_DLL_XFORM_QUSE3,
+	EMC_DLL_XFORM_QUSE4,
+	EMC_DLL_XFORM_QUSE5,
+	EMC_DLL_XFORM_QUSE6,
+	EMC_DLL_XFORM_QUSE7,
+	EMC_DLI_TRIM_TXDQS0,
+	EMC_DLI_TRIM_TXDQS1,
+	EMC_DLI_TRIM_TXDQS2,
+	EMC_DLI_TRIM_TXDQS3,
+	EMC_DLI_TRIM_TXDQS4,
+	EMC_DLI_TRIM_TXDQS5,
+	EMC_DLI_TRIM_TXDQS6,
+	EMC_DLI_TRIM_TXDQS7,
+	EMC_DLL_XFORM_DQ0,
+	EMC_DLL_XFORM_DQ1,
+	EMC_DLL_XFORM_DQ2,
+	EMC_DLL_XFORM_DQ3,
+	EMC_XM2CMDPADCTRL,
+	EMC_XM2CMDPADCTRL4,
+	EMC_XM2DQPADCTRL2,
+	EMC_XM2CLKPADCTRL,
+	EMC_XM2COMPPADCTRL,
+	EMC_XM2VTTGENPADCTRL,
+	EMC_XM2VTTGENPADCTRL2,
+	EMC_XM2DQSPADCTRL3,
+	EMC_XM2DQSPADCTRL4,
+	EMC_DSR_VTTGEN_DRV,
+	EMC_TXDSRVTTGEN,
+	EMC_FBIO_SPARE,
+	EMC_ZCAL_WAIT_CNT,
+	EMC_MRS_WAIT_CNT2,
+	EMC_CTT,
+	EMC_CTT_DURATION,
+	EMC_DYN_SELF_REF_CONTROL,
+};
+
+struct emc_timing {
+	unsigned long rate;
+
+	u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
+
+	u32 emc_auto_cal_config;
+	u32 emc_auto_cal_config2;
+	u32 emc_auto_cal_config3;
+	u32 emc_auto_cal_interval;
+	u32 emc_cfg;
+	u32 emc_ctt_term_ctrl;
+	u32 emc_mode_1;
+	u32 emc_mode_2;
+	u32 emc_mode_4;
+	u32 emc_mode_reset;
+	u32 emc_mrs_wait_cnt;
+	u32 emc_sel_dpd_ctrl;
+	u32 emc_xm2dqspadctrl2;
+	u32 emc_zcal_cnt_long;
+	u32 emc_zcal_interval;
+};
+
+enum emc_rate_request_type {
+	EMC_RATE_DEBUG,
+	EMC_RATE_ICC,
+	EMC_RATE_TYPE_MAX,
+};
+
+struct emc_rate_request {
+	unsigned long min_rate;
+	unsigned long max_rate;
+};
+
+struct tegra_emc {
+	struct device *dev;
+	struct tegra_mc *mc;
+	void __iomem *regs;
+	unsigned int irq;
+	struct clk *clk;
+
+	enum emc_dram_type dram_type;
+	unsigned int dram_num;
+
+	struct emc_timing last_timing;
+	struct emc_timing *timings;
+	unsigned int num_timings;
+
+	struct {
+		struct dentry *root;
+		unsigned long min_rate;
+		unsigned long max_rate;
+	} debugfs;
+
+	struct icc_provider provider;
+
+	/*
+	 * There are multiple sources in the EMC driver which could request
+	 * a min/max clock rate, these rates are contained in this array.
+	 */
+	struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
+
+	/* protect shared rate-change code path */
+	struct mutex rate_lock;
+};
+
+static irqreturn_t tegra_emc_isr(int irq, void *data)
+{
+	struct tegra_emc *emc = data;
+	u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW;
+	u32 status;
+
+	status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
+	if (!status)
+		return IRQ_NONE;
+
+	/* notify about HW problem */
+	if (status & EMC_INTSTATUS_REFRESH_OVERFLOW)
+		dev_err_ratelimited(emc->dev,
+				    "refresh request overflow timeout\n");
+
+	/* clear interrupts */
+	writel_relaxed(status, emc->regs + EMC_INTSTATUS);
+
+	return IRQ_HANDLED;
+}
+
+/* Timing change sequence functions */
+
+static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
+			      unsigned long offset)
+{
+	writel(value, emc->regs + EMC_CCFIFO_DATA);
+	writel(offset, emc->regs + EMC_CCFIFO_ADDR);
+}
+
+static void emc_seq_update_timing(struct tegra_emc *emc)
+{
+	int ret;
+	u32 value;
+
+	writel(1, emc->regs + EMC_TIMING_CONTROL);
+
+	ret = readl_poll_timeout_atomic(emc->regs + EMC_STATUS, value,
+					!(value & EMC_STATUS_TIMING_UPDATE_STALLED),
+					1, EMC_STATUS_UPDATE_TIMEOUT);
+	if (ret)
+		dev_err(emc->dev, "timing update timed out\n");
+}
+
+static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
+{
+	int ret;
+	u32 value;
+
+	writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
+
+	ret = readl_poll_timeout_atomic(emc->regs + EMC_AUTO_CAL_STATUS, value,
+					!(value & EMC_AUTO_CAL_STATUS_ACTIVE),
+					1, EMC_STATUS_UPDATE_TIMEOUT);
+	if (ret)
+		dev_err(emc->dev, "auto cal disable timed out\n");
+}
+
+static void emc_seq_wait_clkchange(struct tegra_emc *emc)
+{
+	int ret;
+	u32 value;
+
+	ret = readl_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, value,
+					value & EMC_INTSTATUS_CLKCHANGE_COMPLETE,
+					1, EMC_STATUS_UPDATE_TIMEOUT);
+	if (ret)
+		dev_err(emc->dev, "clock change timed out\n");
+}
+
+static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
+						unsigned long rate)
+{
+	struct emc_timing *timing = NULL;
+	unsigned int i;
+
+	for (i = 0; i < emc->num_timings; i++) {
+		if (emc->timings[i].rate == rate) {
+			timing = &emc->timings[i];
+			break;
+		}
+	}
+
+	if (!timing) {
+		dev_err(emc->dev, "no timing for rate %lu\n", rate);
+		return NULL;
+	}
+
+	return timing;
+}
+
+static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
+					   unsigned long rate)
+{
+	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
+	struct emc_timing *last = &emc->last_timing;
+	enum emc_dll_change dll_change;
+	unsigned int pre_wait = 0;
+	u32 val, mask;
+	bool next_dll_enabled = !(timing->emc_mode_1 & 0x1);
+	bool last_dll_enabled = !(last->emc_mode_1 & 0x1);
+	bool update = false;
+	unsigned int i;
+
+	if (!timing)
+		return -ENOENT;
+
+	if (next_dll_enabled == last_dll_enabled)
+		dll_change = DLL_CHANGE_NONE;
+	else if (next_dll_enabled)
+		dll_change = DLL_CHANGE_ON;
+	else
+		dll_change = DLL_CHANGE_OFF;
+
+	/* Clear CLKCHANGE_COMPLETE interrupts */
+	writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
+
+	/* Disable dynamic self-refresh */
+	val = readl(emc->regs + EMC_CFG);
+	if (val & EMC_CFG_PWR_MASK) {
+		val &= ~EMC_CFG_POWER_FEATURES_MASK;
+		writel(val, emc->regs + EMC_CFG);
+
+		pre_wait = 5;
+	}
+
+	/* Disable SEL_DPD_CTRL for clock change */
+	if (emc->dram_type == DRAM_TYPE_DDR3)
+		mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
+	else
+		mask = EMC_SEL_DPD_CTRL_MASK;
+
+	val = readl(emc->regs + EMC_SEL_DPD_CTRL);
+	if (val & mask) {
+		val &= ~mask;
+		writel(val, emc->regs + EMC_SEL_DPD_CTRL);
+	}
+
+	/* Prepare DQ/DQS for clock change */
+	val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
+	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
+	    !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
+		val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
+		update = true;
+	}
+
+	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
+	    !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
+		val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
+		update = true;
+	}
+
+	if (update) {
+		writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
+		if (pre_wait < 30)
+			pre_wait = 30;
+	}
+
+	/* Wait to settle */
+	if (pre_wait) {
+		emc_seq_update_timing(emc);
+		udelay(pre_wait);
+	}
+
+	/* Program CTT_TERM control */
+	if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
+		emc_seq_disable_auto_cal(emc);
+		writel(timing->emc_ctt_term_ctrl,
+		       emc->regs + EMC_CTT_TERM_CTRL);
+		emc_seq_update_timing(emc);
+	}
+
+	/* Program burst shadow registers */
+	for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
+		writel(timing->emc_burst_data[i],
+		       emc->regs + emc_burst_regs[i]);
+
+	writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
+	writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
+
+	tegra_mc_write_emem_configuration(emc->mc, timing->rate);
+
+	val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
+	emc_ccfifo_writel(emc, val, EMC_CFG);
+
+	/* Program AUTO_CAL_CONFIG */
+	if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
+		emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
+				  EMC_AUTO_CAL_CONFIG2);
+
+	if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
+		emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
+				  EMC_AUTO_CAL_CONFIG3);
+
+	if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
+		val = timing->emc_auto_cal_config;
+		val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
+		emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
+	}
+
+	/* DDR3: predict MRS long wait count */
+	if (emc->dram_type == DRAM_TYPE_DDR3 &&
+	    dll_change == DLL_CHANGE_ON) {
+		u32 cnt = 512;
+
+		if (timing->emc_zcal_interval != 0 &&
+		    last->emc_zcal_interval == 0)
+			cnt -= emc->dram_num * 256;
+
+		val = (timing->emc_mrs_wait_cnt
+			& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
+			>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
+		if (cnt < val)
+			cnt = val;
+
+		val = timing->emc_mrs_wait_cnt
+			& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
+		val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
+			& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
+
+		writel(val, emc->regs + EMC_MRS_WAIT_CNT);
+	}
+
+	/* DDR3: Turn off DLL and enter self-refresh */
+	if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
+		emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
+
+	/* Disable refresh controller */
+	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
+			  EMC_REFCTRL);
+	if (emc->dram_type == DRAM_TYPE_DDR3)
+		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
+				       EMC_SELF_REF_CMD_ENABLED,
+				  EMC_SELF_REF);
+
+	/* Flow control marker */
+	emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
+
+	/* DDR3: Exit self-refresh */
+	if (emc->dram_type == DRAM_TYPE_DDR3)
+		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
+				  EMC_SELF_REF);
+	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
+			       EMC_REFCTRL_ENABLE,
+			  EMC_REFCTRL);
+
+	/* Set DRAM mode registers */
+	if (emc->dram_type == DRAM_TYPE_DDR3) {
+		if (timing->emc_mode_1 != last->emc_mode_1)
+			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
+		if (timing->emc_mode_2 != last->emc_mode_2)
+			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
+
+		if (timing->emc_mode_reset != last->emc_mode_reset ||
+		    dll_change == DLL_CHANGE_ON) {
+			val = timing->emc_mode_reset;
+			if (dll_change == DLL_CHANGE_ON) {
+				val |= EMC_MODE_SET_DLL_RESET;
+				val |= EMC_MODE_SET_LONG_CNT;
+			} else {
+				val &= ~EMC_MODE_SET_DLL_RESET;
+			}
+			emc_ccfifo_writel(emc, val, EMC_MRS);
+		}
+	} else {
+		if (timing->emc_mode_2 != last->emc_mode_2)
+			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
+		if (timing->emc_mode_1 != last->emc_mode_1)
+			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
+		if (timing->emc_mode_4 != last->emc_mode_4)
+			emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
+	}
+
+	/*  Issue ZCAL command if turning ZCAL on */
+	if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
+		emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
+		if (emc->dram_num > 1)
+			emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
+					  EMC_ZQ_CAL);
+	}
+
+	/*  Write to RO register to remove stall after change */
+	emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
+
+	/* Disable AUTO_CAL for clock change */
+	emc_seq_disable_auto_cal(emc);
+
+	/* Read register to wait until programming has settled */
+	mc_readl(emc->mc, MC_EMEM_ADR_CFG);
+
+	return 0;
+}
+
+static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
+					     unsigned long rate)
+{
+	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
+	struct emc_timing *last = &emc->last_timing;
+
+	if (!timing)
+		return;
+
+	/* Wait until the state machine has settled */
+	emc_seq_wait_clkchange(emc);
+
+	/* Restore AUTO_CAL */
+	if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
+		writel(timing->emc_auto_cal_interval,
+		       emc->regs + EMC_AUTO_CAL_INTERVAL);
+
+	/* Restore dynamic self-refresh */
+	if (timing->emc_cfg & EMC_CFG_PWR_MASK)
+		writel(timing->emc_cfg, emc->regs + EMC_CFG);
+
+	/* Set ZCAL wait count */
+	writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
+
+	/* Wait for timing to settle */
+	udelay(2);
+
+	/* Reprogram SEL_DPD_CTRL */
+	writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
+	emc_seq_update_timing(emc);
+
+	emc->last_timing = *timing;
+}
+
+/* Initialization and deinitialization */
+
+static void emc_read_current_timing(struct tegra_emc *emc,
+				    struct emc_timing *timing)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
+		timing->emc_burst_data[i] =
+			readl(emc->regs + emc_burst_regs[i]);
+
+	timing->emc_cfg = readl(emc->regs + EMC_CFG);
+
+	timing->emc_auto_cal_interval = 0;
+	timing->emc_zcal_cnt_long = 0;
+	timing->emc_mode_1 = 0;
+	timing->emc_mode_2 = 0;
+	timing->emc_mode_4 = 0;
+	timing->emc_mode_reset = 0;
+}
+
+static int emc_init(struct tegra_emc *emc)
+{
+	u32 emc_cfg, emc_dbg;
+	u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW;
+	const char *dram_type_str;
+
+	emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
+
+	emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
+	emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
+
+	emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
+
+	emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
+
+	/* enable EMC and CAR to handshake on PLL divider/source changes */
+	emc_cfg |= EMC_CFG_2_CLKCHANGE_REQ_ENABLE;
+
+	/* configure clock change mode accordingly to DRAM type */
+	if (emc->dram_type == DRAM_TYPE_LPDDR2)
+		emc_cfg |= EMC_CFG_2_CLKCHANGE_PD_ENABLE;
+	else
+		emc_cfg &= ~EMC_CFG_2_CLKCHANGE_PD_ENABLE;
+
+	writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
+
+	/* initialize interrupt */
+	writel_relaxed(intmask, emc->regs + EMC_INTMASK);
+	writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
+
+	/* ensure that unwanted debug features are disabled */
+	emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
+	emc_dbg |= EMC_DBG_CFG_PRIORITY;
+	emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
+	emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
+	emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
+	writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
+
+	switch (emc->dram_type) {
+	case DRAM_TYPE_DDR1:
+		dram_type_str = "DDR1";
+		break;
+	case DRAM_TYPE_LPDDR2:
+		dram_type_str = "LPDDR2";
+		break;
+	case DRAM_TYPE_DDR2:
+		dram_type_str = "DDR2";
+		break;
+	case DRAM_TYPE_DDR3:
+		dram_type_str = "DDR3";
+		break;
+	}
+
+	dev_info_once(emc->dev, "%u %s %s attached\n", emc->dram_num,
+		      dram_type_str, emc->dram_num == 2 ? "devices" : "device");
+
+	emc_read_current_timing(emc, &emc->last_timing);
+
+	return 0;
+}
+
+static int load_one_timing_from_dt(struct tegra_emc *emc,
+				   struct emc_timing *timing,
+				   struct device_node *node)
+{
+	u32 value;
+	int err;
+
+	err = of_property_read_u32(node, "clock-frequency", &value);
+	if (err) {
+		dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
+			node, err);
+		return err;
+	}
+
+	timing->rate = value;
+
+	err = of_property_read_u32_array(node, "nvidia,emc-configuration",
+					 timing->emc_burst_data,
+					 ARRAY_SIZE(timing->emc_burst_data));
+	if (err) {
+		dev_err(emc->dev,
+			"timing %pOFn: failed to read emc burst data: %d\n",
+			node, err);
+		return err;
+	}
+
+#define EMC_READ_PROP(prop, dtprop) { \
+	err = of_property_read_u32(node, dtprop, &timing->prop); \
+	if (err) { \
+		dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
+			node, err); \
+		return err; \
+	} \
+}
+
+	EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
+	EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
+	EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
+	EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
+	EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
+	EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
+	EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
+	EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
+	EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
+	EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
+	EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
+	EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
+	EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
+	EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
+	EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
+
+#undef EMC_READ_PROP
+
+	return 0;
+}
+
+static int cmp_timings(const void *_a, const void *_b)
+{
+	const struct emc_timing *a = _a;
+	const struct emc_timing *b = _b;
+
+	if (a->rate < b->rate)
+		return -1;
+	else if (a->rate == b->rate)
+		return 0;
+	else
+		return 1;
+}
+
+static int emc_check_mc_timings(struct tegra_emc *emc)
+{
+	struct tegra_mc *mc = emc->mc;
+	unsigned int i;
+
+	if (emc->num_timings != mc->num_timings) {
+		dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
+			emc->num_timings, mc->num_timings);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < mc->num_timings; i++) {
+		if (emc->timings[i].rate != mc->timings[i].rate) {
+			dev_err(emc->dev,
+				"emc/mc timing rate mismatch: %lu %lu\n",
+				emc->timings[i].rate, mc->timings[i].rate);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
+					  struct device_node *node)
+{
+	int child_count = of_get_child_count(node);
+	struct emc_timing *timing;
+	unsigned int i = 0;
+	int err;
+
+	emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
+				    GFP_KERNEL);
+	if (!emc->timings)
+		return -ENOMEM;
+
+	emc->num_timings = child_count;
+
+	for_each_child_of_node_scoped(node, child) {
+		timing = &emc->timings[i++];
+
+		err = load_one_timing_from_dt(emc, timing, child);
+		if (err)
+			return err;
+	}
+
+	sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
+	     NULL);
+
+	err = emc_check_mc_timings(emc);
+	if (err)
+		return err;
+
+	dev_info_once(emc->dev,
+		      "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
+		      emc->num_timings,
+		      tegra_read_ram_code(),
+		      emc->timings[0].rate / 1000000,
+		      emc->timings[emc->num_timings - 1].rate / 1000000);
+
+	return 0;
+}
+
+static struct device_node *
+tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
+{
+	struct device_node *np;
+	int err;
+
+	for_each_child_of_node(node, np) {
+		u32 value;
+
+		err = of_property_read_u32(np, "nvidia,ram-code", &value);
+		if (err || value != ram_code)
+			continue;
+
+		return np;
+	}
+
+	return NULL;
+}
+
+static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
+{
+	unsigned int i;
+
+	for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
+		emc->requested_rate[i].min_rate = 0;
+		emc->requested_rate[i].max_rate = ULONG_MAX;
+	}
+}
+
+static int emc_request_rate(struct tegra_emc *emc,
+			    unsigned long new_min_rate,
+			    unsigned long new_max_rate,
+			    enum emc_rate_request_type type)
+{
+	struct emc_rate_request *req = emc->requested_rate;
+	unsigned long min_rate = 0, max_rate = ULONG_MAX;
+	unsigned int i;
+	int err;
+
+	/* select minimum and maximum rates among the requested rates */
+	for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
+		if (i == type) {
+			min_rate = max(new_min_rate, min_rate);
+			max_rate = min(new_max_rate, max_rate);
+		} else {
+			min_rate = max(req->min_rate, min_rate);
+			max_rate = min(req->max_rate, max_rate);
+		}
+	}
+
+	if (min_rate > max_rate) {
+		dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
+				    __func__, type, min_rate, max_rate);
+		return -ERANGE;
+	}
+
+	/*
+	 * EMC rate-changes should go via OPP API because it manages voltage
+	 * changes.
+	 */
+	err = dev_pm_opp_set_rate(emc->dev, min_rate);
+	if (err)
+		return err;
+
+	emc->requested_rate[type].min_rate = new_min_rate;
+	emc->requested_rate[type].max_rate = new_max_rate;
+
+	return 0;
+}
+
+static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
+			    enum emc_rate_request_type type)
+{
+	struct emc_rate_request *req = &emc->requested_rate[type];
+	int ret;
+
+	mutex_lock(&emc->rate_lock);
+	ret = emc_request_rate(emc, rate, req->max_rate, type);
+	mutex_unlock(&emc->rate_lock);
+
+	return ret;
+}
+
+static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
+			    enum emc_rate_request_type type)
+{
+	struct emc_rate_request *req = &emc->requested_rate[type];
+	int ret;
+
+	mutex_lock(&emc->rate_lock);
+	ret = emc_request_rate(emc, req->min_rate, rate, type);
+	mutex_unlock(&emc->rate_lock);
+
+	return ret;
+}
+
+/*
+ * debugfs interface
+ *
+ * The memory controller driver exposes some files in debugfs that can be used
+ * to control the EMC frequency. The top-level directory can be found here:
+ *
+ *   /sys/kernel/debug/emc
+ *
+ * It contains the following files:
+ *
+ *   - available_rates: This file contains a list of valid, space-separated
+ *     EMC frequencies.
+ *
+ *   - min_rate: Writing a value to this file sets the given frequency as the
+ *       floor of the permitted range. If this is higher than the currently
+ *       configured EMC frequency, this will cause the frequency to be
+ *       increased so that it stays within the valid range.
+ *
+ *   - max_rate: Similarly to the min_rate file, writing a value to this file
+ *       sets the given frequency as the ceiling of the permitted range. If
+ *       the value is lower than the currently configured EMC frequency, this
+ *       will cause the frequency to be decreased so that it stays within the
+ *       valid range.
+ */
+
+static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
+{
+	unsigned int i;
+
+	for (i = 0; i < emc->num_timings; i++)
+		if (rate == emc->timings[i].rate)
+			return true;
+
+	return false;
+}
+
+static int tegra_emc_debug_available_rates_show(struct seq_file *s,
+						void *data)
+{
+	struct tegra_emc *emc = s->private;
+	const char *prefix = "";
+	unsigned int i;
+
+	for (i = 0; i < emc->num_timings; i++) {
+		seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
+		prefix = " ";
+	}
+
+	seq_puts(s, "\n");
+
+	return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
+
+static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
+{
+	struct tegra_emc *emc = data;
+
+	*rate = emc->debugfs.min_rate;
+
+	return 0;
+}
+
+static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
+{
+	struct tegra_emc *emc = data;
+	int err;
+
+	if (!tegra_emc_validate_rate(emc, rate))
+		return -EINVAL;
+
+	err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
+	if (err < 0)
+		return err;
+
+	emc->debugfs.min_rate = rate;
+
+	return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
+			 tegra_emc_debug_min_rate_get,
+			 tegra_emc_debug_min_rate_set, "%llu\n");
+
+static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
+{
+	struct tegra_emc *emc = data;
+
+	*rate = emc->debugfs.max_rate;
+
+	return 0;
+}
+
+static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
+{
+	struct tegra_emc *emc = data;
+	int err;
+
+	if (!tegra_emc_validate_rate(emc, rate))
+		return -EINVAL;
+
+	err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
+	if (err < 0)
+		return err;
+
+	emc->debugfs.max_rate = rate;
+
+	return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
+			 tegra_emc_debug_max_rate_get,
+			 tegra_emc_debug_max_rate_set, "%llu\n");
+
+static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
+{
+	unsigned int i;
+	int err;
+
+	emc->debugfs.min_rate = ULONG_MAX;
+	emc->debugfs.max_rate = 0;
+
+	for (i = 0; i < emc->num_timings; i++) {
+		if (emc->timings[i].rate < emc->debugfs.min_rate)
+			emc->debugfs.min_rate = emc->timings[i].rate;
+
+		if (emc->timings[i].rate > emc->debugfs.max_rate)
+			emc->debugfs.max_rate = emc->timings[i].rate;
+	}
+
+	if (!emc->num_timings) {
+		emc->debugfs.min_rate = clk_get_rate(emc->clk);
+		emc->debugfs.max_rate = emc->debugfs.min_rate;
+	}
+
+	err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
+				 emc->debugfs.max_rate);
+	if (err < 0) {
+		dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
+			emc->debugfs.min_rate, emc->debugfs.max_rate,
+			emc->clk);
+		return;
+	}
+
+	emc->debugfs.root = debugfs_create_dir("emc", NULL);
+
+	debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
+			    &tegra_emc_debug_available_rates_fops);
+	debugfs_create_file("min_rate", 0644, emc->debugfs.root,
+			    emc, &tegra_emc_debug_min_rate_fops);
+	debugfs_create_file("max_rate", 0644, emc->debugfs.root,
+			    emc, &tegra_emc_debug_max_rate_fops);
+}
+
+static inline struct tegra_emc *
+to_tegra_emc_provider(struct icc_provider *provider)
+{
+	return container_of(provider, struct tegra_emc, provider);
+}
+
+static struct icc_node_data *
+emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
+{
+	struct icc_provider *provider = data;
+	struct icc_node_data *ndata;
+	struct icc_node *node;
+
+	/* External Memory is the only possible ICC route */
+	list_for_each_entry(node, &provider->nodes, node_list) {
+		if (node->id != TEGRA_ICC_EMEM)
+			continue;
+
+		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
+		if (!ndata)
+			return ERR_PTR(-ENOMEM);
+
+		/*
+		 * SRC and DST nodes should have matching TAG in order to have
+		 * it set by default for a requested path.
+		 */
+		ndata->tag = TEGRA_MC_ICC_TAG_ISO;
+		ndata->node = node;
+
+		return ndata;
+	}
+
+	return ERR_PTR(-EPROBE_DEFER);
+}
+
+static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
+	unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
+	unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
+	unsigned long long rate = max(avg_bw, peak_bw);
+	unsigned int dram_data_bus_width_bytes = 4;
+	const unsigned int ddr = 2;
+	int err;
+
+	/*
+	 * Tegra114 EMC runs on a clock rate of SDRAM bus. This means that
+	 * EMC clock rate is twice smaller than the peak data rate because
+	 * data is sampled on both EMC clock edges.
+	 */
+	do_div(rate, ddr * dram_data_bus_width_bytes);
+	rate = min_t(u64, rate, U32_MAX);
+
+	err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int tegra_emc_interconnect_init(struct tegra_emc *emc)
+{
+	const struct tegra_mc_soc *soc = emc->mc->soc;
+	struct icc_node *node;
+	int err;
+
+	emc->provider.dev = emc->dev;
+	emc->provider.set = emc_icc_set;
+	emc->provider.data = &emc->provider;
+	emc->provider.aggregate = soc->icc_ops->aggregate;
+	emc->provider.xlate_extended = emc_of_icc_xlate_extended;
+
+	icc_provider_init(&emc->provider);
+
+	/* create External Memory Controller node */
+	node = icc_node_create(TEGRA_ICC_EMC);
+	if (IS_ERR(node)) {
+		err = PTR_ERR(node);
+		goto err_msg;
+	}
+
+	node->name = "External Memory Controller";
+	icc_node_add(node, &emc->provider);
+
+	/* link External Memory Controller to External Memory (DRAM) */
+	err = icc_link_create(node, TEGRA_ICC_EMEM);
+	if (err)
+		goto remove_nodes;
+
+	/* create External Memory node */
+	node = icc_node_create(TEGRA_ICC_EMEM);
+	if (IS_ERR(node)) {
+		err = PTR_ERR(node);
+		goto remove_nodes;
+	}
+
+	node->name = "External Memory (DRAM)";
+	icc_node_add(node, &emc->provider);
+
+	err = icc_provider_register(&emc->provider);
+	if (err)
+		goto remove_nodes;
+
+	return 0;
+
+remove_nodes:
+	icc_nodes_remove(&emc->provider);
+err_msg:
+	dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
+
+	return err;
+}
+
+static void devm_tegra_emc_unset_callback(void *data)
+{
+	tegra124_clk_set_emc_callbacks(NULL, NULL);
+}
+
+static int tegra_emc_probe(struct platform_device *pdev)
+{
+	struct tegra_core_opp_params opp_params = {};
+	struct device_node *np;
+	struct tegra_emc *emc;
+	u32 ram_code;
+	int err;
+
+	emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
+	if (!emc)
+		return -ENOMEM;
+
+	mutex_init(&emc->rate_lock);
+	emc->dev = &pdev->dev;
+
+	emc->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(emc->regs))
+		return PTR_ERR(emc->regs);
+
+	emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
+	if (IS_ERR(emc->mc))
+		return PTR_ERR(emc->mc);
+
+	ram_code = tegra_read_ram_code();
+
+	np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
+	if (np) {
+		err = tegra_emc_load_timings_from_dt(emc, np);
+		of_node_put(np);
+		if (err)
+			return err;
+	} else {
+		dev_info_once(&pdev->dev,
+			      "no memory timings for RAM code %u found in DT\n",
+			      ram_code);
+	}
+
+	err = emc_init(emc);
+	if (err) {
+		dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
+		return err;
+	}
+
+	platform_set_drvdata(pdev, emc);
+
+	tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
+				       tegra_emc_complete_timing_change);
+
+	err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback,
+				       NULL);
+	if (err)
+		return err;
+
+	err = platform_get_irq(pdev, 0);
+	if (err < 0)
+		return err;
+
+	emc->irq = err;
+
+	err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
+			       dev_name(&pdev->dev), emc);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request irq: %d\n", err);
+		return err;
+	}
+
+	emc->clk = devm_clk_get(&pdev->dev, "emc");
+	if (IS_ERR(emc->clk)) {
+		err = PTR_ERR(emc->clk);
+		dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
+		return err;
+	}
+
+	opp_params.init_state = true;
+
+	err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
+	if (err)
+		return err;
+
+	tegra_emc_rate_requests_init(emc);
+
+	if (IS_ENABLED(CONFIG_DEBUG_FS))
+		emc_debugfs_init(&pdev->dev, emc);
+
+	tegra_emc_interconnect_init(emc);
+
+	/*
+	 * Don't allow the kernel module to be unloaded. Unloading adds some
+	 * extra complexity which doesn't really worth the effort in a case of
+	 * this driver.
+	 */
+	try_module_get(THIS_MODULE);
+
+	return 0;
+};
+
+static const struct of_device_id tegra_emc_of_match[] = {
+	{ .compatible = "nvidia,tegra114-emc" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
+
+static struct platform_driver tegra_emc_driver = {
+	.probe = tegra_emc_probe,
+	.driver = {
+		.name = "tegra114-emc",
+		.of_match_table = tegra_emc_of_match,
+		.suppress_bind_attrs = true,
+		.sync_state = icc_sync_state,
+	},
+};
+module_platform_driver(tegra_emc_driver);
+
+MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra114 EMC driver");
+MODULE_LICENSE("GPL");
-- 
2.51.0

[PATCH v4 10/12] ARM: tegra: Add External Memory Controller node on Tegra114

[Svyatoslav Ryhel]

Add External Memory Controller node to the device-tree.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra114.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index ef0618e9eec1..a920ad041c14 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -259,6 +259,8 @@ tegra_car: clock@60006000 {
 		reg = <0x60006000 0x1000>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
+
+		nvidia,external-memory-controller = <&emc>;
 	};
 
 	flow-controller@60007000 {
@@ -655,6 +657,16 @@ mc: memory-controller@70019000 {
 		#iommu-cells = <1>;
 	};
 
+	emc: external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra114-emc";
+		reg = <0x7001b000 0x1000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA114_CLK_EMC>;
+		clock-names = "emc";
+
+		nvidia,memory-controller = <&mc>;
+	};
+
 	hda@70030000 {
 		compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda";
 		reg = <0x70030000 0x10000>;
-- 
2.51.0

[PATCH v4 11/12] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes

[Svyatoslav Ryhel]

Add EMC OPP tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 151 ++++++++++++++++++
 arch/arm/boot/dts/nvidia/tegra114.dtsi        |   9 ++
 2 files changed, 160 insertions(+)
 create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi

diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
new file mode 100644
index 000000000000..1a0e68f22039
--- /dev/null
+++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+	emc_icc_dvfs_opp_table: opp-table-emc {
+		compatible = "operating-points-v2";
+
+		opp-12750000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <12750000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-20400000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <20400000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-40800000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <40800000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-68000000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <68000000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-102000000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <102000000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-204000000-900 {
+			opp-microvolt = <900000 900000 1390000>;
+			opp-hz = /bits/ 64 <204000000>;
+			opp-supported-hw = <0x000F>;
+			opp-suspend;
+		};
+
+		opp-312000000-1000 {
+			opp-microvolt = <1000000 1000000 1390000>;
+			opp-hz = /bits/ 64 <312000000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-408000000-1000 {
+			opp-microvolt = <1000000 1000000 1390000>;
+			opp-hz = /bits/ 64 <408000000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-528000000-1050 {
+			opp-microvolt = <1050000 1050000 1390000>;
+			opp-hz = /bits/ 64 <528000000>;
+			opp-supported-hw = <0x000E>;
+		};
+
+		opp-528000000-1100 {
+			opp-microvolt = <1100000 1100000 1390000>;
+			opp-hz = /bits/ 64 <528000000>;
+			opp-supported-hw = <0x0001>;
+		};
+
+		opp-624000000-1100 {
+			opp-microvolt = <1100000 1100000 1390000>;
+			opp-hz = /bits/ 64 <624000000>;
+			opp-supported-hw = <0x000F>;
+		};
+
+		opp-792000000-1100 {
+			opp-microvolt = <1100000 1100000 1390000>;
+			opp-hz = /bits/ 64 <792000000>;
+			opp-supported-hw = <0x000F>;
+		};
+	};
+
+	emc_bw_dfs_opp_table: opp-table-actmon {
+		compatible = "operating-points-v2";
+
+		opp-12750000 {
+			opp-hz = /bits/ 64 <12750000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <204000>;
+		};
+
+		opp-20400000 {
+			opp-hz = /bits/ 64 <20400000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <326400>;
+		};
+
+		opp-40800000 {
+			opp-hz = /bits/ 64 <40800000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <652800>;
+		};
+
+		opp-68000000 {
+			opp-hz = /bits/ 64 <68000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <1088000>;
+		};
+
+		opp-102000000 {
+			opp-hz = /bits/ 64 <102000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <1632000>;
+		};
+
+		opp-204000000 {
+			opp-hz = /bits/ 64 <204000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <3264000>;
+			opp-suspend;
+		};
+
+		opp-312000000 {
+			opp-hz = /bits/ 64 <312000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <4992000>;
+		};
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <6528000>;
+		};
+
+		opp-528000000 {
+			opp-hz = /bits/ 64 <528000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <8448000>;
+		};
+
+		opp-624000000 {
+			opp-hz = /bits/ 64 <624000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <9984000>;
+		};
+
+		opp-792000000 {
+			opp-hz = /bits/ 64 <792000000>;
+			opp-supported-hw = <0x000F>;
+			opp-peak-kBps = <12672000>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index a920ad041c14..6221423b81d1 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -8,6 +8,8 @@
 #include <dt-bindings/soc/tegra-pmc.h>
 #include <dt-bindings/thermal/tegra114-soctherm.h>
 
+#include "tegra114-peripherals-opp.dtsi"
+
 / {
 	compatible = "nvidia,tegra114";
 	interrupt-parent = <&lic>;
@@ -323,6 +325,9 @@ actmon: actmon@6000c800 {
 		clock-names = "actmon", "emc";
 		resets = <&tegra_car TEGRA114_CLK_ACTMON>;
 		reset-names = "actmon";
+		operating-points-v2 = <&emc_bw_dfs_opp_table>;
+		interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
+		interconnect-names = "cpu-read";
 		#cooling-cells = <2>;
 	};
 
@@ -655,6 +660,7 @@ mc: memory-controller@70019000 {
 
 		#reset-cells = <1>;
 		#iommu-cells = <1>;
+		#interconnect-cells = <1>;
 	};
 
 	emc: external-memory-controller@7001b000 {
@@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 {
 		clock-names = "emc";
 
 		nvidia,memory-controller = <&mc>;
+		operating-points-v2 = <&emc_icc_dvfs_opp_table>;
+
+		#interconnect-cells = <0>;
 	};
 
 	hda@70030000 {
-- 
2.51.0

[PATCH v4 12/12] ARM: tegra: add DC interconnections for Tegra114

[Svyatoslav Ryhel]

Add DC interconnections to Tegra114 device tree to reflect connections
between MC, EMC and DC.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
 arch/arm/boot/dts/nvidia/tegra114.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 6221423b81d1..732f8b5b4eed 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -125,6 +125,17 @@ dc@54200000 {
 
 			nvidia,head = <0>;
 
+			interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>,
+					<&mc TEGRA114_MC_DISPLAY0B &emc>,
+					<&mc TEGRA114_MC_DISPLAY1B &emc>,
+					<&mc TEGRA114_MC_DISPLAY0C &emc>,
+					<&mc TEGRA114_MC_DISPLAYHC &emc>;
+			interconnect-names = "wina",
+					     "winb",
+					     "winb-vfilter",
+					     "winc",
+					     "cursor";
+
 			rgb {
 				status = "disabled";
 			};
@@ -144,6 +155,17 @@ dc@54240000 {
 
 			nvidia,head = <1>;
 
+			interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>,
+					<&mc TEGRA114_MC_DISPLAY0BB &emc>,
+					<&mc TEGRA114_MC_DISPLAY1BB &emc>,
+					<&mc TEGRA114_MC_DISPLAY0CB &emc>,
+					<&mc TEGRA114_MC_DISPLAYHCB &emc>;
+			interconnect-names = "wina",
+					     "winb",
+					     "winb-vfilter",
+					     "winc",
+					     "cursor";
+
 			rgb {
 				status = "disabled";
 			};
-- 
2.51.0

Re: [PATCH v4 00/12] Tegra114: implement EMC support

[Krzysztof Kozlowski]

On 25/11/2025 13:05, Svyatoslav Ryhel wrote:
> Add support for External Memory Controller found in Tegra 4 SoC along
> with adjustments required for it to work properly.
> 
> Tested on ASUS TF701T (T40X) and Nvidia Tegratab (T40S). Both work fine.

You mixed here FOUR independent subsystems and without any explanation
of the dependencies it means things are just harder for us to handle for
no reason.

Please split independent subsystems or clearly document the merging
issues/dependencies.

Best regards,
Krzysztof

Re: [PATCH v4 00/12] Tegra114: implement EMC support

[Svyatoslav Ryhel]

ср, 26 лист. 2025 р. о 10:47 Krzysztof Kozlowski <krzk@kernel.org> пише:
>
> On 25/11/2025 13:05, Svyatoslav Ryhel wrote:
> > Add support for External Memory Controller found in Tegra 4 SoC along
> > with adjustments required for it to work properly.
> >
> > Tested on ASUS TF701T (T40X) and Nvidia Tegratab (T40S). Both work fine.
>
> You mixed here FOUR independent subsystems and without any explanation
> of the dependencies it means things are just harder for us to handle for
> no reason.
>
> Please split independent subsystems or clearly document the merging
> issues/dependencies.
>

All commits are independent and subsystem maintainers can pick commits
which are relevant for their domain. No regressions at the build time
nor on the device itself were detected with individual commits picked.
Only device tree changes are preferred to be picked last.

Patchset is made this way to show logic of implementation of EMC
support for Tegra114 since a list of links between fragmented
patchsets will not bring clarity nor it will improve merging
experience.

> Best regards,
> Krzysztof

Re: [PATCH v4 00/12] Tegra114: implement EMC support

[Krzysztof Kozlowski]

On 01/12/2025 07:12, Svyatoslav Ryhel wrote:
> ср, 26 лист. 2025 р. о 10:47 Krzysztof Kozlowski <krzk@kernel.org> пише:
>>
>> On 25/11/2025 13:05, Svyatoslav Ryhel wrote:
>>> Add support for External Memory Controller found in Tegra 4 SoC along
>>> with adjustments required for it to work properly.
>>>
>>> Tested on ASUS TF701T (T40X) and Nvidia Tegratab (T40S). Both work fine.
>>
>> You mixed here FOUR independent subsystems and without any explanation
>> of the dependencies it means things are just harder for us to handle for
>> no reason.
>>
>> Please split independent subsystems or clearly document the merging
>> issues/dependencies.
>>
> 
> All commits are independent and subsystem maintainers can pick commits
> which are relevant for their domain. No regressions at the build time
> nor on the device itself were detected with individual commits picked.
> Only device tree changes are preferred to be picked last.
> 
> Patchset is made this way to show logic of implementation of EMC
> support for Tegra114 since a list of links between fragmented
> patchsets will not bring clarity nor it will improve merging
> experience.

This is clearly not true statement and it is not you who will merged
that. Instead of just applying it with one command, maintainers will
have to use several to find/pick up individual bits.

You received comment, I expect implementing it. I am not going through
this patchset.

Best regards,
Krzysztof

Re: [PATCH v4 03/12] dt-bindings: memory: Document Tegra114 Memory Controller

[Rob Herring (Arm)]

On Tue, 25 Nov 2025 14:05:50 +0200, Svyatoslav Ryhel wrote:
> Add Tegra114 support into existing Tegra124 MC schema with the most
> notable difference in the amount of EMEM timings.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  .../nvidia,tegra124-mc.yaml                   | 31 +++++--------------
>  1 file changed, 8 insertions(+), 23 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v4 07/12] dt-bindings: memory: Document Tegra114 External Memory Controller

[Rob Herring (Arm)]

On Tue, 25 Nov 2025 14:05:54 +0200, Svyatoslav Ryhel wrote:
> Include Tegra114 support into existing Tegra124 EMC schema with the most
> notable difference being the amount of EMC timings and a few SoC unique
> entries.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  .../nvidia,tegra124-emc.yaml                  | 174 +++---------------
>  1 file changed, 26 insertions(+), 148 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v4 01/12] devfreq: tegra30-devfreq: add support for Tegra114

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Lets add Tegra114 support to activity monitor device as a preparation to
> upcoming EMC controller support.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/devfreq/tegra30-devfreq.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c
> index 8ea5b482bfb3..fa83480a923f 100644
> --- a/drivers/devfreq/tegra30-devfreq.c
> +++ b/drivers/devfreq/tegra30-devfreq.c
> @@ -963,16 +963,22 @@ static int tegra_devfreq_probe(struct platform_device *pdev)
>  	return 0;
>  }
>  
> +/*
> + * The activity counter is incremented every 256 memory transactions. However,
> + * the number of clock cycles required for each transaction varies across
> + * different SoC generations. For instance, a single transaction takes 2 EMC
> + * clocks on Tegra30, 1 EMC clock on Tegra114, and 4 EMC clocks on Tegra124.
> + */
>  static const struct tegra_devfreq_soc_data tegra124_soc = {
>  	.configs = tegra124_device_configs,
> -
> -	/*
> -	 * Activity counter is incremented every 256 memory transactions,
> -	 * and each transaction takes 4 EMC clocks.
> -	 */
>  	.count_weight = 4 * 256,
>  };
>  
> +static const struct tegra_devfreq_soc_data tegra114_soc = {
> +	.configs = tegra124_device_configs,
> +	.count_weight = 256,
> +};
> +
>  static const struct tegra_devfreq_soc_data tegra30_soc = {
>  	.configs = tegra30_device_configs,
>  	.count_weight = 2 * 256,
> @@ -980,6 +986,7 @@ static const struct tegra_devfreq_soc_data tegra30_soc = {
>  
>  static const struct of_device_id tegra_devfreq_of_match[] = {
>  	{ .compatible = "nvidia,tegra30-actmon",  .data = &tegra30_soc, },
> +	{ .compatible = "nvidia,tegra114-actmon", .data = &tegra114_soc, },
>  	{ .compatible = "nvidia,tegra124-actmon", .data = &tegra124_soc, },
>  	{ },
>  };
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v4 06/12] clk: tegra: set up proper EMC clock implementation for Tegra114

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Remove current emc and emc_mux clocks and replace them with the proper EMC
> clock implementation for correct EMC driver support.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra114.c | 39 ++++++++++++++++++++------------
>  1 file changed, 25 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index 8bde72aa5e68..853ef707654a 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -622,10 +622,6 @@ static const char *mux_plld_out0_plld2_out0[] = {
>  };
>  #define mux_plld_out0_plld2_out0_idx NULL
>  
> -static const char *mux_pllmcp_clkm[] = {
> -	"pll_m_out0", "pll_c_out0", "pll_p_out0", "clk_m", "pll_m_ud",
> -};
> -
>  static const struct clk_div_table pll_re_div_table[] = {
>  	{ .val = 0, .div = 1 },
>  	{ .val = 1, .div = 2 },
> @@ -672,7 +668,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
>  	[tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
>  	[tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
>  	[tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
> -	[tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
>  	[tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
>  	[tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
>  	[tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
> @@ -1048,14 +1043,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
>  					     0, 82, periph_clk_enb_refcnt);
>  	clks[TEGRA114_CLK_DSIB] = clk;
>  
> -	/* emc mux */
> -	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
> -			       ARRAY_SIZE(mux_pllmcp_clkm),
> -			       CLK_SET_RATE_NO_REPARENT,
> -			       clk_base + CLK_SOURCE_EMC,
> -			       29, 3, 0, &emc_lock);
> -
> -	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
> +	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
>  				    &emc_lock);
>  	clks[TEGRA114_CLK_MC] = clk;
>  
> @@ -1321,6 +1309,26 @@ static int tegra114_reset_deassert(unsigned long id)
>  	return 0;
>  }
>  
> +static struct clk *tegra114_clk_src_onecell_get(struct of_phandle_args *clkspec,
> +						void *data)
> +{
> +	struct clk_hw *hw;
> +	struct clk *clk;
> +
> +	clk = of_clk_src_onecell_get(clkspec, data);
> +	if (IS_ERR(clk))
> +		return clk;
> +
> +	hw = __clk_get_hw(clk);
> +
> +	if (clkspec->args[0] == TEGRA114_CLK_EMC) {
> +		if (!tegra124_clk_emc_driver_available(hw))
> +			return ERR_PTR(-EPROBE_DEFER);
> +	}
> +
> +	return clk;
> +}
> +
>  static void __init tegra114_clock_init(struct device_node *np)
>  {
>  	struct device_node *node;
> @@ -1368,7 +1376,10 @@ static void __init tegra114_clock_init(struct device_node *np)
>  	tegra_init_special_resets(1, tegra114_reset_assert,
>  				  tegra114_reset_deassert);
>  
> -	tegra_add_of_provider(np, of_clk_src_onecell_get);
> +	tegra_add_of_provider(np, tegra114_clk_src_onecell_get);
> +	clks[TEGRA114_CLK_EMC] = tegra124_clk_register_emc(clk_base, np,
> +							   &emc_lock);
> +
>  	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
>  
>  	tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v4 08/12] soc: tegra: common: add Tegra114 support to devm_tegra_core_dev_init_opp_table

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Determine the Tegra114 hardware version using the SoC Speedo ID bit macro,
> mirroring the approach already used for Tegra30 and Tegra124.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/soc/tegra/common.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/tegra/common.c b/drivers/soc/tegra/common.c
> index 6292a1c72071..2264dd38893a 100644
> --- a/drivers/soc/tegra/common.c
> +++ b/drivers/soc/tegra/common.c
> @@ -143,7 +143,8 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
>  		hw_version = BIT(tegra_sku_info.soc_process_id);
>  		config.supported_hw = &hw_version;
>  		config.supported_hw_count = 1;
> -	} else if (of_machine_is_compatible("nvidia,tegra30")) {
> +	} else if (of_machine_is_compatible("nvidia,tegra30") ||
> +		   of_machine_is_compatible("nvidia,tegra114")) {
>  		hw_version = BIT(tegra_sku_info.soc_speedo_id);
>  		config.supported_hw = &hw_version;
>  		config.supported_hw_count = 1;
> @@ -156,7 +157,7 @@ int devm_tegra_core_dev_init_opp_table(struct device *dev,
>  	}
>  
>  	/*
> -	 * Tegra114+ doesn't support OPP yet, return early for non tegra20/30
> +	 * Tegra124+ doesn't support OPP yet, return early for pre-Tegra124
>  	 * case.
>  	 */
>  	if (!config.supported_hw)
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v4 09/12] memory: tegra: Add Tegra114 EMC driver

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Introduce driver for the External Memory Controller (EMC) found in
> Tegra114 SoC. It controls the external DRAM on the board. The purpose of
> this driver is to program memory timing for external memory on the EMC
> clock rate change.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/memory/tegra/Kconfig        |   12 +
>  drivers/memory/tegra/Makefile       |    1 +
>  drivers/memory/tegra/tegra114-emc.c | 1463 +++++++++++++++++++++++++++
>  3 files changed, 1476 insertions(+)
>  create mode 100644 drivers/memory/tegra/tegra114-emc.c
> 
> diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
> index fc5a27791826..11e7cc357d39 100644
> --- a/drivers/memory/tegra/Kconfig
> +++ b/drivers/memory/tegra/Kconfig
> @@ -35,6 +35,18 @@ config TEGRA30_EMC
>  	  This driver is required to change memory timings / clock rate for
>  	  external memory.
>  
> +config TEGRA114_EMC
> +	tristate "NVIDIA Tegra114 External Memory Controller driver"
> +	default y
> +	depends on ARCH_TEGRA_114_SOC || COMPILE_TEST
> +	select TEGRA124_CLK_EMC if ARCH_TEGRA
> +	select PM_OPP
> +	help
> +	  This driver is for the External Memory Controller (EMC) found on
> +	  Tegra114 chips. The EMC controls the external DRAM on the board.
> +	  This driver is required to change memory timings / clock rate for
> +	  external memory.
> +
>  config TEGRA124_EMC
>  	tristate "NVIDIA Tegra124 External Memory Controller driver"
>  	default ARCH_TEGRA_124_SOC
> diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
> index 6334601e6120..6b9156de4b66 100644
> --- a/drivers/memory/tegra/Makefile
> +++ b/drivers/memory/tegra/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
>  
>  obj-$(CONFIG_TEGRA20_EMC)  += tegra20-emc.o
>  obj-$(CONFIG_TEGRA30_EMC)  += tegra30-emc.o
> +obj-$(CONFIG_TEGRA114_EMC) += tegra114-emc.o
>  obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
>  obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
>  obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
> diff --git a/drivers/memory/tegra/tegra114-emc.c b/drivers/memory/tegra/tegra114-emc.c
> new file mode 100644
> index 000000000000..789b8e959a68
> --- /dev/null
> +++ b/drivers/memory/tegra/tegra114-emc.c
> @@ -0,0 +1,1463 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Tegra114 External Memory Controller driver
> + *
> + * Based on downstream driver from NVIDIA and tegra124-emc.c
> + * Copyright (C) 2011-2014 NVIDIA Corporation
> + *
> + * Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk/tegra.h>
> +#include <linux/debugfs.h>
> +#include <linux/delay.h>
> +#include <linux/interconnect-provider.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/sort.h>
> +#include <linux/string.h>
> +
> +#include <soc/tegra/common.h>
> +#include <soc/tegra/fuse.h>
> +#include <soc/tegra/mc.h>
> +
> +#include "mc.h"
> +
> +#define EMC_INTSTATUS				0x0
> +#define EMC_INTSTATUS_REFRESH_OVERFLOW		BIT(3)
> +#define EMC_INTSTATUS_CLKCHANGE_COMPLETE	BIT(4)
> +
> +#define EMC_INTMASK				0x4
> +
> +#define EMC_DBG					0x8
> +#define EMC_DBG_READ_MUX_ASSEMBLY		BIT(0)
> +#define EMC_DBG_WRITE_MUX_ACTIVE		BIT(1)
> +#define EMC_DBG_FORCE_UPDATE			BIT(2)
> +#define EMC_DBG_CFG_PRIORITY			BIT(24)
> +
> +#define EMC_CFG					0xc
> +#define EMC_CFG_DSR_VTTGEN_DRV_EN		BIT(18)
> +#define EMC_CFG_PWR_MASK			((0xF << 28) | BIT(18))
> +#define EMC_CFG_DYN_SREF			BIT(28)
> +#define EMC_CFG_DRAM_ACPD			BIT(29)
> +#define EMC_CFG_DRAM_CLKSTOP_SR			BIT(30)
> +#define EMC_CFG_DRAM_CLKSTOP_PD			BIT(31)
> +
> +#define EMC_ADR_CFG				0x10
> +#define EMC_ADR_CFG_EMEM_NUMDEV			BIT(0)
> +
> +#define EMC_REFCTRL				0x20
> +#define EMC_REFCTRL_DEV_SEL_SHIFT		0
> +#define EMC_REFCTRL_ENABLE			BIT(31)
> +
> +#define EMC_TIMING_CONTROL			0x28
> +#define EMC_RC					0x2c
> +#define EMC_RFC					0x30
> +#define EMC_RAS					0x34
> +#define EMC_RP					0x38
> +#define EMC_R2W					0x3c
> +#define EMC_W2R					0x40
> +#define EMC_R2P					0x44
> +#define EMC_W2P					0x48
> +#define EMC_RD_RCD				0x4c
> +#define EMC_WR_RCD				0x50
> +#define EMC_RRD					0x54
> +#define EMC_REXT				0x58
> +#define EMC_WDV					0x5c
> +#define EMC_QUSE				0x60
> +#define EMC_QRST				0x64
> +#define EMC_QSAFE				0x68
> +#define EMC_RDV					0x6c
> +#define EMC_REFRESH				0x70
> +#define EMC_BURST_REFRESH_NUM			0x74
> +#define EMC_PDEX2WR				0x78
> +#define EMC_PDEX2RD				0x7c
> +#define EMC_PCHG2PDEN				0x80
> +#define EMC_ACT2PDEN				0x84
> +#define EMC_AR2PDEN				0x88
> +#define EMC_RW2PDEN				0x8c
> +#define EMC_TXSR				0x90
> +#define EMC_TCKE				0x94
> +#define EMC_TFAW				0x98
> +#define EMC_TRPAB				0x9c
> +#define EMC_TCLKSTABLE				0xa0
> +#define EMC_TCLKSTOP				0xa4
> +#define EMC_TREFBW				0xa8
> +#define EMC_QUSE_EXTRA				0xac
> +#define EMC_ODT_WRITE				0xb0
> +#define EMC_ODT_READ				0xb4
> +#define EMC_WEXT				0xb8
> +#define EMC_CTT					0xbc
> +#define EMC_RFC_SLR				0xc0
> +#define EMC_MRS_WAIT_CNT2			0xc4
> +
> +#define EMC_MRS_WAIT_CNT			0xc8
> +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT	0
> +#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK	\
> +	(0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
> +#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT	16
> +#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK		\
> +	(0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
> +
> +#define EMC_MRS					0xcc
> +#define EMC_MODE_SET_DLL_RESET			BIT(8)
> +#define EMC_MODE_SET_LONG_CNT			BIT(26)
> +#define EMC_EMRS				0xd0
> +#define EMC_REF					0xd4
> +#define EMC_PRE					0xd8
> +
> +#define EMC_SELF_REF				0xe0
> +#define EMC_SELF_REF_CMD_ENABLED		BIT(0)
> +#define EMC_SELF_REF_DEV_SEL_SHIFT		30
> +
> +#define EMC_MRW					0xe8
> +
> +#define EMC_MRR					0xec
> +#define EMC_MRR_MA_SHIFT			16
> +#define LPDDR2_MR4_TEMP_SHIFT			0
> +
> +#define EMC_XM2DQSPADCTRL3			0xf8
> +#define EMC_FBIO_SPARE				0x100
> +
> +#define EMC_FBIO_CFG5				0x104
> +#define EMC_FBIO_CFG5_DRAM_TYPE_MASK		0x3
> +#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT		0
> +
> +#define EMC_FBIO_CFG6				0x114
> +#define EMC_EMRS2				0x12c
> +#define EMC_MRW2				0x134
> +#define EMC_MRW4				0x13c
> +#define EMC_EINPUT				0x14c
> +#define EMC_EINPUT_DURATION			0x150
> +#define EMC_PUTERM_EXTRA			0x154
> +#define EMC_TCKESR				0x158
> +#define EMC_TPD					0x15c
> +
> +#define EMC_AUTO_CAL_CONFIG			0x2a4
> +#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START	BIT(31)
> +#define EMC_AUTO_CAL_INTERVAL			0x2a8
> +#define EMC_AUTO_CAL_STATUS			0x2ac
> +#define EMC_AUTO_CAL_STATUS_ACTIVE		BIT(31)
> +#define EMC_STATUS				0x2b4
> +#define EMC_STATUS_TIMING_UPDATE_STALLED	BIT(23)
> +
> +#define EMC_CFG_2				0x2b8
> +#define EMC_CFG_2_CLKCHANGE_REQ_ENABLE		BIT(0)
> +#define EMC_CFG_2_CLKCHANGE_PD_ENABLE		BIT(1)
> +#define EMC_CFG_2_CLKCHANGE_SR_ENABLE		BIT(2)
> +
> +#define EMC_CFG_DIG_DLL				0x2bc
> +#define EMC_CFG_DIG_DLL_PERIOD			0x2c0
> +#define EMC_RDV_MASK				0x2cc
> +#define EMC_WDV_MASK				0x2d0
> +#define EMC_CTT_DURATION			0x2d8
> +#define EMC_CTT_TERM_CTRL			0x2dc
> +#define EMC_ZCAL_INTERVAL			0x2e0
> +#define EMC_ZCAL_WAIT_CNT			0x2e4
> +
> +#define EMC_ZQ_CAL				0x2ec
> +#define EMC_ZQ_CAL_CMD				BIT(0)
> +#define EMC_ZQ_CAL_LONG				BIT(4)
> +#define EMC_ZQ_CAL_LONG_CMD_DEV0		\
> +	(DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
> +#define EMC_ZQ_CAL_LONG_CMD_DEV1		\
> +	(DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
> +
> +#define EMC_XM2CMDPADCTRL			0x2f0
> +#define EMC_XM2DQSPADCTRL			0x2f8
> +#define EMC_XM2DQSPADCTRL2			0x2fc
> +#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE	BIT(0)
> +#define EMC_XM2DQSPADCTRL2_VREF_ENABLE		BIT(5)
> +#define EMC_XM2DQPADCTRL			0x300
> +#define EMC_XM2DQPADCTRL2			0x304
> +#define EMC_XM2CLKPADCTRL			0x308
> +#define EMC_XM2COMPPADCTRL			0x30c
> +#define EMC_XM2VTTGENPADCTRL			0x310
> +#define EMC_XM2VTTGENPADCTRL2			0x314
> +#define EMC_XM2QUSEPADCTRL			0x318
> +#define EMC_XM2DQSPADCTRL4			0x320
> +#define EMC_DLL_XFORM_DQS0			0x328
> +#define EMC_DLL_XFORM_DQS1			0x32c
> +#define EMC_DLL_XFORM_DQS2			0x330
> +#define EMC_DLL_XFORM_DQS3			0x334
> +#define EMC_DLL_XFORM_DQS4			0x338
> +#define EMC_DLL_XFORM_DQS5			0x33c
> +#define EMC_DLL_XFORM_DQS6			0x340
> +#define EMC_DLL_XFORM_DQS7			0x344
> +#define EMC_DLL_XFORM_QUSE0			0x348
> +#define EMC_DLL_XFORM_QUSE1			0x34c
> +#define EMC_DLL_XFORM_QUSE2			0x350
> +#define EMC_DLL_XFORM_QUSE3			0x354
> +#define EMC_DLL_XFORM_QUSE4			0x358
> +#define EMC_DLL_XFORM_QUSE5			0x35c
> +#define EMC_DLL_XFORM_QUSE6			0x360
> +#define EMC_DLL_XFORM_QUSE7			0x364
> +#define EMC_DLL_XFORM_DQ0			0x368
> +#define EMC_DLL_XFORM_DQ1			0x36c
> +#define EMC_DLL_XFORM_DQ2			0x370
> +#define EMC_DLL_XFORM_DQ3			0x374
> +#define EMC_DLI_TRIM_TXDQS0			0x3a8
> +#define EMC_DLI_TRIM_TXDQS1			0x3ac
> +#define EMC_DLI_TRIM_TXDQS2			0x3b0
> +#define EMC_DLI_TRIM_TXDQS3			0x3b4
> +#define EMC_DLI_TRIM_TXDQS4			0x3b8
> +#define EMC_DLI_TRIM_TXDQS5			0x3bc
> +#define EMC_DLI_TRIM_TXDQS6			0x3c0
> +#define EMC_DLI_TRIM_TXDQS7			0x3c4
> +#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE	0x3cc
> +#define EMC_SEL_DPD_CTRL			0x3d8
> +#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD		BIT(8)
> +#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD		BIT(5)
> +#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD		BIT(4)
> +#define EMC_SEL_DPD_CTRL_CA_SEL_DPD		BIT(3)
> +#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD		BIT(2)
> +#define EMC_SEL_DPD_CTRL_DDR3_MASK	\
> +	((0xf << 2) | BIT(8))
> +#define EMC_SEL_DPD_CTRL_MASK \
> +	((0x3 << 2) | BIT(5) | BIT(8))
> +#define EMC_PRE_REFRESH_REQ_CNT			0x3dc
> +#define EMC_DYN_SELF_REF_CONTROL		0x3e0
> +#define EMC_TXSRDLL				0x3e4
> +#define EMC_CCFIFO_ADDR				0x3e8
> +#define EMC_CCFIFO_DATA				0x3ec
> +#define EMC_CCFIFO_STATUS			0x3f0
> +#define EMC_CDB_CNTL_1				0x3f4
> +#define EMC_CDB_CNTL_2				0x3f8
> +#define EMC_XM2CLKPADCTRL2			0x3fc
> +#define EMC_AUTO_CAL_CONFIG2			0x458
> +#define EMC_AUTO_CAL_CONFIG3			0x45c
> +#define EMC_IBDLY				0x468
> +#define EMC_DLL_XFORM_ADDR0			0x46c
> +#define EMC_DLL_XFORM_ADDR1			0x470
> +#define EMC_DLL_XFORM_ADDR2			0x474
> +#define EMC_DSR_VTTGEN_DRV			0x47c
> +#define EMC_TXDSRVTTGEN				0x480
> +#define EMC_XM2CMDPADCTRL4			0x484
> +
> +#define DRAM_DEV_SEL_ALL			0
> +#define DRAM_DEV_SEL_0				BIT(31)
> +#define DRAM_DEV_SEL_1				BIT(30)
> +
> +#define EMC_CFG_POWER_FEATURES_MASK		\
> +	(EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
> +	EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
> +#define EMC_REFCTRL_DEV_SEL(n) ((((n) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
> +#define EMC_DRAM_DEV_SEL(n) (((n) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
> +
> +/* Maximum amount of time in us. to wait for changes to become effective */
> +#define EMC_STATUS_UPDATE_TIMEOUT		1000
> +
> +enum emc_dram_type {
> +	DRAM_TYPE_DDR3,
> +	DRAM_TYPE_DDR1,
> +	DRAM_TYPE_LPDDR2,
> +	DRAM_TYPE_DDR2
> +};
> +
> +enum emc_dll_change {
> +	DLL_CHANGE_NONE,
> +	DLL_CHANGE_ON,
> +	DLL_CHANGE_OFF
> +};
> +
> +static const unsigned long emc_burst_regs[] = {
> +	EMC_RC,
> +	EMC_RFC,
> +	EMC_RAS,
> +	EMC_RP,
> +	EMC_R2W,
> +	EMC_W2R,
> +	EMC_R2P,
> +	EMC_W2P,
> +	EMC_RD_RCD,
> +	EMC_WR_RCD,
> +	EMC_RRD,
> +	EMC_REXT,
> +	EMC_WEXT,
> +	EMC_WDV,
> +	EMC_WDV_MASK,
> +	EMC_QUSE,
> +	EMC_IBDLY,
> +	EMC_EINPUT,
> +	EMC_EINPUT_DURATION,
> +	EMC_PUTERM_EXTRA,
> +	EMC_CDB_CNTL_1,
> +	EMC_CDB_CNTL_2,
> +	EMC_QRST,
> +	EMC_QSAFE,
> +	EMC_RDV,
> +	EMC_RDV_MASK,
> +	EMC_REFRESH,
> +	EMC_BURST_REFRESH_NUM,
> +	EMC_PRE_REFRESH_REQ_CNT,
> +	EMC_PDEX2WR,
> +	EMC_PDEX2RD,
> +	EMC_PCHG2PDEN,
> +	EMC_ACT2PDEN,
> +	EMC_AR2PDEN,
> +	EMC_RW2PDEN,
> +	EMC_TXSR,
> +	EMC_TXSRDLL,
> +	EMC_TCKE,
> +	EMC_TCKESR,
> +	EMC_TPD,
> +	EMC_TFAW,
> +	EMC_TRPAB,
> +	EMC_TCLKSTABLE,
> +	EMC_TCLKSTOP,
> +	EMC_TREFBW,
> +	EMC_QUSE_EXTRA,
> +	EMC_FBIO_CFG6,
> +	EMC_ODT_WRITE,
> +	EMC_ODT_READ,
> +	EMC_FBIO_CFG5,
> +	EMC_CFG_DIG_DLL,
> +	EMC_CFG_DIG_DLL_PERIOD,
> +	EMC_DLL_XFORM_DQS0,
> +	EMC_DLL_XFORM_DQS1,
> +	EMC_DLL_XFORM_DQS2,
> +	EMC_DLL_XFORM_DQS3,
> +	EMC_DLL_XFORM_DQS4,
> +	EMC_DLL_XFORM_DQS5,
> +	EMC_DLL_XFORM_DQS6,
> +	EMC_DLL_XFORM_DQS7,
> +	EMC_DLL_XFORM_QUSE0,
> +	EMC_DLL_XFORM_QUSE1,
> +	EMC_DLL_XFORM_QUSE2,
> +	EMC_DLL_XFORM_QUSE3,
> +	EMC_DLL_XFORM_QUSE4,
> +	EMC_DLL_XFORM_QUSE5,
> +	EMC_DLL_XFORM_QUSE6,
> +	EMC_DLL_XFORM_QUSE7,
> +	EMC_DLI_TRIM_TXDQS0,
> +	EMC_DLI_TRIM_TXDQS1,
> +	EMC_DLI_TRIM_TXDQS2,
> +	EMC_DLI_TRIM_TXDQS3,
> +	EMC_DLI_TRIM_TXDQS4,
> +	EMC_DLI_TRIM_TXDQS5,
> +	EMC_DLI_TRIM_TXDQS6,
> +	EMC_DLI_TRIM_TXDQS7,
> +	EMC_DLL_XFORM_DQ0,
> +	EMC_DLL_XFORM_DQ1,
> +	EMC_DLL_XFORM_DQ2,
> +	EMC_DLL_XFORM_DQ3,
> +	EMC_XM2CMDPADCTRL,
> +	EMC_XM2CMDPADCTRL4,
> +	EMC_XM2DQPADCTRL2,
> +	EMC_XM2CLKPADCTRL,
> +	EMC_XM2COMPPADCTRL,
> +	EMC_XM2VTTGENPADCTRL,
> +	EMC_XM2VTTGENPADCTRL2,
> +	EMC_XM2DQSPADCTRL3,
> +	EMC_XM2DQSPADCTRL4,
> +	EMC_DSR_VTTGEN_DRV,
> +	EMC_TXDSRVTTGEN,
> +	EMC_FBIO_SPARE,
> +	EMC_ZCAL_WAIT_CNT,
> +	EMC_MRS_WAIT_CNT2,
> +	EMC_CTT,
> +	EMC_CTT_DURATION,
> +	EMC_DYN_SELF_REF_CONTROL,
> +};
> +
> +struct emc_timing {
> +	unsigned long rate;
> +
> +	u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
> +
> +	u32 emc_auto_cal_config;
> +	u32 emc_auto_cal_config2;
> +	u32 emc_auto_cal_config3;
> +	u32 emc_auto_cal_interval;
> +	u32 emc_cfg;
> +	u32 emc_ctt_term_ctrl;
> +	u32 emc_mode_1;
> +	u32 emc_mode_2;
> +	u32 emc_mode_4;
> +	u32 emc_mode_reset;
> +	u32 emc_mrs_wait_cnt;
> +	u32 emc_sel_dpd_ctrl;
> +	u32 emc_xm2dqspadctrl2;
> +	u32 emc_zcal_cnt_long;
> +	u32 emc_zcal_interval;
> +};
> +
> +enum emc_rate_request_type {
> +	EMC_RATE_DEBUG,
> +	EMC_RATE_ICC,
> +	EMC_RATE_TYPE_MAX,
> +};
> +
> +struct emc_rate_request {
> +	unsigned long min_rate;
> +	unsigned long max_rate;
> +};
> +
> +struct tegra_emc {
> +	struct device *dev;
> +	struct tegra_mc *mc;
> +	void __iomem *regs;
> +	unsigned int irq;
> +	struct clk *clk;
> +
> +	enum emc_dram_type dram_type;
> +	unsigned int dram_num;
> +
> +	struct emc_timing last_timing;
> +	struct emc_timing *timings;
> +	unsigned int num_timings;
> +
> +	struct {
> +		struct dentry *root;
> +		unsigned long min_rate;
> +		unsigned long max_rate;
> +	} debugfs;
> +
> +	struct icc_provider provider;
> +
> +	/*
> +	 * There are multiple sources in the EMC driver which could request
> +	 * a min/max clock rate, these rates are contained in this array.
> +	 */
> +	struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
> +
> +	/* protect shared rate-change code path */
> +	struct mutex rate_lock;
> +};
> +
> +static irqreturn_t tegra_emc_isr(int irq, void *data)
> +{
> +	struct tegra_emc *emc = data;
> +	u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW;
> +	u32 status;
> +
> +	status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
> +	if (!status)
> +		return IRQ_NONE;
> +
> +	/* notify about HW problem */
> +	if (status & EMC_INTSTATUS_REFRESH_OVERFLOW)
> +		dev_err_ratelimited(emc->dev,
> +				    "refresh request overflow timeout\n");
> +
> +	/* clear interrupts */
> +	writel_relaxed(status, emc->regs + EMC_INTSTATUS);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/* Timing change sequence functions */
> +
> +static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
> +			      unsigned long offset)
> +{
> +	writel(value, emc->regs + EMC_CCFIFO_DATA);
> +	writel(offset, emc->regs + EMC_CCFIFO_ADDR);
> +}
> +
> +static void emc_seq_update_timing(struct tegra_emc *emc)
> +{
> +	int ret;
> +	u32 value;
> +
> +	writel(1, emc->regs + EMC_TIMING_CONTROL);
> +
> +	ret = readl_poll_timeout_atomic(emc->regs + EMC_STATUS, value,
> +					!(value & EMC_STATUS_TIMING_UPDATE_STALLED),
> +					1, EMC_STATUS_UPDATE_TIMEOUT);
> +	if (ret)
> +		dev_err(emc->dev, "timing update timed out\n");
> +}
> +
> +static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
> +{
> +	int ret;
> +	u32 value;
> +
> +	writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
> +
> +	ret = readl_poll_timeout_atomic(emc->regs + EMC_AUTO_CAL_STATUS, value,
> +					!(value & EMC_AUTO_CAL_STATUS_ACTIVE),
> +					1, EMC_STATUS_UPDATE_TIMEOUT);
> +	if (ret)
> +		dev_err(emc->dev, "auto cal disable timed out\n");
> +}
> +
> +static void emc_seq_wait_clkchange(struct tegra_emc *emc)
> +{
> +	int ret;
> +	u32 value;
> +
> +	ret = readl_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, value,
> +					value & EMC_INTSTATUS_CLKCHANGE_COMPLETE,
> +					1, EMC_STATUS_UPDATE_TIMEOUT);
> +	if (ret)
> +		dev_err(emc->dev, "clock change timed out\n");
> +}
> +
> +static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
> +						unsigned long rate)
> +{
> +	struct emc_timing *timing = NULL;
> +	unsigned int i;
> +
> +	for (i = 0; i < emc->num_timings; i++) {
> +		if (emc->timings[i].rate == rate) {
> +			timing = &emc->timings[i];
> +			break;
> +		}
> +	}
> +
> +	if (!timing) {
> +		dev_err(emc->dev, "no timing for rate %lu\n", rate);
> +		return NULL;
> +	}
> +
> +	return timing;
> +}
> +
> +static int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
> +					   unsigned long rate)
> +{
> +	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
> +	struct emc_timing *last = &emc->last_timing;
> +	enum emc_dll_change dll_change;
> +	unsigned int pre_wait = 0;
> +	u32 val, mask;
> +	bool next_dll_enabled = !(timing->emc_mode_1 & 0x1);
> +	bool last_dll_enabled = !(last->emc_mode_1 & 0x1);
> +	bool update = false;
> +	unsigned int i;
> +
> +	if (!timing)
> +		return -ENOENT;
> +
> +	if (next_dll_enabled == last_dll_enabled)
> +		dll_change = DLL_CHANGE_NONE;
> +	else if (next_dll_enabled)
> +		dll_change = DLL_CHANGE_ON;
> +	else
> +		dll_change = DLL_CHANGE_OFF;
> +
> +	/* Clear CLKCHANGE_COMPLETE interrupts */
> +	writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
> +
> +	/* Disable dynamic self-refresh */
> +	val = readl(emc->regs + EMC_CFG);
> +	if (val & EMC_CFG_PWR_MASK) {
> +		val &= ~EMC_CFG_POWER_FEATURES_MASK;
> +		writel(val, emc->regs + EMC_CFG);
> +
> +		pre_wait = 5;
> +	}
> +
> +	/* Disable SEL_DPD_CTRL for clock change */
> +	if (emc->dram_type == DRAM_TYPE_DDR3)
> +		mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
> +	else
> +		mask = EMC_SEL_DPD_CTRL_MASK;
> +
> +	val = readl(emc->regs + EMC_SEL_DPD_CTRL);
> +	if (val & mask) {
> +		val &= ~mask;
> +		writel(val, emc->regs + EMC_SEL_DPD_CTRL);
> +	}
> +
> +	/* Prepare DQ/DQS for clock change */
> +	val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
> +	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
> +	    !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
> +		val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
> +		update = true;
> +	}
> +
> +	if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
> +	    !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
> +		val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
> +		update = true;
> +	}
> +
> +	if (update) {
> +		writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
> +		if (pre_wait < 30)
> +			pre_wait = 30;
> +	}
> +
> +	/* Wait to settle */
> +	if (pre_wait) {
> +		emc_seq_update_timing(emc);
> +		udelay(pre_wait);
> +	}
> +
> +	/* Program CTT_TERM control */
> +	if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
> +		emc_seq_disable_auto_cal(emc);
> +		writel(timing->emc_ctt_term_ctrl,
> +		       emc->regs + EMC_CTT_TERM_CTRL);
> +		emc_seq_update_timing(emc);
> +	}
> +
> +	/* Program burst shadow registers */
> +	for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
> +		writel(timing->emc_burst_data[i],
> +		       emc->regs + emc_burst_regs[i]);
> +
> +	writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
> +	writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
> +
> +	tegra_mc_write_emem_configuration(emc->mc, timing->rate);
> +
> +	val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
> +	emc_ccfifo_writel(emc, val, EMC_CFG);
> +
> +	/* Program AUTO_CAL_CONFIG */
> +	if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
> +		emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
> +				  EMC_AUTO_CAL_CONFIG2);
> +
> +	if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
> +		emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
> +				  EMC_AUTO_CAL_CONFIG3);
> +
> +	if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
> +		val = timing->emc_auto_cal_config;
> +		val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
> +		emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
> +	}
> +
> +	/* DDR3: predict MRS long wait count */
> +	if (emc->dram_type == DRAM_TYPE_DDR3 &&
> +	    dll_change == DLL_CHANGE_ON) {
> +		u32 cnt = 512;
> +
> +		if (timing->emc_zcal_interval != 0 &&
> +		    last->emc_zcal_interval == 0)
> +			cnt -= emc->dram_num * 256;
> +
> +		val = (timing->emc_mrs_wait_cnt
> +			& EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
> +			>> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
> +		if (cnt < val)
> +			cnt = val;
> +
> +		val = timing->emc_mrs_wait_cnt
> +			& ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
> +		val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
> +			& EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
> +
> +		writel(val, emc->regs + EMC_MRS_WAIT_CNT);
> +	}
> +
> +	/* DDR3: Turn off DLL and enter self-refresh */
> +	if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
> +		emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
> +
> +	/* Disable refresh controller */
> +	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
> +			  EMC_REFCTRL);
> +	if (emc->dram_type == DRAM_TYPE_DDR3)
> +		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
> +				       EMC_SELF_REF_CMD_ENABLED,
> +				  EMC_SELF_REF);
> +
> +	/* Flow control marker */
> +	emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
> +
> +	/* DDR3: Exit self-refresh */
> +	if (emc->dram_type == DRAM_TYPE_DDR3)
> +		emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
> +				  EMC_SELF_REF);
> +	emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
> +			       EMC_REFCTRL_ENABLE,
> +			  EMC_REFCTRL);
> +
> +	/* Set DRAM mode registers */
> +	if (emc->dram_type == DRAM_TYPE_DDR3) {
> +		if (timing->emc_mode_1 != last->emc_mode_1)
> +			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
> +		if (timing->emc_mode_2 != last->emc_mode_2)
> +			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
> +
> +		if (timing->emc_mode_reset != last->emc_mode_reset ||
> +		    dll_change == DLL_CHANGE_ON) {
> +			val = timing->emc_mode_reset;
> +			if (dll_change == DLL_CHANGE_ON) {
> +				val |= EMC_MODE_SET_DLL_RESET;
> +				val |= EMC_MODE_SET_LONG_CNT;
> +			} else {
> +				val &= ~EMC_MODE_SET_DLL_RESET;
> +			}
> +			emc_ccfifo_writel(emc, val, EMC_MRS);
> +		}
> +	} else {
> +		if (timing->emc_mode_2 != last->emc_mode_2)
> +			emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
> +		if (timing->emc_mode_1 != last->emc_mode_1)
> +			emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
> +		if (timing->emc_mode_4 != last->emc_mode_4)
> +			emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
> +	}
> +
> +	/*  Issue ZCAL command if turning ZCAL on */
> +	if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
> +		emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
> +		if (emc->dram_num > 1)
> +			emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
> +					  EMC_ZQ_CAL);
> +	}
> +
> +	/*  Write to RO register to remove stall after change */
> +	emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
> +
> +	/* Disable AUTO_CAL for clock change */
> +	emc_seq_disable_auto_cal(emc);
> +
> +	/* Read register to wait until programming has settled */
> +	mc_readl(emc->mc, MC_EMEM_ADR_CFG);
> +
> +	return 0;
> +}
> +
> +static void tegra_emc_complete_timing_change(struct tegra_emc *emc,
> +					     unsigned long rate)
> +{
> +	struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
> +	struct emc_timing *last = &emc->last_timing;
> +
> +	if (!timing)
> +		return;
> +
> +	/* Wait until the state machine has settled */
> +	emc_seq_wait_clkchange(emc);
> +
> +	/* Restore AUTO_CAL */
> +	if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
> +		writel(timing->emc_auto_cal_interval,
> +		       emc->regs + EMC_AUTO_CAL_INTERVAL);
> +
> +	/* Restore dynamic self-refresh */
> +	if (timing->emc_cfg & EMC_CFG_PWR_MASK)
> +		writel(timing->emc_cfg, emc->regs + EMC_CFG);
> +
> +	/* Set ZCAL wait count */
> +	writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
> +
> +	/* Wait for timing to settle */
> +	udelay(2);
> +
> +	/* Reprogram SEL_DPD_CTRL */
> +	writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
> +	emc_seq_update_timing(emc);
> +
> +	emc->last_timing = *timing;
> +}
> +
> +/* Initialization and deinitialization */
> +
> +static void emc_read_current_timing(struct tegra_emc *emc,
> +				    struct emc_timing *timing)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
> +		timing->emc_burst_data[i] =
> +			readl(emc->regs + emc_burst_regs[i]);
> +
> +	timing->emc_cfg = readl(emc->regs + EMC_CFG);
> +
> +	timing->emc_auto_cal_interval = 0;
> +	timing->emc_zcal_cnt_long = 0;
> +	timing->emc_mode_1 = 0;
> +	timing->emc_mode_2 = 0;
> +	timing->emc_mode_4 = 0;
> +	timing->emc_mode_reset = 0;
> +}
> +
> +static int emc_init(struct tegra_emc *emc)
> +{
> +	u32 emc_cfg, emc_dbg;
> +	u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW;
> +	const char *dram_type_str;
> +
> +	emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
> +
> +	emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
> +	emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
> +
> +	emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
> +
> +	emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
> +
> +	/* enable EMC and CAR to handshake on PLL divider/source changes */
> +	emc_cfg |= EMC_CFG_2_CLKCHANGE_REQ_ENABLE;
> +
> +	/* configure clock change mode accordingly to DRAM type */
> +	if (emc->dram_type == DRAM_TYPE_LPDDR2)
> +		emc_cfg |= EMC_CFG_2_CLKCHANGE_PD_ENABLE;
> +	else
> +		emc_cfg &= ~EMC_CFG_2_CLKCHANGE_PD_ENABLE;
> +
> +	writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
> +
> +	/* initialize interrupt */
> +	writel_relaxed(intmask, emc->regs + EMC_INTMASK);
> +	writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS);
> +
> +	/* ensure that unwanted debug features are disabled */
> +	emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
> +	emc_dbg |= EMC_DBG_CFG_PRIORITY;
> +	emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
> +	emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
> +	emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
> +	writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
> +
> +	switch (emc->dram_type) {
> +	case DRAM_TYPE_DDR1:
> +		dram_type_str = "DDR1";
> +		break;
> +	case DRAM_TYPE_LPDDR2:
> +		dram_type_str = "LPDDR2";
> +		break;
> +	case DRAM_TYPE_DDR2:
> +		dram_type_str = "DDR2";
> +		break;
> +	case DRAM_TYPE_DDR3:
> +		dram_type_str = "DDR3";
> +		break;
> +	}
> +
> +	dev_info_once(emc->dev, "%u %s %s attached\n", emc->dram_num,
> +		      dram_type_str, emc->dram_num == 2 ? "devices" : "device");
> +
> +	emc_read_current_timing(emc, &emc->last_timing);
> +
> +	return 0;
> +}
> +
> +static int load_one_timing_from_dt(struct tegra_emc *emc,
> +				   struct emc_timing *timing,
> +				   struct device_node *node)
> +{
> +	u32 value;
> +	int err;
> +
> +	err = of_property_read_u32(node, "clock-frequency", &value);
> +	if (err) {
> +		dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n",
> +			node, err);
> +		return err;
> +	}
> +
> +	timing->rate = value;
> +
> +	err = of_property_read_u32_array(node, "nvidia,emc-configuration",
> +					 timing->emc_burst_data,
> +					 ARRAY_SIZE(timing->emc_burst_data));
> +	if (err) {
> +		dev_err(emc->dev,
> +			"timing %pOFn: failed to read emc burst data: %d\n",
> +			node, err);
> +		return err;
> +	}
> +
> +#define EMC_READ_PROP(prop, dtprop) { \
> +	err = of_property_read_u32(node, dtprop, &timing->prop); \
> +	if (err) { \
> +		dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \
> +			node, err); \
> +		return err; \
> +	} \
> +}
> +
> +	EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
> +	EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
> +	EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
> +	EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
> +	EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
> +	EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
> +	EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
> +	EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
> +	EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
> +	EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
> +	EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
> +	EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
> +	EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
> +	EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
> +	EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
> +
> +#undef EMC_READ_PROP
> +
> +	return 0;
> +}
> +
> +static int cmp_timings(const void *_a, const void *_b)
> +{
> +	const struct emc_timing *a = _a;
> +	const struct emc_timing *b = _b;
> +
> +	if (a->rate < b->rate)
> +		return -1;
> +	else if (a->rate == b->rate)
> +		return 0;
> +	else
> +		return 1;
> +}
> +
> +static int emc_check_mc_timings(struct tegra_emc *emc)
> +{
> +	struct tegra_mc *mc = emc->mc;
> +	unsigned int i;
> +
> +	if (emc->num_timings != mc->num_timings) {
> +		dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n",
> +			emc->num_timings, mc->num_timings);
> +		return -EINVAL;
> +	}
> +
> +	for (i = 0; i < mc->num_timings; i++) {
> +		if (emc->timings[i].rate != mc->timings[i].rate) {
> +			dev_err(emc->dev,
> +				"emc/mc timing rate mismatch: %lu %lu\n",
> +				emc->timings[i].rate, mc->timings[i].rate);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
> +					  struct device_node *node)
> +{
> +	int child_count = of_get_child_count(node);
> +	struct emc_timing *timing;
> +	unsigned int i = 0;
> +	int err;
> +
> +	emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
> +				    GFP_KERNEL);
> +	if (!emc->timings)
> +		return -ENOMEM;
> +
> +	emc->num_timings = child_count;
> +
> +	for_each_child_of_node_scoped(node, child) {
> +		timing = &emc->timings[i++];
> +
> +		err = load_one_timing_from_dt(emc, timing, child);
> +		if (err)
> +			return err;
> +	}
> +
> +	sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
> +	     NULL);
> +
> +	err = emc_check_mc_timings(emc);
> +	if (err)
> +		return err;
> +
> +	dev_info_once(emc->dev,
> +		      "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
> +		      emc->num_timings,
> +		      tegra_read_ram_code(),
> +		      emc->timings[0].rate / 1000000,
> +		      emc->timings[emc->num_timings - 1].rate / 1000000);
> +
> +	return 0;
> +}
> +
> +static struct device_node *
> +tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
> +{
> +	struct device_node *np;
> +	int err;
> +
> +	for_each_child_of_node(node, np) {
> +		u32 value;
> +
> +		err = of_property_read_u32(np, "nvidia,ram-code", &value);
> +		if (err || value != ram_code)
> +			continue;
> +
> +		return np;
> +	}
> +
> +	return NULL;
> +}
> +
> +static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
> +		emc->requested_rate[i].min_rate = 0;
> +		emc->requested_rate[i].max_rate = ULONG_MAX;
> +	}
> +}
> +
> +static int emc_request_rate(struct tegra_emc *emc,
> +			    unsigned long new_min_rate,
> +			    unsigned long new_max_rate,
> +			    enum emc_rate_request_type type)
> +{
> +	struct emc_rate_request *req = emc->requested_rate;
> +	unsigned long min_rate = 0, max_rate = ULONG_MAX;
> +	unsigned int i;
> +	int err;
> +
> +	/* select minimum and maximum rates among the requested rates */
> +	for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
> +		if (i == type) {
> +			min_rate = max(new_min_rate, min_rate);
> +			max_rate = min(new_max_rate, max_rate);
> +		} else {
> +			min_rate = max(req->min_rate, min_rate);
> +			max_rate = min(req->max_rate, max_rate);
> +		}
> +	}
> +
> +	if (min_rate > max_rate) {
> +		dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
> +				    __func__, type, min_rate, max_rate);
> +		return -ERANGE;
> +	}
> +
> +	/*
> +	 * EMC rate-changes should go via OPP API because it manages voltage
> +	 * changes.
> +	 */
> +	err = dev_pm_opp_set_rate(emc->dev, min_rate);
> +	if (err)
> +		return err;
> +
> +	emc->requested_rate[type].min_rate = new_min_rate;
> +	emc->requested_rate[type].max_rate = new_max_rate;
> +
> +	return 0;
> +}
> +
> +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
> +			    enum emc_rate_request_type type)
> +{
> +	struct emc_rate_request *req = &emc->requested_rate[type];
> +	int ret;
> +
> +	mutex_lock(&emc->rate_lock);
> +	ret = emc_request_rate(emc, rate, req->max_rate, type);
> +	mutex_unlock(&emc->rate_lock);
> +
> +	return ret;
> +}
> +
> +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
> +			    enum emc_rate_request_type type)
> +{
> +	struct emc_rate_request *req = &emc->requested_rate[type];
> +	int ret;
> +
> +	mutex_lock(&emc->rate_lock);
> +	ret = emc_request_rate(emc, req->min_rate, rate, type);
> +	mutex_unlock(&emc->rate_lock);
> +
> +	return ret;
> +}
> +
> +/*
> + * debugfs interface
> + *
> + * The memory controller driver exposes some files in debugfs that can be used
> + * to control the EMC frequency. The top-level directory can be found here:
> + *
> + *   /sys/kernel/debug/emc
> + *
> + * It contains the following files:
> + *
> + *   - available_rates: This file contains a list of valid, space-separated
> + *     EMC frequencies.
> + *
> + *   - min_rate: Writing a value to this file sets the given frequency as the
> + *       floor of the permitted range. If this is higher than the currently
> + *       configured EMC frequency, this will cause the frequency to be
> + *       increased so that it stays within the valid range.
> + *
> + *   - max_rate: Similarly to the min_rate file, writing a value to this file
> + *       sets the given frequency as the ceiling of the permitted range. If
> + *       the value is lower than the currently configured EMC frequency, this
> + *       will cause the frequency to be decreased so that it stays within the
> + *       valid range.
> + */
> +
> +static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < emc->num_timings; i++)
> +		if (rate == emc->timings[i].rate)
> +			return true;
> +
> +	return false;
> +}
> +
> +static int tegra_emc_debug_available_rates_show(struct seq_file *s,
> +						void *data)
> +{
> +	struct tegra_emc *emc = s->private;
> +	const char *prefix = "";
> +	unsigned int i;
> +
> +	for (i = 0; i < emc->num_timings; i++) {
> +		seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
> +		prefix = " ";
> +	}
> +
> +	seq_puts(s, "\n");
> +
> +	return 0;
> +}
> +
> +DEFINE_SHOW_ATTRIBUTE(tegra_emc_debug_available_rates);
> +
> +static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
> +{
> +	struct tegra_emc *emc = data;
> +
> +	*rate = emc->debugfs.min_rate;
> +
> +	return 0;
> +}
> +
> +static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
> +{
> +	struct tegra_emc *emc = data;
> +	int err;
> +
> +	if (!tegra_emc_validate_rate(emc, rate))
> +		return -EINVAL;
> +
> +	err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
> +	if (err < 0)
> +		return err;
> +
> +	emc->debugfs.min_rate = rate;
> +
> +	return 0;
> +}
> +
> +DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
> +			 tegra_emc_debug_min_rate_get,
> +			 tegra_emc_debug_min_rate_set, "%llu\n");
> +
> +static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
> +{
> +	struct tegra_emc *emc = data;
> +
> +	*rate = emc->debugfs.max_rate;
> +
> +	return 0;
> +}
> +
> +static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
> +{
> +	struct tegra_emc *emc = data;
> +	int err;
> +
> +	if (!tegra_emc_validate_rate(emc, rate))
> +		return -EINVAL;
> +
> +	err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
> +	if (err < 0)
> +		return err;
> +
> +	emc->debugfs.max_rate = rate;
> +
> +	return 0;
> +}
> +
> +DEFINE_DEBUGFS_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
> +			 tegra_emc_debug_max_rate_get,
> +			 tegra_emc_debug_max_rate_set, "%llu\n");
> +
> +static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc)
> +{
> +	unsigned int i;
> +	int err;
> +
> +	emc->debugfs.min_rate = ULONG_MAX;
> +	emc->debugfs.max_rate = 0;
> +
> +	for (i = 0; i < emc->num_timings; i++) {
> +		if (emc->timings[i].rate < emc->debugfs.min_rate)
> +			emc->debugfs.min_rate = emc->timings[i].rate;
> +
> +		if (emc->timings[i].rate > emc->debugfs.max_rate)
> +			emc->debugfs.max_rate = emc->timings[i].rate;
> +	}
> +
> +	if (!emc->num_timings) {
> +		emc->debugfs.min_rate = clk_get_rate(emc->clk);
> +		emc->debugfs.max_rate = emc->debugfs.min_rate;
> +	}
> +
> +	err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
> +				 emc->debugfs.max_rate);
> +	if (err < 0) {
> +		dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
> +			emc->debugfs.min_rate, emc->debugfs.max_rate,
> +			emc->clk);
> +		return;
> +	}
> +
> +	emc->debugfs.root = debugfs_create_dir("emc", NULL);
> +
> +	debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
> +			    &tegra_emc_debug_available_rates_fops);
> +	debugfs_create_file("min_rate", 0644, emc->debugfs.root,
> +			    emc, &tegra_emc_debug_min_rate_fops);
> +	debugfs_create_file("max_rate", 0644, emc->debugfs.root,
> +			    emc, &tegra_emc_debug_max_rate_fops);
> +}
> +
> +static inline struct tegra_emc *
> +to_tegra_emc_provider(struct icc_provider *provider)
> +{
> +	return container_of(provider, struct tegra_emc, provider);
> +}
> +
> +static struct icc_node_data *
> +emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
> +{
> +	struct icc_provider *provider = data;
> +	struct icc_node_data *ndata;
> +	struct icc_node *node;
> +
> +	/* External Memory is the only possible ICC route */
> +	list_for_each_entry(node, &provider->nodes, node_list) {
> +		if (node->id != TEGRA_ICC_EMEM)
> +			continue;
> +
> +		ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
> +		if (!ndata)
> +			return ERR_PTR(-ENOMEM);
> +
> +		/*
> +		 * SRC and DST nodes should have matching TAG in order to have
> +		 * it set by default for a requested path.
> +		 */
> +		ndata->tag = TEGRA_MC_ICC_TAG_ISO;
> +		ndata->node = node;
> +
> +		return ndata;
> +	}
> +
> +	return ERR_PTR(-EPROBE_DEFER);
> +}
> +
> +static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
> +{
> +	struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
> +	unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
> +	unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
> +	unsigned long long rate = max(avg_bw, peak_bw);
> +	unsigned int dram_data_bus_width_bytes = 4;
> +	const unsigned int ddr = 2;
> +	int err;
> +
> +	/*
> +	 * Tegra114 EMC runs on a clock rate of SDRAM bus. This means that
> +	 * EMC clock rate is twice smaller than the peak data rate because
> +	 * data is sampled on both EMC clock edges.
> +	 */
> +	do_div(rate, ddr * dram_data_bus_width_bytes);
> +	rate = min_t(u64, rate, U32_MAX);
> +
> +	err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
> +	if (err)
> +		return err;
> +
> +	return 0;
> +}
> +
> +static int tegra_emc_interconnect_init(struct tegra_emc *emc)
> +{
> +	const struct tegra_mc_soc *soc = emc->mc->soc;
> +	struct icc_node *node;
> +	int err;
> +
> +	emc->provider.dev = emc->dev;
> +	emc->provider.set = emc_icc_set;
> +	emc->provider.data = &emc->provider;
> +	emc->provider.aggregate = soc->icc_ops->aggregate;
> +	emc->provider.xlate_extended = emc_of_icc_xlate_extended;
> +
> +	icc_provider_init(&emc->provider);
> +
> +	/* create External Memory Controller node */
> +	node = icc_node_create(TEGRA_ICC_EMC);
> +	if (IS_ERR(node)) {
> +		err = PTR_ERR(node);
> +		goto err_msg;
> +	}
> +
> +	node->name = "External Memory Controller";
> +	icc_node_add(node, &emc->provider);
> +
> +	/* link External Memory Controller to External Memory (DRAM) */
> +	err = icc_link_create(node, TEGRA_ICC_EMEM);
> +	if (err)
> +		goto remove_nodes;
> +
> +	/* create External Memory node */
> +	node = icc_node_create(TEGRA_ICC_EMEM);
> +	if (IS_ERR(node)) {
> +		err = PTR_ERR(node);
> +		goto remove_nodes;
> +	}
> +
> +	node->name = "External Memory (DRAM)";
> +	icc_node_add(node, &emc->provider);
> +
> +	err = icc_provider_register(&emc->provider);
> +	if (err)
> +		goto remove_nodes;
> +
> +	return 0;
> +
> +remove_nodes:
> +	icc_nodes_remove(&emc->provider);
> +err_msg:
> +	dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
> +
> +	return err;
> +}
> +
> +static void devm_tegra_emc_unset_callback(void *data)
> +{
> +	tegra124_clk_set_emc_callbacks(NULL, NULL);
> +}
> +
> +static int tegra_emc_probe(struct platform_device *pdev)
> +{
> +	struct tegra_core_opp_params opp_params = {};
> +	struct device_node *np;
> +	struct tegra_emc *emc;
> +	u32 ram_code;
> +	int err;
> +
> +	emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
> +	if (!emc)
> +		return -ENOMEM;
> +
> +	mutex_init(&emc->rate_lock);
> +	emc->dev = &pdev->dev;
> +
> +	emc->regs = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(emc->regs))
> +		return PTR_ERR(emc->regs);
> +
> +	emc->mc = devm_tegra_memory_controller_get(&pdev->dev);
> +	if (IS_ERR(emc->mc))
> +		return PTR_ERR(emc->mc);
> +
> +	ram_code = tegra_read_ram_code();
> +
> +	np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
> +	if (np) {
> +		err = tegra_emc_load_timings_from_dt(emc, np);
> +		of_node_put(np);
> +		if (err)
> +			return err;
> +	} else {
> +		dev_info_once(&pdev->dev,
> +			      "no memory timings for RAM code %u found in DT\n",
> +			      ram_code);
> +	}
> +
> +	err = emc_init(emc);
> +	if (err) {
> +		dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
> +		return err;
> +	}
> +
> +	platform_set_drvdata(pdev, emc);
> +
> +	tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change,
> +				       tegra_emc_complete_timing_change);
> +
> +	err = devm_add_action_or_reset(&pdev->dev, devm_tegra_emc_unset_callback,
> +				       NULL);
> +	if (err)
> +		return err;
> +
> +	err = platform_get_irq(pdev, 0);
> +	if (err < 0)
> +		return err;
> +
> +	emc->irq = err;
> +
> +	err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0,
> +			       dev_name(&pdev->dev), emc);
> +	if (err) {
> +		dev_err(&pdev->dev, "failed to request irq: %d\n", err);
> +		return err;
> +	}
> +
> +	emc->clk = devm_clk_get(&pdev->dev, "emc");
> +	if (IS_ERR(emc->clk)) {
> +		err = PTR_ERR(emc->clk);
> +		dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
> +		return err;
> +	}
> +
> +	opp_params.init_state = true;
> +
> +	err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
> +	if (err)
> +		return err;
> +
> +	tegra_emc_rate_requests_init(emc);
> +
> +	if (IS_ENABLED(CONFIG_DEBUG_FS))
> +		emc_debugfs_init(&pdev->dev, emc);
> +
> +	tegra_emc_interconnect_init(emc);
> +
> +	/*
> +	 * Don't allow the kernel module to be unloaded. Unloading adds some
> +	 * extra complexity which doesn't really worth the effort in a case of
> +	 * this driver.
> +	 */
> +	try_module_get(THIS_MODULE);
> +
> +	return 0;
> +};
> +
> +static const struct of_device_id tegra_emc_of_match[] = {
> +	{ .compatible = "nvidia,tegra114-emc" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
> +
> +static struct platform_driver tegra_emc_driver = {
> +	.probe = tegra_emc_probe,
> +	.driver = {
> +		.name = "tegra114-emc",
> +		.of_match_table = tegra_emc_of_match,
> +		.suppress_bind_attrs = true,
> +		.sync_state = icc_sync_state,
> +	},
> +};
> +module_platform_driver(tegra_emc_driver);
> +
> +MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>");
> +MODULE_DESCRIPTION("NVIDIA Tegra114 EMC driver");
> +MODULE_LICENSE("GPL");
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v4 10/12] ARM: tegra: Add External Memory Controller node on Tegra114

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Add External Memory Controller node to the device-tree.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra114.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> index ef0618e9eec1..a920ad041c14 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -259,6 +259,8 @@ tegra_car: clock@60006000 {
>  		reg = <0x60006000 0x1000>;
>  		#clock-cells = <1>;
>  		#reset-cells = <1>;
> +
> +		nvidia,external-memory-controller = <&emc>;
>  	};
>  
>  	flow-controller@60007000 {
> @@ -655,6 +657,16 @@ mc: memory-controller@70019000 {
>  		#iommu-cells = <1>;
>  	};
>  
> +	emc: external-memory-controller@7001b000 {
> +		compatible = "nvidia,tegra114-emc";
> +		reg = <0x7001b000 0x1000>;

The TRM says that the aperture is 2K in size. Otherwise LGTM.

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

> +		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&tegra_car TEGRA114_CLK_EMC>;
> +		clock-names = "emc";
> +
> +		nvidia,memory-controller = <&mc>;
> +	};
> +
>  	hda@70030000 {
>  		compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda";
>  		reg = <0x70030000 0x10000>;
> 

Re: [PATCH v4 11/12] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Add EMC OPP tables and interconnect paths that will be used for
> dynamic memory bandwidth scaling based on memory utilization statistics.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 151 ++++++++++++++++++
>  arch/arm/boot/dts/nvidia/tegra114.dtsi        |   9 ++
>  2 files changed, 160 insertions(+)
>  create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> new file mode 100644
> index 000000000000..1a0e68f22039
> --- /dev/null
> +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> @@ -0,0 +1,151 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/ {
> +	emc_icc_dvfs_opp_table: opp-table-emc {
> +		compatible = "operating-points-v2";
> +
> +		opp-12750000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <12750000>;
> +			opp-supported-hw = <0x000F>;
> +		};

What's the source of the opp data?

Cheers,
Mikko

> +
> +		opp-20400000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <20400000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-40800000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <40800000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-68000000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <68000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-102000000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <102000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-204000000-900 {
> +			opp-microvolt = <900000 900000 1390000>;
> +			opp-hz = /bits/ 64 <204000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-suspend;
> +		};
> +
> +		opp-312000000-1000 {
> +			opp-microvolt = <1000000 1000000 1390000>;
> +			opp-hz = /bits/ 64 <312000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-408000000-1000 {
> +			opp-microvolt = <1000000 1000000 1390000>;
> +			opp-hz = /bits/ 64 <408000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-528000000-1050 {
> +			opp-microvolt = <1050000 1050000 1390000>;
> +			opp-hz = /bits/ 64 <528000000>;
> +			opp-supported-hw = <0x000E>;
> +		};
> +
> +		opp-528000000-1100 {
> +			opp-microvolt = <1100000 1100000 1390000>;
> +			opp-hz = /bits/ 64 <528000000>;
> +			opp-supported-hw = <0x0001>;
> +		};
> +
> +		opp-624000000-1100 {
> +			opp-microvolt = <1100000 1100000 1390000>;
> +			opp-hz = /bits/ 64 <624000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +
> +		opp-792000000-1100 {
> +			opp-microvolt = <1100000 1100000 1390000>;
> +			opp-hz = /bits/ 64 <792000000>;
> +			opp-supported-hw = <0x000F>;
> +		};
> +	};
> +
> +	emc_bw_dfs_opp_table: opp-table-actmon {
> +		compatible = "operating-points-v2";
> +
> +		opp-12750000 {
> +			opp-hz = /bits/ 64 <12750000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <204000>;
> +		};
> +
> +		opp-20400000 {
> +			opp-hz = /bits/ 64 <20400000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <326400>;
> +		};
> +
> +		opp-40800000 {
> +			opp-hz = /bits/ 64 <40800000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <652800>;
> +		};
> +
> +		opp-68000000 {
> +			opp-hz = /bits/ 64 <68000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <1088000>;
> +		};
> +
> +		opp-102000000 {
> +			opp-hz = /bits/ 64 <102000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <1632000>;
> +		};
> +
> +		opp-204000000 {
> +			opp-hz = /bits/ 64 <204000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <3264000>;
> +			opp-suspend;
> +		};
> +
> +		opp-312000000 {
> +			opp-hz = /bits/ 64 <312000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <4992000>;
> +		};
> +
> +		opp-408000000 {
> +			opp-hz = /bits/ 64 <408000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <6528000>;
> +		};
> +
> +		opp-528000000 {
> +			opp-hz = /bits/ 64 <528000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <8448000>;
> +		};
> +
> +		opp-624000000 {
> +			opp-hz = /bits/ 64 <624000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <9984000>;
> +		};
> +
> +		opp-792000000 {
> +			opp-hz = /bits/ 64 <792000000>;
> +			opp-supported-hw = <0x000F>;
> +			opp-peak-kBps = <12672000>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> index a920ad041c14..6221423b81d1 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -8,6 +8,8 @@
>  #include <dt-bindings/soc/tegra-pmc.h>
>  #include <dt-bindings/thermal/tegra114-soctherm.h>
>  
> +#include "tegra114-peripherals-opp.dtsi"
> +
>  / {
>  	compatible = "nvidia,tegra114";
>  	interrupt-parent = <&lic>;
> @@ -323,6 +325,9 @@ actmon: actmon@6000c800 {
>  		clock-names = "actmon", "emc";
>  		resets = <&tegra_car TEGRA114_CLK_ACTMON>;
>  		reset-names = "actmon";
> +		operating-points-v2 = <&emc_bw_dfs_opp_table>;
> +		interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
> +		interconnect-names = "cpu-read";
>  		#cooling-cells = <2>;
>  	};
>  
> @@ -655,6 +660,7 @@ mc: memory-controller@70019000 {
>  
>  		#reset-cells = <1>;
>  		#iommu-cells = <1>;
> +		#interconnect-cells = <1>;
>  	};
>  
>  	emc: external-memory-controller@7001b000 {
> @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 {
>  		clock-names = "emc";
>  
>  		nvidia,memory-controller = <&mc>;
> +		operating-points-v2 = <&emc_icc_dvfs_opp_table>;
> +
> +		#interconnect-cells = <0>;
>  	};
>  
>  	hda@70030000 {
> 

Re: [PATCH v4 12/12] ARM: tegra: add DC interconnections for Tegra114

[Mikko Perttunen]

On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> Add DC interconnections to Tegra114 device tree to reflect connections
> between MC, EMC and DC.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  arch/arm/boot/dts/nvidia/tegra114.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> index 6221423b81d1..732f8b5b4eed 100644
> --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> @@ -125,6 +125,17 @@ dc@54200000 {
>  
>  			nvidia,head = <0>;
>  
> +			interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>,
> +					<&mc TEGRA114_MC_DISPLAY0B &emc>,
> +					<&mc TEGRA114_MC_DISPLAY1B &emc>,
> +					<&mc TEGRA114_MC_DISPLAY0C &emc>,
> +					<&mc TEGRA114_MC_DISPLAYHC &emc>;
> +			interconnect-names = "wina",
> +					     "winb",
> +					     "winb-vfilter",
> +					     "winc",
> +					     "cursor";
> +
>  			rgb {
>  				status = "disabled";
>  			};
> @@ -144,6 +155,17 @@ dc@54240000 {
>  
>  			nvidia,head = <1>;
>  
> +			interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>,
> +					<&mc TEGRA114_MC_DISPLAY0BB &emc>,
> +					<&mc TEGRA114_MC_DISPLAY1BB &emc>,
> +					<&mc TEGRA114_MC_DISPLAY0CB &emc>,
> +					<&mc TEGRA114_MC_DISPLAYHCB &emc>;
> +			interconnect-names = "wina",
> +					     "winb",
> +					     "winb-vfilter",
> +					     "winc",
> +					     "cursor";
> +
>  			rgb {
>  				status = "disabled";
>  			};
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

Re: [PATCH v4 11/12] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes

[Svyatoslav Ryhel]

ср, 21 січ. 2026 р. о 09:56 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> > Add EMC OPP tables and interconnect paths that will be used for
> > dynamic memory bandwidth scaling based on memory utilization statistics.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> >  .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 151 ++++++++++++++++++
> >  arch/arm/boot/dts/nvidia/tegra114.dtsi        |   9 ++
> >  2 files changed, 160 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> >
> > diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > new file mode 100644
> > index 000000000000..1a0e68f22039
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > @@ -0,0 +1,151 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +/ {
> > +     emc_icc_dvfs_opp_table: opp-table-emc {
> > +             compatible = "operating-points-v2";
> > +
> > +             opp-12750000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <12750000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
>
> What's the source of the opp data?
>

I have used tf701t (T40X) and tegratab (T40S) kernel sources, to be
more specific board-*-memory.c files. Timing struct for each clock
contains min voltage field which was used to compose these opps.
1390000 is the max core regulator voltage, taken from tegra11_dvfs.c

I have converted an entire core_dvfs_table table from tegra11_dvfs.c
and I am planning to submit those later on too along with
powergates/domains configuration for tegra114, but that is for another
time :)

> Cheers,
> Mikko
>
> > +
> > +             opp-20400000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <20400000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-40800000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <40800000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-68000000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <68000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-102000000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <102000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-204000000-900 {
> > +                     opp-microvolt = <900000 900000 1390000>;
> > +                     opp-hz = /bits/ 64 <204000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-suspend;
> > +             };
> > +
> > +             opp-312000000-1000 {
> > +                     opp-microvolt = <1000000 1000000 1390000>;
> > +                     opp-hz = /bits/ 64 <312000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-408000000-1000 {
> > +                     opp-microvolt = <1000000 1000000 1390000>;
> > +                     opp-hz = /bits/ 64 <408000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-528000000-1050 {
> > +                     opp-microvolt = <1050000 1050000 1390000>;
> > +                     opp-hz = /bits/ 64 <528000000>;
> > +                     opp-supported-hw = <0x000E>;
> > +             };
> > +
> > +             opp-528000000-1100 {
> > +                     opp-microvolt = <1100000 1100000 1390000>;
> > +                     opp-hz = /bits/ 64 <528000000>;
> > +                     opp-supported-hw = <0x0001>;
> > +             };
> > +
> > +             opp-624000000-1100 {
> > +                     opp-microvolt = <1100000 1100000 1390000>;
> > +                     opp-hz = /bits/ 64 <624000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +
> > +             opp-792000000-1100 {
> > +                     opp-microvolt = <1100000 1100000 1390000>;
> > +                     opp-hz = /bits/ 64 <792000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +             };
> > +     };
> > +
> > +     emc_bw_dfs_opp_table: opp-table-actmon {
> > +             compatible = "operating-points-v2";
> > +
> > +             opp-12750000 {
> > +                     opp-hz = /bits/ 64 <12750000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <204000>;
> > +             };
> > +
> > +             opp-20400000 {
> > +                     opp-hz = /bits/ 64 <20400000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <326400>;
> > +             };
> > +
> > +             opp-40800000 {
> > +                     opp-hz = /bits/ 64 <40800000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <652800>;
> > +             };
> > +
> > +             opp-68000000 {
> > +                     opp-hz = /bits/ 64 <68000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <1088000>;
> > +             };
> > +
> > +             opp-102000000 {
> > +                     opp-hz = /bits/ 64 <102000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <1632000>;
> > +             };
> > +
> > +             opp-204000000 {
> > +                     opp-hz = /bits/ 64 <204000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <3264000>;
> > +                     opp-suspend;
> > +             };
> > +
> > +             opp-312000000 {
> > +                     opp-hz = /bits/ 64 <312000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <4992000>;
> > +             };
> > +
> > +             opp-408000000 {
> > +                     opp-hz = /bits/ 64 <408000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <6528000>;
> > +             };
> > +
> > +             opp-528000000 {
> > +                     opp-hz = /bits/ 64 <528000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <8448000>;
> > +             };
> > +
> > +             opp-624000000 {
> > +                     opp-hz = /bits/ 64 <624000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <9984000>;
> > +             };
> > +
> > +             opp-792000000 {
> > +                     opp-hz = /bits/ 64 <792000000>;
> > +                     opp-supported-hw = <0x000F>;
> > +                     opp-peak-kBps = <12672000>;
> > +             };
> > +     };
> > +};
> > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > index a920ad041c14..6221423b81d1 100644
> > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > @@ -8,6 +8,8 @@
> >  #include <dt-bindings/soc/tegra-pmc.h>
> >  #include <dt-bindings/thermal/tegra114-soctherm.h>
> >
> > +#include "tegra114-peripherals-opp.dtsi"
> > +
> >  / {
> >       compatible = "nvidia,tegra114";
> >       interrupt-parent = <&lic>;
> > @@ -323,6 +325,9 @@ actmon: actmon@6000c800 {
> >               clock-names = "actmon", "emc";
> >               resets = <&tegra_car TEGRA114_CLK_ACTMON>;
> >               reset-names = "actmon";
> > +             operating-points-v2 = <&emc_bw_dfs_opp_table>;
> > +             interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
> > +             interconnect-names = "cpu-read";
> >               #cooling-cells = <2>;
> >       };
> >
> > @@ -655,6 +660,7 @@ mc: memory-controller@70019000 {
> >
> >               #reset-cells = <1>;
> >               #iommu-cells = <1>;
> > +             #interconnect-cells = <1>;
> >       };
> >
> >       emc: external-memory-controller@7001b000 {
> > @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 {
> >               clock-names = "emc";
> >
> >               nvidia,memory-controller = <&mc>;
> > +             operating-points-v2 = <&emc_icc_dvfs_opp_table>;
> > +
> > +             #interconnect-cells = <0>;
> >       };
> >
> >       hda@70030000 {
> >
>
>
>
>

Re: [PATCH v4 11/12] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes

[Mikko Perttunen]

On Thursday, January 22, 2026 1:57 AM Svyatoslav Ryhel wrote:
> ср, 21 січ. 2026 р. о 09:56 Mikko Perttunen <mperttunen@nvidia.com> пише:
> >
> > On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> > > Add EMC OPP tables and interconnect paths that will be used for
> > > dynamic memory bandwidth scaling based on memory utilization statistics.
> > >
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > >  .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 151 ++++++++++++++++++
> > >  arch/arm/boot/dts/nvidia/tegra114.dtsi        |   9 ++
> > >  2 files changed, 160 insertions(+)
> > >  create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > >
> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > > new file mode 100644
> > > index 000000000000..1a0e68f22039
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > > @@ -0,0 +1,151 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +
> > > +/ {
> > > +     emc_icc_dvfs_opp_table: opp-table-emc {
> > > +             compatible = "operating-points-v2";
> > > +
> > > +             opp-12750000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <12750000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> >
> > What's the source of the opp data?
> >
> 
> I have used tf701t (T40X) and tegratab (T40S) kernel sources, to be
> more specific board-*-memory.c files. Timing struct for each clock
> contains min voltage field which was used to compose these opps.
> 1390000 is the max core regulator voltage, taken from tegra11_dvfs.c

Thanks! I also looked through SHIELD Portable (roth, T40T) memory tables and this appears to match except for the 528MHz opp.

The opp table here is setting the voltage for the 528MHz opp to 1050mV for the high end SKUs (T40X and T40T)[1] and 1100mV for the lower end T40S, which makes sense. However, the roth memory table (rel-roth branch) specifies 1100mV for the 528MHz opp. My understanding is T40T is supposed to be at least as good silicon as T40X, so it doesn't make sense to me that it would require a higher voltage, but memory timings are a dark art and I would err on the baseline side and keep the voltage at 1100mV. Let me know what you think or if you have additional information.

FWIW, roth also specifies a 900MHz opp. I think in principle T40X/T40T in general can reach this but it might only have been characterized for roth.

[1] T40X is SKU 0x3 and T40T is SKU 0x4, and these are mapped to soc_speedo_id=1 -> supported_hw BIT(1).

> 
> I have converted an entire core_dvfs_table table from tegra11_dvfs.c
> and I am planning to submit those later on too along with
> powergates/domains configuration for tegra114, but that is for another
> time :)

Sounds good!

Thanks,
Mikko

> 
> > Cheers,
> > Mikko
> >
> > > +
> > > +             opp-20400000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <20400000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-40800000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <40800000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-68000000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <68000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-102000000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <102000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-204000000-900 {
> > > +                     opp-microvolt = <900000 900000 1390000>;
> > > +                     opp-hz = /bits/ 64 <204000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-suspend;
> > > +             };
> > > +
> > > +             opp-312000000-1000 {
> > > +                     opp-microvolt = <1000000 1000000 1390000>;
> > > +                     opp-hz = /bits/ 64 <312000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-408000000-1000 {
> > > +                     opp-microvolt = <1000000 1000000 1390000>;
> > > +                     opp-hz = /bits/ 64 <408000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-528000000-1050 {
> > > +                     opp-microvolt = <1050000 1050000 1390000>;
> > > +                     opp-hz = /bits/ 64 <528000000>;
> > > +                     opp-supported-hw = <0x000E>;
> > > +             };
> > > +
> > > +             opp-528000000-1100 {
> > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > +                     opp-hz = /bits/ 64 <528000000>;
> > > +                     opp-supported-hw = <0x0001>;
> > > +             };
> > > +
> > > +             opp-624000000-1100 {
> > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > +                     opp-hz = /bits/ 64 <624000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +
> > > +             opp-792000000-1100 {
> > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > +                     opp-hz = /bits/ 64 <792000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +             };
> > > +     };
> > > +
> > > +     emc_bw_dfs_opp_table: opp-table-actmon {
> > > +             compatible = "operating-points-v2";
> > > +
> > > +             opp-12750000 {
> > > +                     opp-hz = /bits/ 64 <12750000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <204000>;
> > > +             };
> > > +
> > > +             opp-20400000 {
> > > +                     opp-hz = /bits/ 64 <20400000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <326400>;
> > > +             };
> > > +
> > > +             opp-40800000 {
> > > +                     opp-hz = /bits/ 64 <40800000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <652800>;
> > > +             };
> > > +
> > > +             opp-68000000 {
> > > +                     opp-hz = /bits/ 64 <68000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <1088000>;
> > > +             };
> > > +
> > > +             opp-102000000 {
> > > +                     opp-hz = /bits/ 64 <102000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <1632000>;
> > > +             };
> > > +
> > > +             opp-204000000 {
> > > +                     opp-hz = /bits/ 64 <204000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <3264000>;
> > > +                     opp-suspend;
> > > +             };
> > > +
> > > +             opp-312000000 {
> > > +                     opp-hz = /bits/ 64 <312000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <4992000>;
> > > +             };
> > > +
> > > +             opp-408000000 {
> > > +                     opp-hz = /bits/ 64 <408000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <6528000>;
> > > +             };
> > > +
> > > +             opp-528000000 {
> > > +                     opp-hz = /bits/ 64 <528000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <8448000>;
> > > +             };
> > > +
> > > +             opp-624000000 {
> > > +                     opp-hz = /bits/ 64 <624000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <9984000>;
> > > +             };
> > > +
> > > +             opp-792000000 {
> > > +                     opp-hz = /bits/ 64 <792000000>;
> > > +                     opp-supported-hw = <0x000F>;
> > > +                     opp-peak-kBps = <12672000>;
> > > +             };
> > > +     };
> > > +};
> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > index a920ad041c14..6221423b81d1 100644
> > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > @@ -8,6 +8,8 @@
> > >  #include <dt-bindings/soc/tegra-pmc.h>
> > >  #include <dt-bindings/thermal/tegra114-soctherm.h>
> > >
> > > +#include "tegra114-peripherals-opp.dtsi"
> > > +
> > >  / {
> > >       compatible = "nvidia,tegra114";
> > >       interrupt-parent = <&lic>;
> > > @@ -323,6 +325,9 @@ actmon: actmon@6000c800 {
> > >               clock-names = "actmon", "emc";
> > >               resets = <&tegra_car TEGRA114_CLK_ACTMON>;
> > >               reset-names = "actmon";
> > > +             operating-points-v2 = <&emc_bw_dfs_opp_table>;
> > > +             interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
> > > +             interconnect-names = "cpu-read";
> > >               #cooling-cells = <2>;
> > >       };
> > >
> > > @@ -655,6 +660,7 @@ mc: memory-controller@70019000 {
> > >
> > >               #reset-cells = <1>;
> > >               #iommu-cells = <1>;
> > > +             #interconnect-cells = <1>;
> > >       };
> > >
> > >       emc: external-memory-controller@7001b000 {
> > > @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 {
> > >               clock-names = "emc";
> > >
> > >               nvidia,memory-controller = <&mc>;
> > > +             operating-points-v2 = <&emc_icc_dvfs_opp_table>;
> > > +
> > > +             #interconnect-cells = <0>;
> > >       };
> > >
> > >       hda@70030000 {
> > >
> >
> >
> >
> >

Re: [PATCH v4 11/12] ARM: tegra: Add EMC OPP and ICC properties to Tegra114 EMC and ACTMON device-tree nodes

[Svyatoslav Ryhel]

чт, 22 січ. 2026 р. о 07:46 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Thursday, January 22, 2026 1:57 AM Svyatoslav Ryhel wrote:
> > ср, 21 січ. 2026 р. о 09:56 Mikko Perttunen <mperttunen@nvidia.com> пише:
> > >
> > > On Tuesday, November 25, 2025 9:05 PM Svyatoslav Ryhel wrote:
> > > > Add EMC OPP tables and interconnect paths that will be used for
> > > > dynamic memory bandwidth scaling based on memory utilization statistics.
> > > >
> > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > > ---
> > > >  .../dts/nvidia/tegra114-peripherals-opp.dtsi  | 151 ++++++++++++++++++
> > > >  arch/arm/boot/dts/nvidia/tegra114.dtsi        |   9 ++
> > > >  2 files changed, 160 insertions(+)
> > > >  create mode 100644 arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > > >
> > > > diff --git a/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > > > new file mode 100644
> > > > index 000000000000..1a0e68f22039
> > > > --- /dev/null
> > > > +++ b/arch/arm/boot/dts/nvidia/tegra114-peripherals-opp.dtsi
> > > > @@ -0,0 +1,151 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +
> > > > +/ {
> > > > +     emc_icc_dvfs_opp_table: opp-table-emc {
> > > > +             compatible = "operating-points-v2";
> > > > +
> > > > +             opp-12750000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <12750000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > >
> > > What's the source of the opp data?
> > >
> >
> > I have used tf701t (T40X) and tegratab (T40S) kernel sources, to be
> > more specific board-*-memory.c files. Timing struct for each clock
> > contains min voltage field which was used to compose these opps.
> > 1390000 is the max core regulator voltage, taken from tegra11_dvfs.c
>
> Thanks! I also looked through SHIELD Portable (roth, T40T) memory tables and this appears to match except for the 528MHz opp.
>
> The opp table here is setting the voltage for the 528MHz opp to 1050mV for the high end SKUs (T40X and T40T)[1] and 1100mV for the lower end T40S, which makes sense. However, the roth memory table (rel-roth branch) specifies 1100mV for the 528MHz opp. My understanding is T40T is supposed to be at least as good silicon as T40X, so it doesn't make sense to me that it would require a higher voltage, but memory timings are a dark art and I would err on the baseline side and keep the voltage at 1100mV. Let me know what you think or if you have additional information.

If roth requires 1100mV for 528MHz opp there should be a reason for
that, maybe we are just not aware or it since it may be not
documented/not public/empirical. I see no issue in setting it to
1100mV for both T40X and T40T since they both can work with this
voltage. I will add a comment in case there will be enough T40T users
who can check if 1050mV for 528MHz work stable enough to lower voltage
later on.

>
> FWIW, roth also specifies a 900MHz opp. I think in principle T40X/T40T in general can reach this but it might only have been characterized for roth.
>

Very nice, then I will include 900MHz opp in the next iteration. It is
always better to have a wider coverage. Thank you!

Best regards,
Svyatoslav R.

> [1] T40X is SKU 0x3 and T40T is SKU 0x4, and these are mapped to soc_speedo_id=1 -> supported_hw BIT(1).
>
> >
> > I have converted an entire core_dvfs_table table from tegra11_dvfs.c
> > and I am planning to submit those later on too along with
> > powergates/domains configuration for tegra114, but that is for another
> > time :)
>
> Sounds good!
>
> Thanks,
> Mikko
>
> >
> > > Cheers,
> > > Mikko
> > >
> > > > +
> > > > +             opp-20400000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <20400000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-40800000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <40800000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-68000000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <68000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-102000000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <102000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-204000000-900 {
> > > > +                     opp-microvolt = <900000 900000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <204000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-suspend;
> > > > +             };
> > > > +
> > > > +             opp-312000000-1000 {
> > > > +                     opp-microvolt = <1000000 1000000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <312000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-408000000-1000 {
> > > > +                     opp-microvolt = <1000000 1000000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <408000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-528000000-1050 {
> > > > +                     opp-microvolt = <1050000 1050000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <528000000>;
> > > > +                     opp-supported-hw = <0x000E>;
> > > > +             };
> > > > +
> > > > +             opp-528000000-1100 {
> > > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <528000000>;
> > > > +                     opp-supported-hw = <0x0001>;
> > > > +             };
> > > > +
> > > > +             opp-624000000-1100 {
> > > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <624000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +
> > > > +             opp-792000000-1100 {
> > > > +                     opp-microvolt = <1100000 1100000 1390000>;
> > > > +                     opp-hz = /bits/ 64 <792000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +             };
> > > > +     };
> > > > +
> > > > +     emc_bw_dfs_opp_table: opp-table-actmon {
> > > > +             compatible = "operating-points-v2";
> > > > +
> > > > +             opp-12750000 {
> > > > +                     opp-hz = /bits/ 64 <12750000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <204000>;
> > > > +             };
> > > > +
> > > > +             opp-20400000 {
> > > > +                     opp-hz = /bits/ 64 <20400000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <326400>;
> > > > +             };
> > > > +
> > > > +             opp-40800000 {
> > > > +                     opp-hz = /bits/ 64 <40800000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <652800>;
> > > > +             };
> > > > +
> > > > +             opp-68000000 {
> > > > +                     opp-hz = /bits/ 64 <68000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <1088000>;
> > > > +             };
> > > > +
> > > > +             opp-102000000 {
> > > > +                     opp-hz = /bits/ 64 <102000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <1632000>;
> > > > +             };
> > > > +
> > > > +             opp-204000000 {
> > > > +                     opp-hz = /bits/ 64 <204000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <3264000>;
> > > > +                     opp-suspend;
> > > > +             };
> > > > +
> > > > +             opp-312000000 {
> > > > +                     opp-hz = /bits/ 64 <312000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <4992000>;
> > > > +             };
> > > > +
> > > > +             opp-408000000 {
> > > > +                     opp-hz = /bits/ 64 <408000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <6528000>;
> > > > +             };
> > > > +
> > > > +             opp-528000000 {
> > > > +                     opp-hz = /bits/ 64 <528000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <8448000>;
> > > > +             };
> > > > +
> > > > +             opp-624000000 {
> > > > +                     opp-hz = /bits/ 64 <624000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <9984000>;
> > > > +             };
> > > > +
> > > > +             opp-792000000 {
> > > > +                     opp-hz = /bits/ 64 <792000000>;
> > > > +                     opp-supported-hw = <0x000F>;
> > > > +                     opp-peak-kBps = <12672000>;
> > > > +             };
> > > > +     };
> > > > +};
> > > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > > index a920ad041c14..6221423b81d1 100644
> > > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
> > > > @@ -8,6 +8,8 @@
> > > >  #include <dt-bindings/soc/tegra-pmc.h>
> > > >  #include <dt-bindings/thermal/tegra114-soctherm.h>
> > > >
> > > > +#include "tegra114-peripherals-opp.dtsi"
> > > > +
> > > >  / {
> > > >       compatible = "nvidia,tegra114";
> > > >       interrupt-parent = <&lic>;
> > > > @@ -323,6 +325,9 @@ actmon: actmon@6000c800 {
> > > >               clock-names = "actmon", "emc";
> > > >               resets = <&tegra_car TEGRA114_CLK_ACTMON>;
> > > >               reset-names = "actmon";
> > > > +             operating-points-v2 = <&emc_bw_dfs_opp_table>;
> > > > +             interconnects = <&mc TEGRA114_MC_MPCORER &emc>;
> > > > +             interconnect-names = "cpu-read";
> > > >               #cooling-cells = <2>;
> > > >       };
> > > >
> > > > @@ -655,6 +660,7 @@ mc: memory-controller@70019000 {
> > > >
> > > >               #reset-cells = <1>;
> > > >               #iommu-cells = <1>;
> > > > +             #interconnect-cells = <1>;
> > > >       };
> > > >
> > > >       emc: external-memory-controller@7001b000 {
> > > > @@ -665,6 +671,9 @@ emc: external-memory-controller@7001b000 {
> > > >               clock-names = "emc";
> > > >
> > > >               nvidia,memory-controller = <&mc>;
> > > > +             operating-points-v2 = <&emc_icc_dvfs_opp_table>;
> > > > +
> > > > +             #interconnect-cells = <0>;
> > > >       };
> > > >
> > > >       hda@70030000 {
> > > >
> > >
> > >
> > >
> > >
>
>
>
>