* [PATCH 0/6] AMCC 440SP/Luan board enhancements & fixes @ 2006-03-01 23:35 Wade Farnsworth 2006-03-01 23:45 ` [PATCH 1/6] Support for UART 2 on 440SP and Luan Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:35 UTC (permalink / raw) To: linuxppc-embedded Greetings, The following patches are enhancements and/or fixes for the AMCC 440SP SoC and the Luan board. Most notably there is support for UART2 and the L2 Cache, as well as increased flexibility for the PCIX bridges. --Wade Farnsworth ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/6] Support for UART 2 on 440SP and Luan 2006-03-01 23:35 [PATCH 0/6] AMCC 440SP/Luan board enhancements & fixes Wade Farnsworth @ 2006-03-01 23:45 ` Wade Farnsworth 2006-03-01 23:47 ` [PATCH 2/6] Add UIC settings for 440SP & Luan Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:45 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 204 bytes --] This fixes the IRQ number for UART 2 on the 440SP and adds support to ibm440gx_get_clocks() for it. It also enables the UART on the Luan. --Wade Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-uart2.patch --] [-- Type: text/x-patch, Size: 2731 bytes --] diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h --- a/arch/ppc/platforms/4xx/ibm440sp.h +++ b/arch/ppc/platforms/4xx/ibm440sp.h @@ -27,7 +27,7 @@ #define PPC440SP_UART2_ADDR 0x00000001f0000600ULL #define UART0_INT 0 #define UART1_INT 1 -#define UART2_INT 2 +#define UART2_INT 37 /* Clock and Power Management */ #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -296,9 +296,12 @@ luan_early_serial_map(void) printk("Early serial init of port 1 failed\n"); } + /* Enable UART2 */ + SDR_WRITE(DCRN_SDR_PFC1, SDR_READ(DCRN_SDR_PFC1) | 0x01000000); + port.membase = ioremap64(PPC440SP_UART2_ADDR, 8); port.irq = UART2_INT; - port.uartclk = BASE_BAUD; + port.uartclk = clocks.uart2; port.line = 2; if (early_serial_setup(&port) != 0) { diff --git a/arch/ppc/syslib/ibm440gx_common.c b/arch/ppc/syslib/ibm440gx_common.c --- a/arch/ppc/syslib/ibm440gx_common.c +++ b/arch/ppc/syslib/ibm440gx_common.c @@ -34,8 +34,10 @@ void __init ibm440gx_get_clocks(struct i u32 plld = CPR_READ(DCRN_CPR_PLLD); u32 uart0 = SDR_READ(DCRN_SDR_UART0); u32 uart1 = SDR_READ(DCRN_SDR_UART1); -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440SP) u32 uart2 = SDR_READ(DCRN_SDR_UART2); +#endif +#if defined(CONFIG_440EP) u32 uart3 = SDR_READ(DCRN_SDR_UART3); #endif @@ -100,12 +102,15 @@ bypass: p->uart1 = ser_clk; else p->uart1 = p->plb / __fix_zero(uart1 & 0xff, 256); -#ifdef CONFIG_440EP + +#if defined(CONFIG_440EP) || (CONFIG_440SP) if (uart2 & 0x00800000) p->uart2 = ser_clk; else p->uart2 = p->plb / __fix_zero(uart2 & 0xff, 256); +#endif +#ifdef CONFIG_440EP if (uart3 & 0x00800000) p->uart3 = ser_clk; else diff --git a/arch/ppc/syslib/ibm44x_common.h b/arch/ppc/syslib/ibm44x_common.h --- a/arch/ppc/syslib/ibm44x_common.h +++ b/arch/ppc/syslib/ibm44x_common.h @@ -29,8 +29,10 @@ struct ibm44x_clocks { unsigned int ebc; /* PerClk */ unsigned int uart0; unsigned int uart1; -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440SP) unsigned int uart2; +#endif +#if defined(CONFIG_440EP) unsigned int uart3; #endif }; diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -179,8 +179,10 @@ #define DCRN_SDR_UART0 0x0120 #define DCRN_SDR_UART1 0x0121 -#ifdef CONFIG_440EP +#if defined(CONFIG_440EP) || defined(CONFIG_440SP) #define DCRN_SDR_UART2 0x0122 +#endif +#if defined(CONFIG_440EP) #define DCRN_SDR_UART3 0x0123 #define DCRN_SDR_CUST0 0x4000 #endif ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/6] Add UIC settings for 440SP & Luan 2006-03-01 23:45 ` [PATCH 1/6] Support for UART 2 on 440SP and Luan Wade Farnsworth @ 2006-03-01 23:47 ` Wade Farnsworth 2006-03-01 23:50 ` [PATCH 3/6] PCIX fixes and enhancements " Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:47 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 156 bytes --] This adds the necessary structures for the UIC polarity and triggering on the 440SP & Luan. -Wade Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-uic.patch --] [-- Type: text/x-patch, Size: 1590 bytes --] diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c --- a/arch/ppc/platforms/4xx/ibm440sp.c +++ b/arch/ppc/platforms/4xx/ibm440sp.c @@ -19,6 +19,7 @@ #include <linux/module.h> #include <platforms/4xx/ibm440sp.h> #include <asm/ocp.h> +#include <asm/ppc4xx_pic.h> static struct ocp_func_emac_data ibm440sp_emac0_def = { .rgmii_idx = -1, /* No RGMII */ @@ -129,3 +130,15 @@ struct ocp_def core_ocp[] = { { .vendor = OCP_VENDOR_INVALID } }; + +/* Polarity and triggering settings for internal interrupt sources */ +struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { + { .polarity = 0xffffffff, + .triggering = 0x01084004, + .ext_irq_mask = 0x00000000, + }, + { .polarity = 0x7fff83ff, + .triggering = 0x00000000, + .ext_irq_mask = 0x80007c00, /* IRQ7 - IRQ9 */ + }, +}; diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -56,6 +56,18 @@ extern bd_t __res; static struct ibm44x_clocks clocks __initdata; +/* + * Luan external IRQ triggering/polarity settings + */ +unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = { + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ3 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4 */ + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5 */ +}; + static void __init luan_calibrate_decr(void) { ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/6] PCIX fixes and enhancements for 440SP & Luan 2006-03-01 23:47 ` [PATCH 2/6] Add UIC settings for 440SP & Luan Wade Farnsworth @ 2006-03-01 23:50 ` Wade Farnsworth 2006-03-01 23:51 ` [PATCH 4/6] L2 Cache support for 440SP Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:50 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 249 bytes --] This patch allows each bridge on the 440SP to be configured for both host and adapter mode. Previously, PCIX0 was configured for adapter mode only. Also fixes PCIXn_IO_BASE for PCIX1 and 2. Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-pcix.patch --] [-- Type: text/x-patch, Size: 4304 bytes --] diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -95,9 +95,7 @@ luan_map_irq(struct pci_dev *dev, unsign { struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); - /* PCIX0 in adapter mode, no host interrupt routing */ - - /* PCIX1 */ + /* PCIX0 */ if (hose->index == 0) { static char pci_irq_table[][4] = /* @@ -105,6 +103,21 @@ luan_map_irq(struct pci_dev *dev, unsign * A B C D */ { + { 32, 32, 32, 32 }, /* IDSEL 1 - PCIX0 Slot 0 */ + { 32, 32, 32, 32 }, /* IDSEL 2 - PCIX0 Slot 1 */ + { 32, 32, 32, 32 }, /* IDSEL 3 - PCIX0 Slot 2 */ + { 32, 32, 32, 32 }, /* IDSEL 4 - PCIX0 Slot 3 */ + }; + const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + /* PCIX1 */ + } else if (hose->index == 1) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { { 49, 49, 49, 49 }, /* IDSEL 1 - PCIX1 Slot 0 */ { 49, 49, 49, 49 }, /* IDSEL 2 - PCIX1 Slot 1 */ { 49, 49, 49, 49 }, /* IDSEL 3 - PCIX1 Slot 2 */ @@ -113,7 +126,7 @@ luan_map_irq(struct pci_dev *dev, unsign const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4; return PCI_IRQ_TABLE_LOOKUP; /* PCIX2 */ - } else if (hose->index == 1) { + } else if (hose->index == 2) { static char pci_irq_table[][4] = /* * PCI IDSEL/INTPIN->INTLINE @@ -237,42 +250,70 @@ luan_setup_hose(struct pci_controller *h static void __init luan_setup_hoses(void) { - struct pci_controller *hose1, *hose2; + struct pci_controller *hose0, *hose1, *hose2; + int last_busno = -1; /* Configure windows on the PCI-X host bridge */ luan_setup_pcix(); + + /* Setup PCIX0 */ + if (SDR_READ(0x01c0) & 0x20000000) { + hose0 = pcibios_alloc_controller(); + if (!hose0) + return; + hose0->first_busno = 0; + hose0->last_busno = 0xff; + hose0->index = 0; + + luan_setup_hose(hose0, + LUAN_PCIX0_LOWER_MEM, + LUAN_PCIX0_UPPER_MEM, + PCIX0_CFGA, + PCIX0_CFGD, + PCIX0_IO_BASE); - /* Allocate hoses for PCIX1 and PCIX2 */ - hose1 = pcibios_alloc_controller(); - hose2 = pcibios_alloc_controller(); - if (!hose1 || !hose2) - return; + last_busno = hose0->last_busno = + pciauto_bus_scan(hose0, hose0->first_busno); + } /* Setup PCIX1 */ - hose1->first_busno = 0; - hose1->last_busno = 0xff; - - luan_setup_hose(hose1, - LUAN_PCIX1_LOWER_MEM, - LUAN_PCIX1_UPPER_MEM, - PCIX1_CFGA, - PCIX1_CFGD, - PCIX1_IO_BASE); + if (SDR_READ(0x01c3) & 0x20000000) { + hose1 = pcibios_alloc_controller(); + if (!hose1) + return; + hose1->first_busno = last_busno + 1; + hose1->last_busno = 0xff; + hose1->index = 1; + + luan_setup_hose(hose1, + LUAN_PCIX1_LOWER_MEM, + LUAN_PCIX1_UPPER_MEM, + PCIX1_CFGA, + PCIX1_CFGD, + PCIX1_IO_BASE); - hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno); + last_busno = hose1->last_busno = + pciauto_bus_scan(hose1, hose1->first_busno); + } /* Setup PCIX2 */ - hose2->first_busno = hose1->last_busno + 1; - hose2->last_busno = 0xff; + if (SDR_READ(0x01c6) & 0x20000000) { + hose2 = pcibios_alloc_controller(); + if (!hose2) + return; + hose2->first_busno = last_busno + 1; + hose2->last_busno = 0xff; + hose2->index = 2; + + luan_setup_hose(hose2, + LUAN_PCIX2_LOWER_MEM, + LUAN_PCIX2_UPPER_MEM, + PCIX2_CFGA, + PCIX2_CFGD, + PCIX2_IO_BASE); - luan_setup_hose(hose2, - LUAN_PCIX2_LOWER_MEM, - LUAN_PCIX2_UPPER_MEM, - PCIX2_CFGA, - PCIX2_CFGD, - PCIX2_IO_BASE); - - hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); + hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno); + } ppc_md.pci_swizzle = common_swizzle; ppc_md.pci_map_irq = luan_map_irq; diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -560,8 +560,8 @@ #define PCIX2_CFGD 0x2ec00004UL #define PCIX0_IO_BASE 0x0000000908000000ULL -#define PCIX1_IO_BASE 0x0000000908000000ULL -#define PCIX2_IO_BASE 0x0000000908000000ULL +#define PCIX1_IO_BASE 0x0000000918000000ULL +#define PCIX2_IO_BASE 0x0000000928000000ULL #define PCIX_IO_SIZE 0x00010000 #ifdef CONFIG_440SP ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 4/6] L2 Cache support for 440SP 2006-03-01 23:50 ` [PATCH 3/6] PCIX fixes and enhancements " Wade Farnsworth @ 2006-03-01 23:51 ` Wade Farnsworth 2006-03-01 23:52 ` [PATCH 5/6] Clock and power management define fixes " Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:51 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 107 bytes --] This adds L2 Cache support for the 440SP. --Wade Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-l2c.patch --] [-- Type: text/x-patch, Size: 636 bytes --] diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c --- a/arch/ppc/platforms/4xx/luan.c +++ b/arch/ppc/platforms/4xx/luan.c @@ -408,6 +408,11 @@ luan_setup_arch(void) printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n"); } +static void __init luan_init(void) +{ + ibm440gx_l2c_setup(&clocks); +} + void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) { @@ -422,4 +427,5 @@ void __init platform_init(unsigned long #ifdef CONFIG_KGDB ppc_md.early_serial_map = luan_early_serial_map; #endif + ppc_md.init = luan_init; } ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 5/6] Clock and power management define fixes for 440SP 2006-03-01 23:51 ` [PATCH 4/6] L2 Cache support for 440SP Wade Farnsworth @ 2006-03-01 23:52 ` Wade Farnsworth 2006-03-01 23:54 ` [PATCH 6/6] MTD defines for Luan Wade Farnsworth 0 siblings, 1 reply; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:52 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 129 bytes --] This fixes the clock and power management defines on the 440SP. --Wade Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-cpm.patch --] [-- Type: text/x-patch, Size: 2672 bytes --] diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h --- a/arch/ppc/platforms/4xx/ibm440sp.h +++ b/arch/ppc/platforms/4xx/ibm440sp.h @@ -32,33 +32,28 @@ /* Clock and Power Management */ #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ #define IBM_CPM_IIC1 0x40000000 /* IIC interface */ -#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ -#define IBM_CPM_CPU 0x02000000 /* processor core */ -#define IBM_CPM_DMA 0x01000000 /* DMA controller */ -#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ -#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ -#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ -#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ -#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ -#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ +#define IBM_CPM_PCIX0 0x20000000 /* PCIX bridge 0 */ +#define IBM_CPM_PCIX1 0x10000000 /* PCIX bridge 1 */ +#define IBM_CPM_PCIX2 0x08000000 /* PCIX bridge 2 */ +#define IBM_CPM_CPU 0x02000000 /* processor core */ +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ +#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ +#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ -#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ -#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ #define IBM_CPM_UART0 0x00000200 /* serial port 0 */ #define IBM_CPM_UART1 0x00000100 /* serial port 1 */ -#define IBM_CPM_UART2 0x00000100 /* serial port 1 */ #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ #define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ +#define IBM_CPM_UART2 0x00000010 /* serial port 2 */ -#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \ | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ - | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ - | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ - | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ - | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ - | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) + | IBM_CPM_PLB | IBM_CPM_TMRCLK | IBM_CPM_PCIX0 \ + | IBM_CPM_PCIX1 | IBM_CPM_PCIX2\ + | IBM_CPM_EMAC0 ) #endif /* __PPC_PLATFORMS_IBM440SP_H */ #endif /* __KERNEL__ */ ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 6/6] MTD defines for Luan 2006-03-01 23:52 ` [PATCH 5/6] Clock and power management define fixes " Wade Farnsworth @ 2006-03-01 23:54 ` Wade Farnsworth 0 siblings, 0 replies; 7+ messages in thread From: Wade Farnsworth @ 2006-03-01 23:54 UTC (permalink / raw) To: linuxppc-embedded [-- Attachment #1: Type: text/plain, Size: 131 bytes --] This fixes the defines for MTD support in the Luan platform file. --Wade Signed off by: Wade Farnsworth <wfarnsworth@mvista.com> [-- Attachment #2: luan-mtd-defs.patch --] [-- Type: text/x-patch, Size: 1412 bytes --] diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h --- a/arch/ppc/platforms/4xx/luan.h +++ b/arch/ppc/platforms/4xx/luan.h @@ -32,14 +32,28 @@ #define LUAN_TMR_CLK 25000000 /* Flash */ -#define LUAN_FPGA_REG_0 0x0000000148300000ULL +#define LUAN_FPGA_REG_0 0x00000001f8000000ULL +#define LUAN_CONFIG_MASK 0x43 +#define LUAN_CONFIG_1 0x41 +#define LUAN_CONFIG_2 0x40 +#define LUAN_CONFIG_3 0x01 +#define LUAN_CONFIG_4 0x00 #define LUAN_BOOT_LARGE_FLASH(x) (x & 0x40) -#define LUAN_SMALL_FLASH_LOW 0x00000001ff900000ULL -#define LUAN_SMALL_FLASH_HIGH 0x00000001ffe00000ULL +#define LUAN_SMALL_FLASH_LOW 0x00000001f9900000ULL +#define LUAN_SMALL_FLASH_LOW4 0x00000001f9800000ULL +#define LUAN_SMALL_FLASH_HIGH 0x00000001fff00000ULL +#define LUAN_SMALL_FLASH_HIGH2 0x00000001ffe00000ULL #define LUAN_SMALL_FLASH_SIZE 0x100000 -#define LUAN_LARGE_FLASH_LOW 0x00000001ff800000ULL +#define LUAN_LARGE_FLASH_LOW 0x00000001f9800000ULL #define LUAN_LARGE_FLASH_HIGH 0x00000001ffc00000ULL #define LUAN_LARGE_FLASH_SIZE 0x400000 +#define LUAN_SRAM_HIGH 0x00000001ffe00000ULL +#define LUAN_SRAM_HIGH2 0x00000001fff00000ULL +#define LUAN_SRAM_LOW 0x00000001f9800000ULL +#define LUAN_SRAM_LOW4 0x00000001f9900000ULL +#define LUAN_SRAM_SIZE 0x100000 +#define LUAN_FRAM_ADDR 0x00000001f8060000ULL +#define LUAN_FRAM_SIZE 0x8000 /* * Serial port defines ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2006-03-01 23:57 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2006-03-01 23:35 [PATCH 0/6] AMCC 440SP/Luan board enhancements & fixes Wade Farnsworth 2006-03-01 23:45 ` [PATCH 1/6] Support for UART 2 on 440SP and Luan Wade Farnsworth 2006-03-01 23:47 ` [PATCH 2/6] Add UIC settings for 440SP & Luan Wade Farnsworth 2006-03-01 23:50 ` [PATCH 3/6] PCIX fixes and enhancements " Wade Farnsworth 2006-03-01 23:51 ` [PATCH 4/6] L2 Cache support for 440SP Wade Farnsworth 2006-03-01 23:52 ` [PATCH 5/6] Clock and power management define fixes " Wade Farnsworth 2006-03-01 23:54 ` [PATCH 6/6] MTD defines for Luan Wade Farnsworth
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