From: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
To: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
"Ritesh Harjani (IBM)" <ritesh.list@gmail.com>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Nicholas Piggin <npiggin@gmail.com>,
Praveen K Pandey <praveen@linux.ibm.com>,
Nikhil Kumar Singh <nikhilks@linux.ibm.com>
Subject: Re: [PATCH v2 3/4] powerpc: Add Power12 architected mode
Date: Tue, 4 Aug 2026 11:30:11 +0530 [thread overview]
Message-ID: <anF-LmYhztmpgs1s@linux.ibm.com> (raw)
In-Reply-To: <20260804004514.39870804-35-amachhiw@linux.ibm.com>
On 2026-08-04 00:47:49 Tue, Amit Machhiwal wrote:
> On 2026/08/03 09:27 PM, Mahesh Salgaonkar wrote:
> > From: "Ritesh Harjani (IBM)" <ritesh.list@gmail.com>
> >
> > PVR value of 0x0f000008 means we are arch v3.2 compliant (i.e.
> > Power12). This is used by phyp and kvm when booting as a pseries guest
> > to detect the presence of new Power12 features and to enable the
> > appropriate hwcap and facility bits.
> >
> > Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> > Signed-off-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
> > Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
> > Tested-by: Praveen K Pandey <praveen@linux.ibm.com>
> > Reviewed-by: Nikhil Kumar Singh <nikhilks@linux.ibm.com>
> > ---
> > arch/powerpc/include/asm/prom.h | 1 +
> > arch/powerpc/include/uapi/asm/cputable.h | 1 +
> > arch/powerpc/kernel/cpu_specs_book3s_64.h | 14 ++++++++++++++
> > arch/powerpc/kernel/prom_init.c | 12 ++++++++++--
> > 4 files changed, 26 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
> > index f4991d10d89ec..cd025c7225ee7 100644
> > --- a/arch/powerpc/include/asm/prom.h
> > +++ b/arch/powerpc/include/asm/prom.h
> > @@ -118,6 +118,7 @@ extern unsigned int boot_cpu_node_count;
> >
> > #define OV1_PPC_3_00 0x80 /* set if we support PowerPC 3.00 */
> > #define OV1_PPC_3_1 0x40 /* set if we support PowerPC 3.1 */
> > +#define OV1_PPC_3_2 0x20 /* set if we support PowerPC 3.2 */
>
> Minor: OV1_PPC_3_1 and OV1_PPC_3_2 use extra tabs relative to OV1_PPC_3_00.
> This is pre-existing style inconsistency in the file (not introduced by
> this patch) but new additions should match the surrounding code. Please
> consider aligning them.
This is bit tricky. Prior to 3.0 the ISA versions were 2.05, 2.06, 2.07
and so on and pre-existing style did make sense. But it looks like from
3.1 the style changed may be for a reason because it can not be written
as 3.10 which may create more confusiton. Hence, I plan to stick with
the new style which is introduced from 3.1.
Thanks,
-Mahesh.
next prev parent reply other threads:[~2026-08-04 6:00 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-03 15:57 [PATCH v2 0/4] Base support for Power12 Mahesh Salgaonkar
2026-08-03 15:57 ` [PATCH v2 1/4] powerpc/pseries: Limit PVR list to 16 entries for CAS negotiation Mahesh Salgaonkar
2026-08-03 18:32 ` Amit Machhiwal
2026-08-04 6:42 ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 2/4] powerpc: Add Power12 raw mode Mahesh Salgaonkar
2026-08-03 19:10 ` Amit Machhiwal
2026-08-04 5:52 ` Mahesh J Salgaonkar
2026-08-04 6:13 ` Amit Machhiwal
2026-08-03 15:57 ` [PATCH v2 3/4] powerpc: Add Power12 architected mode Mahesh Salgaonkar
2026-08-03 19:17 ` Amit Machhiwal
2026-08-04 6:00 ` Mahesh J Salgaonkar [this message]
2026-08-04 6:20 ` Amit Machhiwal
2026-08-05 9:32 ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 4/4] powerpc/perf: Add power12 Base Performance Monitoring support Mahesh Salgaonkar
2026-08-03 19:32 ` Amit Machhiwal
2026-08-04 6:34 ` Mahesh J Salgaonkar
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