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From: Mahesh J Salgaonkar <mahesh@linux.ibm.com>
To: linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
	Athira Rajeev <atrajeev@linux.ibm.com>,
	Madhavan Srinivasan <maddy@linux.ibm.com>,
	Praveen K Pandey <praveen@linux.ibm.com>
Subject: Re: [PATCH v2 4/4] powerpc/perf: Add power12 Base Performance Monitoring support
Date: Tue, 4 Aug 2026 12:04:52 +0530	[thread overview]
Message-ID: <anGAwsc1tsjJDdYW@linux.ibm.com> (raw)
In-Reply-To: <20260804010013.56770a8e-e4-amachhiw@linux.ibm.com>

On 2026-08-04 01:02:49 Tue, Amit Machhiwal wrote:
> On 2026/08/03 09:27 PM, Mahesh Salgaonkar wrote:
> > From: Athira Rajeev <atrajeev@linux.ibm.com>
> > 
> > Base enablement patch to register performance monitoring hardware
> > support for power12. Patch introduce the raw event encoding format,
> > defines the supported list of events, config fields for the event
> > attributes and their corresponding bit values which are exported via
> > sysfs.
> > 
> > Signed-off-by: Athira Rajeev <atrajeev@linux.ibm.com>
> > Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
> > Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
> > Tested-by: Praveen K Pandey <praveen@linux.ibm.com>
> > ---
> > Change in v2:
> > - Fix typo reported by Nikhil
> > ---
> >  arch/powerpc/perf/Makefile              |   2 +-
> >  arch/powerpc/perf/core-book3s.c         |   2 +
> >  arch/powerpc/perf/internal.h            |   1 +
> >  arch/powerpc/perf/power12-events-list.h |  78 ++++
> >  arch/powerpc/perf/power12-pmu.c         | 466 ++++++++++++++++++++++++
> >  5 files changed, 548 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/powerpc/perf/power12-events-list.h
> >  create mode 100644 arch/powerpc/perf/power12-pmu.c
> > 
> > diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
> > index 78dd7e25219ee..bcc804c413381 100644
> > --- a/arch/powerpc/perf/Makefile
> > +++ b/arch/powerpc/perf/Makefile
> > @@ -7,7 +7,7 @@ obj-$(CONFIG_PPC_PERF_CTRS)	+= core-book3s.o
> >  obj64-$(CONFIG_PPC_PERF_CTRS)	+= ppc970-pmu.o power5-pmu.o \
> >  				   power5+-pmu.o power6-pmu.o power7-pmu.o \
> >  				   isa207-common.o power8-pmu.o power9-pmu.o \
> > -				   generic-compat-pmu.o power10-pmu.o bhrb.o
> > +				   generic-compat-pmu.o power10-pmu.o bhrb.o power12-pmu.o
> 
> Minor: Line exceeds 80 columns (with tabs expanded). Please wrap
> power12-pmu.o onto its own continuation line aligned with the entries
> above it.

As I mentioned in my response to previous patch, 80 column is no more
hard limit.

Thanks,
-Mahesh.



      reply	other threads:[~2026-08-04  6:35 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-03 15:57 [PATCH v2 0/4] Base support for Power12 Mahesh Salgaonkar
2026-08-03 15:57 ` [PATCH v2 1/4] powerpc/pseries: Limit PVR list to 16 entries for CAS negotiation Mahesh Salgaonkar
2026-08-03 18:32   ` Amit Machhiwal
2026-08-04  6:42     ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 2/4] powerpc: Add Power12 raw mode Mahesh Salgaonkar
2026-08-03 19:10   ` Amit Machhiwal
2026-08-04  5:52     ` Mahesh J Salgaonkar
2026-08-04  6:13       ` Amit Machhiwal
2026-08-03 15:57 ` [PATCH v2 3/4] powerpc: Add Power12 architected mode Mahesh Salgaonkar
2026-08-03 19:17   ` Amit Machhiwal
2026-08-04  6:00     ` Mahesh J Salgaonkar
2026-08-04  6:20       ` Amit Machhiwal
2026-08-05  9:32         ` Mahesh J Salgaonkar
2026-08-03 15:57 ` [PATCH v2 4/4] powerpc/perf: Add power12 Base Performance Monitoring support Mahesh Salgaonkar
2026-08-03 19:32   ` Amit Machhiwal
2026-08-04  6:34     ` Mahesh J Salgaonkar [this message]

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