From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [PATCH v2 21/29] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table
Date: Mon, 17 Mar 2025 17:47:37 +0100 [thread overview]
Message-ID: <20250317164745.4754-22-darwi@linutronix.de> (raw)
In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de>
CPUID leaf 0x2 output is a stream of one-byte descriptors, each implying
certain details about the CPU's cache and TLB entries.
At previous commits, the mapping tables for such descriptors were merged
into one consolidated table. The mapping was also transformed into a
hash lookup instead of a loop-based lookup for each descriptor.
Use the new consolidated table and its hash-based lookup through the
for_each_leaf_0x2_tlb_entry() accessor. Remove the old cache-specific
mapping, cache_table[], as it is no longer used.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
arch/x86/kernel/cpu/cacheinfo.c | 114 +++-----------------------------
1 file changed, 8 insertions(+), 106 deletions(-)
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 9f5bf57fd4fc..0047a41d8d57 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -34,90 +34,6 @@ static cpumask_var_t cpu_cacheinfo_mask;
/* Kernel controls MTRR and/or PAT MSRs. */
unsigned int memory_caching_control __ro_after_init;
-struct _cache_table {
- unsigned char descriptor;
- enum _cache_table_type type;
- short size;
-};
-
-#define MB(x) ((x) * 1024)
-
-/* All the cache descriptor types we care about (no TLB or
- trace cache entries) */
-
-static const struct _cache_table cache_table[] =
-{
- { 0x06, CACHE_L1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
- { 0x08, CACHE_L1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
- { 0x09, CACHE_L1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
- { 0x0a, CACHE_L1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
- { 0x0c, CACHE_L1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
- { 0x0d, CACHE_L1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
- { 0x0e, CACHE_L1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
- { 0x21, CACHE_L2, 256 }, /* 8-way set assoc, 64 byte line size */
- { 0x22, CACHE_L3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x23, CACHE_L3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x25, CACHE_L3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x29, CACHE_L3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x2c, CACHE_L1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
- { 0x30, CACHE_L1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
- { 0x39, CACHE_L2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x3a, CACHE_L2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
- { 0x3b, CACHE_L2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
- { 0x3c, CACHE_L2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x3d, CACHE_L2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
- { 0x3e, CACHE_L2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x3f, CACHE_L2, 256 }, /* 2-way set assoc, 64 byte line size */
- { 0x41, CACHE_L2, 128 }, /* 4-way set assoc, 32 byte line size */
- { 0x42, CACHE_L2, 256 }, /* 4-way set assoc, 32 byte line size */
- { 0x43, CACHE_L2, 512 }, /* 4-way set assoc, 32 byte line size */
- { 0x44, CACHE_L2, MB(1) }, /* 4-way set assoc, 32 byte line size */
- { 0x45, CACHE_L2, MB(2) }, /* 4-way set assoc, 32 byte line size */
- { 0x46, CACHE_L3, MB(4) }, /* 4-way set assoc, 64 byte line size */
- { 0x47, CACHE_L3, MB(8) }, /* 8-way set assoc, 64 byte line size */
- { 0x48, CACHE_L2, MB(3) }, /* 12-way set assoc, 64 byte line size */
- { 0x49, CACHE_L3, MB(4) }, /* 16-way set assoc, 64 byte line size */
- { 0x4a, CACHE_L3, MB(6) }, /* 12-way set assoc, 64 byte line size */
- { 0x4b, CACHE_L3, MB(8) }, /* 16-way set assoc, 64 byte line size */
- { 0x4c, CACHE_L3, MB(12) }, /* 12-way set assoc, 64 byte line size */
- { 0x4d, CACHE_L3, MB(16) }, /* 16-way set assoc, 64 byte line size */
- { 0x4e, CACHE_L2, MB(6) }, /* 24-way set assoc, 64 byte line size */
- { 0x60, CACHE_L1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x66, CACHE_L1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x67, CACHE_L1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x68, CACHE_L1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
- { 0x78, CACHE_L2, MB(1) }, /* 4-way set assoc, 64 byte line size */
- { 0x79, CACHE_L2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x7a, CACHE_L2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x7b, CACHE_L2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x7c, CACHE_L2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
- { 0x7d, CACHE_L2, MB(2) }, /* 8-way set assoc, 64 byte line size */
- { 0x7f, CACHE_L2, 512 }, /* 2-way set assoc, 64 byte line size */
- { 0x80, CACHE_L2, 512 }, /* 8-way set assoc, 64 byte line size */
- { 0x82, CACHE_L2, 256 }, /* 8-way set assoc, 32 byte line size */
- { 0x83, CACHE_L2, 512 }, /* 8-way set assoc, 32 byte line size */
- { 0x84, CACHE_L2, MB(1) }, /* 8-way set assoc, 32 byte line size */
- { 0x85, CACHE_L2, MB(2) }, /* 8-way set assoc, 32 byte line size */
- { 0x86, CACHE_L2, 512 }, /* 4-way set assoc, 64 byte line size */
- { 0x87, CACHE_L2, MB(1) }, /* 8-way set assoc, 64 byte line size */
- { 0xd0, CACHE_L3, 512 }, /* 4-way set assoc, 64 byte line size */
- { 0xd1, CACHE_L3, MB(1) }, /* 4-way set assoc, 64 byte line size */
- { 0xd2, CACHE_L3, MB(2) }, /* 4-way set assoc, 64 byte line size */
- { 0xd6, CACHE_L3, MB(1) }, /* 8-way set assoc, 64 byte line size */
- { 0xd7, CACHE_L3, MB(2) }, /* 8-way set assoc, 64 byte line size */
- { 0xd8, CACHE_L3, MB(4) }, /* 12-way set assoc, 64 byte line size */
- { 0xdc, CACHE_L3, MB(2) }, /* 12-way set assoc, 64 byte line size */
- { 0xdd, CACHE_L3, MB(4) }, /* 12-way set assoc, 64 byte line size */
- { 0xde, CACHE_L3, MB(8) }, /* 12-way set assoc, 64 byte line size */
- { 0xe2, CACHE_L3, MB(2) }, /* 16-way set assoc, 64 byte line size */
- { 0xe3, CACHE_L3, MB(4) }, /* 16-way set assoc, 64 byte line size */
- { 0xe4, CACHE_L3, MB(8) }, /* 16-way set assoc, 64 byte line size */
- { 0xea, CACHE_L3, MB(12) }, /* 24-way set assoc, 64 byte line size */
- { 0xeb, CACHE_L3, MB(18) }, /* 24-way set assoc, 64 byte line size */
- { 0xec, CACHE_L3, MB(24) }, /* 24-way set assoc, 64 byte line size */
-};
-
-
enum _cache_type {
CTYPE_NULL = 0,
CTYPE_DATA = 1,
@@ -436,16 +352,6 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
ci->num_leaves = find_num_cache_leaves(c);
}
-static const struct _cache_table *cache_table_get(u8 desc)
-{
- for (int i = 0; i < ARRAY_SIZE(cache_table); i++) {
- if (cache_table[i].descriptor == desc)
- return &cache_table[i];
- }
-
- return NULL;
-}
-
void init_intel_cacheinfo(struct cpuinfo_x86 *c)
{
/* Cache sizes */
@@ -502,21 +408,17 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)
/* Don't use CPUID(2) if CPUID(4) is supported. */
if (!ci->num_leaves && c->cpuid_level > 1) {
- const struct _cache_table *entry;
+ const struct leaf_0x2_table *entry;
union leaf_0x2_regs regs;
- u8 *desc;
+ u8 *ptr;
cpuid_get_leaf_0x2_regs(®s);
- for_each_leaf_0x2_desc(regs, desc) {
- entry = cache_table_get(*desc);
- if (!entry)
- continue;
-
- switch (entry->type) {
- case CACHE_L1_INST: l1i += entry->size; break;
- case CACHE_L1_DATA: l1d += entry->size; break;
- case CACHE_L2: l2 += entry->size; break;
- case CACHE_L3: l3 += entry->size; break;
+ for_each_leaf_0x2_entry(regs, ptr, entry) {
+ switch (entry->c_type) {
+ case CACHE_L1_INST: l1i += entry->c_size; break;
+ case CACHE_L1_DATA: l1d += entry->c_size; break;
+ case CACHE_L2: l2 += entry->c_size; break;
+ case CACHE_L3: l3 += entry->c_size; break;
}
}
}
--
2.48.1
next prev parent reply other threads:[~2025-03-17 16:53 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-17 16:47 [PATCH v2 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-17 17:32 ` Borislav Petkov
2025-03-17 17:48 ` Peter Zijlstra
2025-03-17 18:10 ` Andrew Cooper
2025-03-17 18:34 ` H. Peter Anvin
2025-03-17 18:11 ` Dave Hansen
2025-03-17 18:21 ` H. Peter Anvin
2025-03-17 18:34 ` Borislav Petkov
2025-03-18 11:07 ` Ahmed S. Darwish
2025-03-19 14:47 ` H. Peter Anvin
2025-03-20 10:47 ` Ahmed S. Darwish
2025-03-17 21:42 ` Ingo Molnar
2025-03-17 21:46 ` Borislav Petkov
2025-03-17 16:47 ` [PATCH v2 02/29] x86/cpuid: Refactor <asm/cpuid.h> Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 03/29] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-17 21:36 ` Ingo Molnar
2025-03-18 11:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 04/29] x86/cacheinfo: Use CPUID leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 05/29] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 06/29] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 08/29] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 09/29] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 11/29] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 12/29] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 13/29] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 14/29] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 15/29] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 16/29] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 17/29] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 18/29] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-19 14:11 ` kernel test robot
2025-03-19 16:09 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 19/29] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-19 16:09 ` kernel test robot
2025-03-19 16:16 ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 20/29] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-17 16:47 ` Ahmed S. Darwish [this message]
2025-03-17 16:47 ` [PATCH v2 22/29] x86/cpu: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 24/29] x86/cacheinfo: Separate Intel leaf 0x4 handling Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 25/29] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 26/29] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 27/29] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 28/29] x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
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