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From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Borislav Petkov <bp@alien8.de>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	John Ogness <john.ogness@linutronix.de>,
	x86@kernel.org, x86-cpuid@lists.linux.dev,
	LKML <linux-kernel@vger.kernel.org>,
	"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: [PATCH v2 06/29] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter
Date: Mon, 17 Mar 2025 17:47:22 +0100	[thread overview]
Message-ID: <20250317164745.4754-7-darwi@linutronix.de> (raw)
In-Reply-To: <20250317164745.4754-1-darwi@linutronix.de>

From: Thomas Gleixner <tglx@linutronix.de>

amd_cpuid4()'s first parameter, "leaf", is not a CPUID leaf as the name
implies.  Rather, it's an index emulating CPUID(4)'s subleaf semantics;
i.e. an ID for the cache object currently enumerated.  Rename that
parameter to "index".

Apply minor coding style fixes to the rest of the function as well.

[ darwi: Move into a separate commit and write commit log.
	 Use "index" instead of "subleaf" for amd_cpuid4() first param,
	 as that's the name typically used at the whole of cacheinfo.c. ]

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 15 ++++++---------
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 44bc044aa9a2..64effa2d7674 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -233,12 +233,10 @@ static const enum cache_type cache_type_map[] = {
 };
 
 static void
-amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
-		     union _cpuid4_leaf_ebx *ebx,
-		     union _cpuid4_leaf_ecx *ecx)
+amd_cpuid4(int index, union _cpuid4_leaf_eax *eax,
+	   union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx)
 {
-	unsigned dummy;
-	unsigned line_size, lines_per_tag, assoc, size_in_kb;
+	unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb;
 	union l1_cache l1i, l1d;
 	union l2_cache l2;
 	union l3_cache l3;
@@ -251,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
 	cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
 
-	switch (leaf) {
+	switch (index) {
 	case 1:
 		l1 = &l1i;
 		fallthrough;
@@ -289,12 +287,11 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
 	}
 
 	eax->split.is_self_initializing = 1;
-	eax->split.type = types[leaf];
-	eax->split.level = levels[leaf];
+	eax->split.type = types[index];
+	eax->split.level = levels[index];
 	eax->split.num_threads_sharing = 0;
 	eax->split.num_cores_on_die = topology_num_cores_per_package();
 
-
 	if (assoc == 0xffff)
 		eax->split.is_fully_associative = 1;
 	ebx->split.coherency_line_size = line_size - 1;
-- 
2.48.1


  parent reply	other threads:[~2025-03-17 16:52 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-17 16:47 [PATCH v2 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 01/29] x86: treewide: Introduce x86_vendor_amd_or_hygon() Ahmed S. Darwish
2025-03-17 17:32   ` Borislav Petkov
2025-03-17 17:48     ` Peter Zijlstra
2025-03-17 18:10       ` Andrew Cooper
2025-03-17 18:34         ` H. Peter Anvin
2025-03-17 18:11       ` Dave Hansen
2025-03-17 18:21         ` H. Peter Anvin
2025-03-17 18:34           ` Borislav Petkov
2025-03-18 11:07     ` Ahmed S. Darwish
2025-03-19 14:47       ` H. Peter Anvin
2025-03-20 10:47         ` Ahmed S. Darwish
2025-03-17 21:42   ` Ingo Molnar
2025-03-17 21:46     ` Borislav Petkov
2025-03-17 16:47 ` [PATCH v2 02/29] x86/cpuid: Refactor <asm/cpuid.h> Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 03/29] x86/cpu: Remove leaf 0x2 parsing loop and add helpers Ahmed S. Darwish
2025-03-17 21:36   ` Ingo Molnar
2025-03-18 11:09     ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 04/29] x86/cacheinfo: Use CPUID leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 05/29] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-17 16:47 ` Ahmed S. Darwish [this message]
2025-03-17 16:47 ` [PATCH v2 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 08/29] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 09/29] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 11/29] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 12/29] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 13/29] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 14/29] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 15/29] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 16/29] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 17/29] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 18/29] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-19 14:11   ` kernel test robot
2025-03-19 16:09     ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 19/29] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-19 16:09   ` kernel test robot
2025-03-19 16:16     ` Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 20/29] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 21/29] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 22/29] x86/cpu: " Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 24/29] x86/cacheinfo: Separate Intel leaf 0x4 handling Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 25/29] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 26/29] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 27/29] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 28/29] x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() Ahmed S. Darwish
2025-03-17 16:47 ` [PATCH v2 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish

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