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From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
	namhyung@kernel.org, tglx@linutronix.de,
	dave.hansen@linux.intel.com, irogers@google.com,
	adrian.hunter@intel.com, jolsa@kernel.org,
	alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org
Cc: dapeng1.mi@linux.intel.com, ak@linux.intel.com,
	zide.chen@intel.com, mark.rutland@arm.com, broonie@kernel.org,
	ravi.bangoria@amd.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [RFC PATCH V2 02/13] perf/x86: Setup the regs data
Date: Thu, 26 Jun 2025 12:55:59 -0700	[thread overview]
Message-ID: <20250626195610.405379-3-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20250626195610.405379-1-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

The current code relies on the generic code to setup the regs data.
It will not work well when there are more regs introduced.
Introduce a X86-specific x86_pmu_setup_regs_data().
Now, it's the same as the generic code. More X86-specific codes will be
added later when the new regs.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/core.c       | 32 ++++++++++++++++++++++++++++++++
 arch/x86/events/intel/ds.c   |  4 +++-
 arch/x86/events/perf_event.h |  4 ++++
 3 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 64a7a8aa2e38..c601ad761534 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1685,6 +1685,38 @@ static void x86_pmu_del(struct perf_event *event, int flags)
 	static_call_cond(x86_pmu_del)(event);
 }
 
+void x86_pmu_setup_regs_data(struct perf_event *event,
+			     struct perf_sample_data *data,
+			     struct pt_regs *regs)
+{
+	u64 sample_type = event->attr.sample_type;
+
+	if (sample_type & PERF_SAMPLE_REGS_USER) {
+		if (user_mode(regs)) {
+			data->regs_user.abi = perf_reg_abi(current);
+			data->regs_user.regs = regs;
+		} else if (!(current->flags & PF_KTHREAD)) {
+			perf_get_regs_user(&data->regs_user, regs);
+		} else {
+			data->regs_user.abi = PERF_SAMPLE_REGS_ABI_NONE;
+			data->regs_user.regs = NULL;
+		}
+		data->dyn_size += sizeof(u64);
+		if (data->regs_user.regs)
+			data->dyn_size += hweight64(event->attr.sample_regs_user) * sizeof(u64);
+		data->sample_flags |= PERF_SAMPLE_REGS_USER;
+	}
+
+	if (sample_type & PERF_SAMPLE_REGS_INTR) {
+		data->regs_intr.regs = regs;
+		data->regs_intr.abi = perf_reg_abi(current);
+		data->dyn_size += sizeof(u64);
+		if (data->regs_intr.regs)
+			data->dyn_size += hweight64(event->attr.sample_regs_intr) * sizeof(u64);
+		data->sample_flags |= PERF_SAMPLE_REGS_INTR;
+	}
+}
+
 int x86_pmu_handle_irq(struct pt_regs *regs)
 {
 	struct perf_sample_data data;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index c0b7ac1c7594..e67d8a03ddfe 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2126,8 +2126,10 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event,
 			regs->flags &= ~PERF_EFLAGS_EXACT;
 		}
 
-		if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER))
+		if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) {
 			adaptive_pebs_save_regs(regs, gprs);
+			x86_pmu_setup_regs_data(event, data, regs);
+		}
 	}
 
 	if (format_group & PEBS_DATACFG_MEMINFO) {
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2b969386dcdd..12682a059608 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1278,6 +1278,10 @@ void x86_pmu_enable_event(struct perf_event *event);
 
 int x86_pmu_handle_irq(struct pt_regs *regs);
 
+void x86_pmu_setup_regs_data(struct perf_event *event,
+			     struct perf_sample_data *data,
+			     struct pt_regs *regs);
+
 void x86_pmu_show_pmu_cap(struct pmu *pmu);
 
 static inline int x86_pmu_num_counters(struct pmu *pmu)
-- 
2.38.1


  parent reply	other threads:[~2025-06-26 19:56 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-26 19:55 [RFC PATCH V2 00/13] Support vector and more extended registers in perf kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 01/13] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-26 19:55 ` kan.liang [this message]
2025-06-26 19:56 ` [RFC PATCH V2 03/13] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-07-02  0:18   ` Chang S. Bae
2025-07-07 18:12     ` Liang, Kan
2025-07-07 18:17       ` Dave Hansen
2025-06-26 19:56 ` [RFC PATCH V2 04/13] perf: Move has_extended_regs() to header file kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-27 14:35   ` Dave Hansen
2025-06-27 21:23     ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 06/13] perf: Support SIMD registers kan.liang
2025-07-02 11:16   ` Mark Brown
2025-07-07 18:12     ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 07/13] perf/x86: Move XMM to sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 08/13] perf/x86: Add YMM into sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 09/13] perf/x86: Add ZMM " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 10/13] perf/x86: Add OPMASK into sample_simd_pred_reg kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 11/13] perf/x86: Add eGPRs into sample_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 12/13] perf/x86: Add SSP " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 13/13] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS kan.liang

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