From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, tglx@linutronix.de,
dave.hansen@linux.intel.com, irogers@google.com,
adrian.hunter@intel.com, jolsa@kernel.org,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org
Cc: dapeng1.mi@linux.intel.com, ak@linux.intel.com,
zide.chen@intel.com, mark.rutland@arm.com, broonie@kernel.org,
ravi.bangoria@amd.com
Subject: Re: [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER
Date: Fri, 27 Jun 2025 17:23:15 -0400 [thread overview]
Message-ID: <d50b0407-c006-48c0-98dc-37d428d5aacf@linux.intel.com> (raw)
In-Reply-To: <b894739e-a0e1-4451-92c5-8bc577d3979b@intel.com>
On 2025-06-27 10:35 a.m., Dave Hansen wrote:
> On 6/26/25 12:56, kan.liang@linux.intel.com wrote:
>> +static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
>> +{
>> + struct xregs_state *xsave = per_cpu(ext_regs_buf, smp_processor_id());
>> +
>> + if (WARN_ON_ONCE(!xsave))
>> + return;
>> +
>> + xsaves_nmi(xsave, mask);
>
> This makes me a little nervous.
>
> Could we maybe keep a mask around that reminds us what 'ext_regs_buf'
> was sized for and then ensure that no bits in the passed-in mask are set
> in that?
>
The x86_pmu.ext_regs_mask tracks the available bits of
x86_pmu.ext_regs_buf. But it has its own format.
I will make it use the XSAVE format, and add a check here.
> I almost wonder if you want to add a
>
> struct fpu_state_config fpu_perf_cfg;
>
> I guess it's mostly overkill for this. But please do have a look at the
> data structures in:
>
> arch/x86/include/asm/fpu/types.h
>
It looks overkill. The perf usage is simple. It should be good enough to
have one mask to track the available bits. The size is from FPU's
xstate_calculate_size(). I think, as long as perf inputs the correct
mask, the size can be trusted.
>> + if (mask & XFEATURE_MASK_SSE &&
>> + xsave->header.xfeatures & BIT_ULL(XFEATURE_SSE))
>> + perf_regs->xmm_space = xsave->i387.xmm_space;
>> +}
>
> There's a lot going on here.
>
> 'mask' and 'xfeatures' have the exact same format. Why use
> XFEATURE_MASK_SSE for one and BIT_ULL(XFEATURE_SSE) for the other?
>
Ah, my bad. The same XFEATURE_MASK_SSE should be used.
> Why check both? How could a bit get into 'xfeatures' without being in
> 'mask'?
The 'mask' is what perf wants/configures. I think the 'xfeatures' is
what XSAVE really gives. I'm not quite sure if HW can always give us
everything we configured. If not, I think both checks are required.
I'm thinking to add the below first.
valid_mask = x86_pmu.ext_regs_mask & mask & xsave->header.xfeatures;
Then only use the valid_mask to check each XFEATURE.
>
> How does the caller handle the fact that ->xmm_space might be written or
> not?
>
For this series, the returned XMM value is zeroed if the ->xmm_space is
NULL.
But I should clear the nr_vectors. So nothing will be dumped to the
userspace if the ->xmm_space is not available. I will address it in V3.
Thanks,
Kan
next prev parent reply other threads:[~2025-06-27 21:23 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 19:55 [RFC PATCH V2 00/13] Support vector and more extended registers in perf kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 01/13] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 02/13] perf/x86: Setup the regs data kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 03/13] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-07-02 0:18 ` Chang S. Bae
2025-07-07 18:12 ` Liang, Kan
2025-07-07 18:17 ` Dave Hansen
2025-06-26 19:56 ` [RFC PATCH V2 04/13] perf: Move has_extended_regs() to header file kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-27 14:35 ` Dave Hansen
2025-06-27 21:23 ` Liang, Kan [this message]
2025-06-26 19:56 ` [RFC PATCH V2 06/13] perf: Support SIMD registers kan.liang
2025-07-02 11:16 ` Mark Brown
2025-07-07 18:12 ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 07/13] perf/x86: Move XMM to sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 08/13] perf/x86: Add YMM into sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 09/13] perf/x86: Add ZMM " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 10/13] perf/x86: Add OPMASK into sample_simd_pred_reg kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 11/13] perf/x86: Add eGPRs into sample_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 12/13] perf/x86: Add SSP " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 13/13] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS kan.liang
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