Re: [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER

[Dave Hansen <dave.hansen@intel.com>]

On 6/26/25 12:56, kan.liang@linux.intel.com wrote:
> +static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
> +{
> +	struct xregs_state *xsave = per_cpu(ext_regs_buf, smp_processor_id());
> +
> +	if (WARN_ON_ONCE(!xsave))
> +		return;
> +
> +	xsaves_nmi(xsave, mask);

This makes me a little nervous.

Could we maybe keep a mask around that reminds us what 'ext_regs_buf'
was sized for and then ensure that no bits in the passed-in mask are set
in that?

I almost wonder if you want to add a

	struct fpu_state_config fpu_perf_cfg;

I guess it's mostly overkill for this. But please do have a look at the
data structures in:

	arch/x86/include/asm/fpu/types.h

> +	if (mask & XFEATURE_MASK_SSE &&
> +	    xsave->header.xfeatures & BIT_ULL(XFEATURE_SSE))
> +		perf_regs->xmm_space = xsave->i387.xmm_space;
> +}

There's a lot going on here.

'mask' and 'xfeatures' have the exact same format. Why use
XFEATURE_MASK_SSE for one and BIT_ULL(XFEATURE_SSE) for the other?

Why check both? How could a bit get into 'xfeatures' without being in
'mask'?

How does the caller handle the fact that ->xmm_space might be written or
not?