From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Mark Brown <broonie@kernel.org>
Cc: peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, tglx@linutronix.de,
dave.hansen@linux.intel.com, irogers@google.com,
adrian.hunter@intel.com, jolsa@kernel.org,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org,
dapeng1.mi@linux.intel.com, ak@linux.intel.com,
zide.chen@intel.com, mark.rutland@arm.com, ravi.bangoria@amd.com
Subject: Re: [RFC PATCH V2 06/13] perf: Support SIMD registers
Date: Mon, 7 Jul 2025 11:12:32 -0700 [thread overview]
Message-ID: <94d2de81-47e4-4ad1-ab92-cfacdab3cf68@linux.intel.com> (raw)
In-Reply-To: <69afb239-da54-452d-8ab4-2d80dbdf8dce@sirena.org.uk>
On 2025-07-02 4:16 a.m., Mark Brown wrote:
> On Thu, Jun 26, 2025 at 12:56:03PM -0700, kan.liang@linux.intel.com wrote:
>
>> * { u64 abi; # enum perf_sample_regs_abi
>> - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER
>> + * u64 regs[weight(mask)];
>> + * struct {
>> + * u16 nr_vectors;
>> + * u16 vector_qwords;
>> + * u16 nr_pred;
>> + * u16 pred_qwords;
>> + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords];
>> + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD)
>> + * } && PERF_SAMPLE_REGS_USER
>
> I'm not super familiar with perf but I think this should work for arm64,
> it supplies the vector length through the _qwords and we can handle FFR
> being optional by varying the number of predicate registers.
That's great. Thanks for the confirmation.
Thanks,
Kan
next prev parent reply other threads:[~2025-07-07 18:12 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 19:55 [RFC PATCH V2 00/13] Support vector and more extended registers in perf kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 01/13] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-26 19:55 ` [RFC PATCH V2 02/13] perf/x86: Setup the regs data kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 03/13] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-07-02 0:18 ` Chang S. Bae
2025-07-07 18:12 ` Liang, Kan
2025-07-07 18:17 ` Dave Hansen
2025-06-26 19:56 ` [RFC PATCH V2 04/13] perf: Move has_extended_regs() to header file kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 05/13] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-27 14:35 ` Dave Hansen
2025-06-27 21:23 ` Liang, Kan
2025-06-26 19:56 ` [RFC PATCH V2 06/13] perf: Support SIMD registers kan.liang
2025-07-02 11:16 ` Mark Brown
2025-07-07 18:12 ` Liang, Kan [this message]
2025-06-26 19:56 ` [RFC PATCH V2 07/13] perf/x86: Move XMM to sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 08/13] perf/x86: Add YMM into sample_simd_vec_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 09/13] perf/x86: Add ZMM " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 10/13] perf/x86: Add OPMASK into sample_simd_pred_reg kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 11/13] perf/x86: Add eGPRs into sample_regs kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 12/13] perf/x86: Add SSP " kan.liang
2025-06-26 19:56 ` [RFC PATCH V2 13/13] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS kan.liang
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